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Subversion Repositories async_sdm_noc

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  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches/init/vc/src
    from Rev 42 to Rev 45
    ↔ Reverse comparison
  •

Rev 42 → Rev 45

/router.v
27,7 → 27,7
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rstn
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rst_n
);
 
parameter VCN = 2; // number of VCs per direction
65,7 → 65,7
// local address, in 1-of-4 format
input [7:0] addrx, addry;
// active-low reset
input rstn;
input rst_n;
 
//----------------------------------
// input to crossbar
129,7 → 129,7
.swrt ( siswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// west input buffer
157,7 → 157,7
.swrt ( wiswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
.rst_n ( rst_n )
);
// north input buffer
185,7 → 185,7
.swrt ( niswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
.rst_n ( rst_n )
);
// east input buffer
213,7 → 213,7
.swrt ( eiswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
.rst_n ( rst_n )
);
// local input buffer
241,7 → 241,7
.swrt ( liswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// south output buffer
264,7 → 264,7
.doa ( soa ),
.credit( soc ),
.vcr ( soswr ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// west output buffer
287,7 → 287,7
.doa ( woa ),
.credit( woc ),
.vcr ( woswr ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// north output buffer
310,7 → 310,7
.doa ( noa ),
.credit( noc ),
.vcr ( noswr ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// east output buffer
333,7 → 333,7
.doa ( eoa ),
.credit( eoc ),
.vcr ( eoswr ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// east output buffer
356,7 → 356,7
.doa ( loa ),
.credit( loc ),
.vcr ( loswr ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// VC allocator
392,7 → 392,7
.nosa ( noswa ),
.eosa ( eoswa ),
.losa ( loswa ),
.rstn ( rstn )
.rst_n ( rst_n )
);
 
// crossbar
/inpbuf.v
24,7 → 24,7
dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
// Inputs
di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
rstn
rst_n
);
 
parameter DW = 32; // data width
64,7 → 64,7
// local addresses
input [7:0] addrx, addry;
 
input rstn;
input rst_n;
 
//-----------------------------
// VC_MUX
117,12 → 117,12
//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
assign di0m = rstn ? di0 : 0;
assign di1m = rstn ? di1 : 0;
assign di2m = rstn ? di2 : 0;
assign di3m = rstn ? di3 : 0;
assign ditm = rstn ? dit : 0;
assign divcm = rstn ? divc : 0;
assign di0m = rst_n ? di0 : 0;
assign di1m = rst_n ? di1 : 0;
assign di2m = rst_n ? di2 : 0;
assign di3m = rst_n ? di3 : 0;
assign ditm = rst_n ? dit : 0;
assign divcm = rst_n ? divc : 0;
 
//---------------------------------------------
// the VC buffers
143,7 → 143,7
.i3 ( vcd3[gbd][gvc][gsub] ),
.oa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
end // block: SC
pipen #(.DW(FT))
153,7 → 153,7
.d_out ( vcdt[gbd+1][gvc] ),
.d_out_a ( vcdatn[gbd+1][gvc] )
);
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rstn;
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
end // block: V
end // block: BFN
188,7 → 188,7
.i3 ( vcd3[gbd][gvc][gsub] ),
.oa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rst_n;
end // block: SC
pipen #(.DW(FT))
199,7 → 199,7
.d_out_a ( vcdatn[gbd+1][gvc] )
);
 
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rstn;
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rst_n;
 
pipen #(.DW(2))
CTP (
209,7 → 209,7
.d_out_a ( vcftan[gbd+1][gvc] )
);
 
assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rstn;
assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rst_n;
end // block: V
end // block: BFL2
 
233,7 → 233,7
.d_in ( swrt[gvc] ),
.d_in_a ( swa[gvc] ),
.d_out ( rtg[gvc] ),
.d_out_a ( (~vcda[1][gvc])&rstn )
.d_out_a ( (~vcda[1][gvc])&rst_n )
);
end
endgenerate
242,7 → 242,7
for(gvc=0; gvc<VCN; gvc++) begin:LPS
 
// credit control
dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rstn));
dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rst_n));
 
// output name conversation
assign do0[gvc] = vcd0[PD*2][gvc];
263,7 → 263,7
RTC (
.dia ( rua ),
.dort ( vcr ),
.rstn ( rstn ),
.rst_n ( rst_n ),
.di0 ( di0m[3:0] ),
.di1 ( di1m[3:0] ),
.di2 ( di2m[3:0] ),
/outpbuf.v
23,7 → 23,7
// Outputs
dia, do0, do1, do2, do3, dot, dovc, afc, vca,
// Inputs
di0, di1, di2, di3, dit, doa, credit, vcr, rstn
di0, di1, di2, di3, dit, doa, credit, vcr, rst_n
);
parameter DW = 32; // data width
parameter VCN = 4; // VC number
51,7 → 51,7
output [VCN-1:0] vca;
 
// active-low reset
input rstn;
input rst_n;
 
//--------------------------------------------------------------
wire [VCN-1:0] vcro, vcg, vcgl, vcrm;
67,7 → 67,7
.ro ( vcro ),
.credit ( credit ),
.ri ( vcr ),
.rst ( ~rstn )
.rst ( ~rst_n )
);
 
// VC arbiter
79,7 → 79,7
c2 C (.a0(vcg[i]), .a1(diavcn), .q(vcgl[i]));
end
endgenerate
assign diavcn = (~diavc)&rstn;
assign diavcn = (~diavc)&rst_n;
 
// output data buffer
generate
97,7 → 97,7
.i3 ( di3[gsub] ),
.oa ( doan[gsub] )
);
assign doan[gsub] = (~doa)&rstn;
assign doan[gsub] = (~doa)&rst_n;
end // block: SC
endgenerate
 
106,7 → 106,7
.d_in ( dit ),
.d_in_a ( diat ),
.d_out ( dot ),
.d_out_a ( (~doa)&rstn )
.d_out_a ( (~doa)&rst_n )
);
ctree #(.DW(SCN+2)) ACKT (.ci({diavc,diat, diad}), .co(dia));
116,7 → 116,7
.d_in ( vcgl ),
.d_in_a ( diavc ),
.d_out ( dovc ),
.d_out_a ( (~doa)&rstn )
.d_out_a ( (~doa)&rst_n )
);
 
assign vca = dovc;
/vca.v
28,7 → 28,7
sosr, wosr, nosr, eosr, losr,
// Inputs
svcr, nvcr, lvcr, wvcr, evcr, sswr, wswr, nswr, eswr, lswr, sosa,
wosa, nosa, eosa, losa, rstn
wosa, nosa, eosa, losa, rst_n
);
 
parameter VCN = 4; // number of VCs
44,7 → 44,7
output [VCN-1:0] sosr, wosr, nosr, eosr, losr; // SW requests to output VCs
input [VCN-1:0] sosa, wosa, nosa, eosa, losa;
input rstn; // active-low reset
input rst_n; // active-low reset
wire [VCN-1:0][3:0] msvcr, mnvcr, mlvcr; // shuffled VC requests
wire [VCN-1:0][1:0] mwvcr, mevcr;
98,22 → 98,22
assign evcra[i] = {evcrai[i][0]|evcrai[i][1]};
assign lvcra[i] = {lvcrai[i][0]|lvcrai[i][1]|lvcrai[i][2]|lvcrai[i][3]};
or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rstn);
or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rstn);
or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rstn);
or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rstn);
or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rstn);
or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rstn);
or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rstn);
or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rstn);
or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rstn);
or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rstn);
or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rstn);
or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rstn);
or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rstn);
or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rstn);
or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rstn);
or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rstn);
or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rst_n);
or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rst_n);
or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rst_n);
or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rst_n);
or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rst_n);
or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rst_n);
or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rst_n);
or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rst_n);
or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rst_n);
or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rst_n);
or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rst_n);
or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rst_n);
or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rst_n);
or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rst_n);
or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rst_n);
or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rst_n);
 
and VCAOs0 (svcrai[i][0], (|svcrami[i][0]), svcraii[i][0]);
and VCAOs1 (svcrai[i][1], (|svcrami[i][1]), svcraii[i][1]);
309,7 → 309,7
.ca ( ),
.r ( svcrdy ),
.ra ( svcrdya ),
.rst_n ( rstn )
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
319,7 → 319,7
.ca ( ),
.r ( wvcrdy ),
.ra ( wvcrdya ),
.rst_n ( rstn )
.rst_n ( rst_n )
);
mrma #(.N(2*VCN), .M(VCN))
329,7 → 329,7
.ca ( ),
.r ( nvcrdy ),
.ra ( nvcrdya ),
.rst_n ( rstn )
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
339,7 → 339,7
.ca ( ),
.r ( evcrdy ),
.ra ( evcrdya ),
.rst_n ( rstn )
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
349,7 → 349,7
.ca ( ),
.r ( lvcrdy ),
.ra ( lvcrdya ),
.rst_n ( rstn )
.rst_n ( rst_n )
);
 
generate
/rtu.v
22,7 → 22,7
// Outputs
dia, dort,
// Inputs
rstn, di0, di1, di2, di3, dit, divc, addrx, addry, doa
rst_n, di0, di1, di2, di3, dit, divc, addrx, addry, doa
);
parameter VCN = 2;
parameter DIR = 0;
29,7 → 29,7
parameter SN = 4;
parameter PD = 2;
 
input rstn;
input rst_n;
input [3:0] di0, di1, di2, di3;
input [2:0] dit;
input [VCN-1:0] divc;
124,7 → 124,7
// p2 -> L -> p3
 
c2 CP2A ( .a0(p2ad), .a1(p2avc), .q(p2a));
assign p2an = (~p2a) & rstn;
assign p2an = (~p2a) & rst_n;
 
pipen #(.DW(SN))
L2R (
152,7 → 152,7
.d_out_a ( pda[0])
);
 
assign p3an = (~p3a) & rstn;
assign p3an = (~p3a) & rst_n;
 
// pd pipeline
generate
165,7 → 165,7
.d_out ( pd[gbd+1][gvc] ),
.d_out_a ( pdan[gbd+1][gvc] )
);
assign pdan[gbd+1][gvc] = (~pda[gbd+1][gvc])&rstn;
assign pdan[gbd+1][gvc] = (~pda[gbd+1][gvc])&rst_n;
end
end // block: RT
endgenerate

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