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URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches/init/vc/tb
    from Rev 44 to Rev 45
    ↔ Reverse comparison
  •

Rev 44 → Rev 45

/rtdriver.cpp
28,9 → 28,7
rtica("rtica"),
rtoa("rtoa"),
rtoc("rtoc"),
rtoca("rtoca"),
IPD("VCIP"),
OPD("VCOP")
rtoca("rtoca")
{
SC_METHOD(IPdetect);
sensitive << rtia;
50,10 → 48,6
 
rtinp_sig = false;
rtoutp_sig = false;
 
sc_spawn_options th_opt;
for(unsigned int i=0; i<SubChN; i++)
sc_spawn(sc_bind(&RTDriver::credit, this, i), NULL, &th_opt);
}
void RTDriver::IPdetect() {
72,10 → 66,14
void RTDriver::OPdetect() {
sc_lv<ChBW*4> data_lv; // the ORed data
sc_logic data_lv_high, data_lv_low;
sc_lv<SubChN> vc_lv; // the local copy of vc number
sc_lv<3> ft_lv; // the local copy of flit type
 
data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read();
data_lv_high = data_lv.and_reduce() & rtovc.read().or_reduce() & rtoft.read().or_reduce();
data_lv_low = data_lv.or_reduce() | rtovc.read().or_reduce() | rtoft.read().or_reduce();
vc_lv = rtovc.read();
ft_lv = rtoft.read();
data_lv_high = (sc_logic)(data_lv.and_reduce()) & (sc_logic)(vc_lv.or_reduce()) & (sc_logic)(ft_lv.or_reduce());
data_lv_low = (sc_logic)(data_lv.or_reduce()) | (sc_logic)(vc_lv.or_reduce()) | (sc_logic)(ft_lv.or_reduce());
 
if(data_lv_high.is_01() && data_lv_high.to_bool())
rtoutp_sig = true;
162,7 → 160,7
case F_HD: mft[0] = SC_LOGIC_1; break;
case F_DAT: mft[1] = SC_LOGIC_1; break;
case F_TL: mft[2] = SC_LOGIC_1; break;
default:
default: break;
}
// VC number
214,12 → 212,14
rtoa.write(mack);
 
while(true) {
// wait for an incoming flit
wait(rtoutp_sig.posedge_event());
if(out_cred_ack[mflit.vcn].read())
wait(out_cred_ack[mflit.vcn].negedge_event());
 
// clear the flit
mflit.clear();
 
// wait for an incoming flit
wait(rtoutp_sig.posedge_event());
 
// analyse the flit
mdata[0] = rtod[0].read();
mdata[1] = rtod[1].read();
270,7 → 270,7
// get the binary vc number
unsigned int fvcn = mvc.to_uint();
while(fvcn != 0) {
while(fvcn != 1) {
mflit.vcn += 1;
fvcn >>= 1;
}
277,6 → 277,9
 
// send the flit to the NI
P2NI->write(mflit);
 
// send back a credit
out_cred[mflit.vcn] = true;
wait(0.2, SC_NS); // a delay to avoid data override
rtoa.write(~mack); // notify that data is captured
283,29 → 286,15
 
// wait for the data withdrawal
wait(rtoutp_sig.negedge_event());
if(!out_cred_ack[mflit.vcn].read())
wait(out_cred_ack[mflit.vcn].posedge_event());
 
wait(0.2, SC_NS); // a delay to avoid data override
rtoa.write(mack); // notify that data is captured
out_cred[mflit.vcn] = false;
}
}
void RTDriver::credit(unsigned int dd) {
out_cred[dd] = false;
 
while(true){
wait(out_cred_ack[dd].posedge_event());
wait(0.2, SC_NS);
out_cred[dd] = true;
wait(out_cred_ack[dd].negedge_event());
wait(0.2, SC_NS);
out_cred[dd] = false;
}
}
 
 
unsigned int RTDriver::c1o42b(unsigned int dd) {
switch(dd) {
case 1: return 0;
/rtdriver.h
49,8 → 49,8
sc_in<sc_lv<SubChN> > rtoca;
 
// local variable
sc_signal<bool> out_cred; /* the input credit */
sc_signal<bool> out_cred_ack; /* the input credit ack */
sc_signal<bool> out_cred[SubChN]; /* the input credit */
sc_signal<bool> out_cred_ack[SubChN]; /* the input credit ack */
 
SC_HAS_PROCESS(RTDriver);
61,7 → 61,6
void Creditdetect(); // Method to detect the credit ports
void send(); // thread of sending a flit
void recv(); // thread to recveive a flit
void credit(unsigned int); // handle the output credit
 
sc_signal<bool> rtinp_sig; // fire when the router input port is ready for a new flit
sc_signal<bool> rtoutp_sig; // fire when the router output port has a new flit
/rtwrapper.v
30,7 → 30,7
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rstn
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rst_n
);
 
parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
/node_top.v
103,7 → 103,7
.li0(li0), .li1(li1), .li2(li2), .li3(li3), .lia(lia), .lift(lift), .livc(livc), .lic(lic), .lica(lica),
.addrx (b2chain(x)),
.addry (b2chain(y)),
.rstn (rst_n)
.rst_n (rst_n)
);
 
/ni.h
41,8 → 41,8
sc_port<sc_fifo_out_if<FRAME> > frame_out; // frame for receiving
// interface with router
sc_port<sc_fifo_in_if<FLIT> > IP [SubChN]; // input port from IO driver
sc_port<sc_fifo_out_if<FLIT> > OP [SubChN]; // output port to IO driver
sc_port<sc_fifo_in_if<FLIT> > IP; // input port from IO driver
sc_port<sc_fifo_out_if<FLIT> > OP; // output port to IO driver
sc_in<bool> CP [SubChN]; // the credit input from the router input buffer
sc_out<bool> CPa [SubChN]; // ack to the credit
 

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