URL
https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc/branches/init
- from Rev 32 to Rev 33
- ↔ Reverse comparison
Rev 32 → Rev 33
/sdm/tb/rtdriver.cpp
14,7 → 14,7
History: |
27/04/2010 Initial version. <wsong83@gmail.com> |
16/10/2010 Support SDM. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
31/05/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com> |
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*/ |
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194,6 → 194,9
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bool is_hd = true; // the current flit is a header flit |
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// initialize the ack signal |
rtoa.write(mack); |
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while(true) { |
// clear the flit |
mflit.clear(); |
/sdm/tb/noctb.v
20,10 → 20,10
`timescale 1ns/1ps |
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module noctb; |
parameter DW = 16; // the data width of a single virtual circuit |
parameter VCN = 2; // the number of virtual circuits per direction |
parameter DW = 8; // the data width of a single virtual circuit |
parameter VCN = 1; // the number of virtual circuits per direction |
parameter DIMX = 4; // the X dimension |
parameter DIMY = 3; // the Y dimension |
parameter DIMY = 4; // the Y dimension |
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reg rst_n; |
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/sdm/tb/rtwrapper.v
87,71 → 87,71
wire [7:0] paddrx, paddry; |
wire prst_n; |
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router_syn RT ( |
.sia ( psia ), |
.wia ( pwia ), |
.nia ( pnia ), |
.eia ( peia ), |
.lia ( plia ), |
.so0 ( pso0 ), |
.so1 ( pso1 ), |
.so2 ( pso2 ), |
.so3 ( pso3 ), |
.wo0 ( pwo0 ), |
.wo1 ( pwo1 ), |
.wo2 ( pwo2 ), |
.wo3 ( pwo3 ), |
.no0 ( pno0 ), |
.no1 ( pno1 ), |
.no2 ( pno2 ), |
.no3 ( pno3 ), |
.eo0 ( peo0 ), |
.eo1 ( peo1 ), |
.eo2 ( peo2 ), |
.eo3 ( peo3 ), |
.lo0 ( plo0 ), |
.lo1 ( plo1 ), |
.lo2 ( plo2 ), |
.lo3 ( plo3 ), |
.so4 ( pso4 ), |
.wo4 ( pwo4 ), |
.no4 ( pno4 ), |
.eo4 ( peo4 ), |
.lo4 ( plo4 ), |
.si0 ( psi0 ), |
.si1 ( psi1 ), |
.si2 ( psi2 ), |
.si3 ( psi3 ), |
.wi0 ( pwi0 ), |
.wi1 ( pwi1 ), |
.wi2 ( pwi2 ), |
.wi3 ( pwi3 ), |
.ni0 ( pni0 ), |
.ni1 ( pni1 ), |
.ni2 ( pni2 ), |
.ni3 ( pni3 ), |
.ei0 ( pei0 ), |
.ei1 ( pei1 ), |
.ei2 ( pei2 ), |
.ei3 ( pei3 ), |
.li0 ( pli0 ), |
.li1 ( pli1 ), |
.li2 ( pli2 ), |
.li3 ( pli3 ), |
.si4 ( psi4 ), |
.wi4 ( pwi4 ), |
.ni4 ( pni4 ), |
.ei4 ( pei4 ), |
.li4 ( pli4 ), |
.soa ( psoa ), |
.woa ( pwoa ), |
.noa ( pnoa ), |
.eoa ( peoa ), |
.loa ( ploa ), |
.addrx ( paddrx ), |
.addry ( paddry ), |
.rst_n ( prst_n ) |
); |
router RT ( |
.sia ( psia ), |
.wia ( pwia ), |
.nia ( pnia ), |
.eia ( peia ), |
.lia ( plia ), |
.so0 ( pso0 ), |
.so1 ( pso1 ), |
.so2 ( pso2 ), |
.so3 ( pso3 ), |
.wo0 ( pwo0 ), |
.wo1 ( pwo1 ), |
.wo2 ( pwo2 ), |
.wo3 ( pwo3 ), |
.no0 ( pno0 ), |
.no1 ( pno1 ), |
.no2 ( pno2 ), |
.no3 ( pno3 ), |
.eo0 ( peo0 ), |
.eo1 ( peo1 ), |
.eo2 ( peo2 ), |
.eo3 ( peo3 ), |
.lo0 ( plo0 ), |
.lo1 ( plo1 ), |
.lo2 ( plo2 ), |
.lo3 ( plo3 ), |
.so4 ( pso4 ), |
.wo4 ( pwo4 ), |
.no4 ( pno4 ), |
.eo4 ( peo4 ), |
.lo4 ( plo4 ), |
.si0 ( psi0 ), |
.si1 ( psi1 ), |
.si2 ( psi2 ), |
.si3 ( psi3 ), |
.wi0 ( pwi0 ), |
.wi1 ( pwi1 ), |
.wi2 ( pwi2 ), |
.wi3 ( pwi3 ), |
.ni0 ( pni0 ), |
.ni1 ( pni1 ), |
.ni2 ( pni2 ), |
.ni3 ( pni3 ), |
.ei0 ( pei0 ), |
.ei1 ( pei1 ), |
.ei2 ( pei2 ), |
.ei3 ( pei3 ), |
.li0 ( pli0 ), |
.li1 ( pli1 ), |
.li2 ( pli2 ), |
.li3 ( pli3 ), |
.si4 ( psi4 ), |
.wi4 ( pwi4 ), |
.ni4 ( pni4 ), |
.ei4 ( pei4 ), |
.li4 ( pli4 ), |
.soa ( psoa ), |
.woa ( pwoa ), |
.noa ( pnoa ), |
.eoa ( peoa ), |
.loa ( ploa ), |
.addrx ( paddrx ), |
.addry ( paddry ), |
.rst_n ( prst_n ) |
); |
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assign sia = psia ; |
assign wia = pwia ; |
/sdm/syn/script/compile.tcl
12,7 → 12,7
# currently using the Nangate 45nm cell lib. |
# |
# History: |
# 26/05/2009 Initial version. <wsong83@gmail.com> |
# 31/05/2009 Initial version. <wsong83@gmail.com> |
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set rm_top router |
set rm_para "VCN=>1, DW=>8, IPD=>1, OPD=>1" |
36,6 → 36,7
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# elaborate the design |
elaborate ${rm_top} -parameters ${rm_para} |
rename_design ${current_design} router |
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link |
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56,8 → 57,8
define_name_rules verilog -allowed "A-Za-z0-9_" -first_restricted "\\" |
change_name -rules verilog -hierarchy |
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write -format verilog -hierarchy -out file/router_syn.v $current_design |
write_sdf -significant_digits 5 file/router.sdf |
write -format verilog -hierarchy -out file/${current_design}_syn.v $current_design |
write_sdf -significant_digits 5 file/${current_design}.sdf |
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report_constraints -verbose |
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/common/tb/procelem.h
13,7 → 13,7
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History: |
26/02/2011 Initial version. <wsong83@gmail.com> |
30/05/2011 Clean up for opensource. <wsong83@gmail.com> |
31/05/2011 Clean up for opensource. <wsong83@gmail.com> |
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*/ |
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28,7 → 28,7
double rand_exponential(double exp) { |
unsigned int rint = rand() % (unsigned int)(1e6); |
double rdat = rint * 1.0 / 1e6; |
return (-1 * exp * log(rint)); |
return (-1.0 * exp * log(rdat)); |
} |
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class ProcElem : public sc_module { |
/common/src/cell_lib.v
16,7 → 16,7
05/05/2009 Initial version. <wsong83@gmail.com> |
20/05/2011 Change to general verilog description for opensource. |
The Nangate cell library is used. <wsong83@gmail.com> |
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31/05/2011 The bugs in the C2 description is fixed. <wsong83@gmail.com> |
*/ |
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// General 2-input C-element |
30,7 → 30,7
nand U1 (m[0], a0, a1); |
nand U2 (m[1], a0, q); |
nand U3 (m[2], a1, q); |
assign q = &m; |
assign q = ~&m; |
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endmodule |
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46,7 → 46,7
nand U1 (m[0], a, d); |
nand U2 (m[1], d, q); |
nand U3 (m[2], a, q); |
assign q = &m; |
assign q = ~&m; |
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endmodule |
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