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/vc/src/router.v
0,0 → 1,424
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Asynchronous VC router.
History:
05/04/2010 Initial version. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module router (/*AUTOARG*/
// Outputs
sia, wia, nia, eia, lia, sic, wic, nic, eic, lic, so0, so1, so2,
so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3,
lo0, lo1, lo2, lo3, soft, woft, noft, eoft, loft, sovc, wovc, novc,
eovc, lovc, soca, woca, noca, eoca, loca,
// Inputs
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rstn
);
 
parameter VCN = 2; // number of VCs per direction
parameter DW = 32; // data width of an input port
parameter PD = 1; // the depth of a input VC buffer
parameter FT = 3; // the number of flit types, currently 3 (HD, DATA, TAIL)
parameter FCPD = PD;
parameter SCN = DW/2;
 
// input ports
input [SCN-1:0] si0, si1, si2, si3;
input [SCN-1:0] wi0, wi1, wi2, wi3;
input [SCN-1:0] ni0, ni1, ni2, ni3;
input [SCN-1:0] ei0, ei1, ei2, ei3;
input [SCN-1:0] li0, li1, li2, li3;
input [FT-1:0] sift, wift, nift, eift, lift;
input [VCN-1:0] sivc, wivc, nivc, eivc, livc;
output sia, wia, nia, eia, lia;
output [VCN-1:0] sic, wic, nic, eic, lic;
input [VCN-1:0] sica, wica, nica, eica, lica;
 
// output ports
output [SCN-1:0] so0, so1, so2, so3;
output [SCN-1:0] wo0, wo1, wo2, wo3;
output [SCN-1:0] no0, no1, no2, no3;
output [SCN-1:0] eo0, eo1, eo2, eo3;
output [SCN-1:0] lo0, lo1, lo2, lo3;
output [FT-1:0] soft, woft, noft, eoft, loft;
output [VCN-1:0] sovc, wovc, novc, eovc, lovc;
input soa, woa, noa, eoa, loa;
input [VCN-1:0] soc, woc, noc, eoc, loc;
output [VCN-1:0] soca, woca, noca, eoca, loca;
 
// local address, in 1-of-4 format
input [7:0] addrx, addry;
// active-low reset
input rstn;
 
//----------------------------------
// input to crossbar
wire [VCN-1:0][SCN-1:0] s2cb0, s2cb1, s2cb2, s2cb3;
wire [VCN-1:0][SCN-1:0] w2cb0, w2cb1, w2cb2, w2cb3;
wire [VCN-1:0][SCN-1:0] n2cb0, n2cb1, n2cb2, n2cb3;
wire [VCN-1:0][SCN-1:0] e2cb0, e2cb1, e2cb2, e2cb3;
wire [VCN-1:0][SCN-1:0] l2cb0, l2cb1, l2cb2, l2cb3;
wire [VCN-1:0][FT-1:0] s2cbt, w2cbt, n2cbt, e2cbt, l2cbt;
wire [VCN-1:0][3:0] s2cbrtg, n2cbrtg, l2cbrtg;
wire [VCN-1:0][1:0] w2cbrtg, e2cbrtg;
wire [VCN-1:0] s2cba, w2cba, n2cba, e2cba, l2cba;
 
// VC requests
wire [VCN-1:0][3:0] svcr, nvcr, lvcr;
wire [VCN-1:0] svcra, nvcra, lvcra;
wire [VCN-1:0][1:0] wvcr, evcr;
wire [VCN-1:0] wvcra, evcra;
 
// SW requests
wire [VCN-1:0][1:0] siswr, wiswr, niswr, eiswr, liswr;
wire [VCN-1:0][3:0] siswrt, niswrt, liswrt;
wire [VCN-1:0][1:0] wiswrt, eiswrt;
 
// crossbar to output
wire [SCN-1:0] cb2s0, cb2s1, cb2s2, cb2s3;
wire [SCN-1:0] cb2w0, cb2w1, cb2w2, cb2w3;
wire [SCN-1:0] cb2n0, cb2n1, cb2n2, cb2n3;
wire [SCN-1:0] cb2e0, cb2e1, cb2e2, cb2e3;
wire [SCN-1:0] cb2l0, cb2l1, cb2l2, cb2l3;
wire [FT-1:0] cb2st, cb2wt, cb2nt, cb2et, cb2lt;
wire cb2sa, cb2wa, cb2na, cb2ea, cb2la;
 
// SW requests to VC arbiters in output buffers
wire [VCN-1:0] soswr, woswr, noswr, eoswr, loswr;
wire [VCN-1:0] soswa, woswa, noswa, eoswa, loswa;
 
//-------------------------------------
// south input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(0), .SN(4), .PD(PD), .FT(FT))
SIB (
.dia ( sia ),
.cor ( sic ),
.do0 ( s2cb0 ),
.do1 ( s2cb1 ),
.do2 ( s2cb2 ),
.do3 ( s2cb3 ),
.dot ( s2cbt ),
.dortg ( s2cbrtg ),
.vcr ( svcr ),
.swr ( siswr ),
.di0 ( si0 ),
.di1 ( si1 ),
.di2 ( si2 ),
.di3 ( si3 ),
.dit ( sift ),
.divc ( sivc ),
.coa ( sica ),
.doa ( s2cba ),
.vcra ( svcra ),
.swrt ( siswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
);
 
// west input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(1), .SN(2), .PD(PD), .FT(FT))
WIB (
.dia ( wia ),
.cor ( wic ),
.do0 ( w2cb0 ),
.do1 ( w2cb1 ),
.do2 ( w2cb2 ),
.do3 ( w2cb3 ),
.dot ( w2cbt ),
.dortg ( w2cbrtg ),
.vcr ( wvcr ),
.swr ( wiswr ),
.di0 ( wi0 ),
.di1 ( wi1 ),
.di2 ( wi2 ),
.di3 ( wi3 ),
.dit ( wift ),
.divc ( wivc ),
.coa ( wica ),
.doa ( w2cba ),
.vcra ( wvcra ),
.swrt ( wiswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
);
// north input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(2), .SN(4), .PD(PD), .FT(FT))
NIB (
.dia ( nia ),
.cor ( nic ),
.do0 ( n2cb0 ),
.do1 ( n2cb1 ),
.do2 ( n2cb2 ),
.do3 ( n2cb3 ),
.dot ( n2cbt ),
.dortg ( n2cbrtg ),
.vcr ( nvcr ),
.swr ( niswr ),
.di0 ( ni0 ),
.di1 ( ni1 ),
.di2 ( ni2 ),
.di3 ( ni3 ),
.dit ( nift ),
.divc ( nivc ),
.coa ( nica ),
.doa ( n2cba ),
.vcra ( nvcra ),
.swrt ( niswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
);
// east input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(3), .SN(2), .PD(PD), .FT(FT))
EIB (
.dia ( eia ),
.cor ( eic ),
.do0 ( e2cb0 ),
.do1 ( e2cb1 ),
.do2 ( e2cb2 ),
.do3 ( e2cb3 ),
.dot ( e2cbt ),
.dortg ( e2cbrtg ),
.vcr ( evcr ),
.swr ( eiswr ),
.di0 ( ei0 ),
.di1 ( ei1 ),
.di2 ( ei2 ),
.di3 ( ei3 ),
.dit ( eift ),
.divc ( eivc ),
.coa ( eica ),
.doa ( e2cba ),
.vcra ( evcra ),
.swrt ( eiswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
);
// local input buffer
inpbuf #(.DW(DW), .VCN(VCN), .DIR(4), .SN(4), .PD(PD), .FT(FT))
LIB (
.dia ( lia ),
.cor ( lic ),
.do0 ( l2cb0 ),
.do1 ( l2cb1 ),
.do2 ( l2cb2 ),
.do3 ( l2cb3 ),
.dot ( l2cbt ),
.dortg ( l2cbrtg ),
.vcr ( lvcr ),
.swr ( liswr ),
.di0 ( li0 ),
.di1 ( li1 ),
.di2 ( li2 ),
.di3 ( li3 ),
.dit ( lift ),
.divc ( livc ),
.coa ( lica ),
.doa ( l2cba ),
.vcra ( lvcra ),
.swrt ( liswrt ),
.addrx ( addrx ),
.addry ( addry ),
.rstn ( rstn )
);
 
// south output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
SOB (
.dia ( cb2sa ),
.do0 ( so0 ),
.do1 ( so1 ),
.do2 ( so2 ),
.do3 ( so3 ),
.dot ( soft ),
.dovc ( sovc ),
.afc ( soca ),
.vca ( soswa ),
.di0 ( cb2s0 ),
.di1 ( cb2s1 ),
.di2 ( cb2s2 ),
.di3 ( cb2s3 ),
.dit ( cb2st ),
.doa ( soa ),
.credit( soc ),
.vcr ( soswr ),
.rstn ( rstn )
);
 
// west output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
WOB (
.dia ( cb2wa ),
.do0 ( wo0 ),
.do1 ( wo1 ),
.do2 ( wo2 ),
.do3 ( wo3 ),
.dot ( woft ),
.dovc ( wovc ),
.afc ( woca ),
.vca ( woswa ),
.di0 ( cb2w0 ),
.di1 ( cb2w1 ),
.di2 ( cb2w2 ),
.di3 ( cb2w3 ),
.dit ( cb2wt ),
.doa ( woa ),
.credit( woc ),
.vcr ( woswr ),
.rstn ( rstn )
);
 
// north output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
NOB (
.dia ( cb2na ),
.do0 ( no0 ),
.do1 ( no1 ),
.do2 ( no2 ),
.do3 ( no3 ),
.dot ( noft ),
.dovc ( novc ),
.afc ( noca ),
.vca ( noswa ),
.di0 ( cb2n0 ),
.di1 ( cb2n1 ),
.di2 ( cb2n2 ),
.di3 ( cb2n3 ),
.dit ( cb2nt ),
.doa ( noa ),
.credit( noc ),
.vcr ( noswr ),
.rstn ( rstn )
);
 
// east output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
EOB (
.dia ( cb2ea ),
.do0 ( eo0 ),
.do1 ( eo1 ),
.do2 ( eo2 ),
.do3 ( eo3 ),
.dot ( eoft ),
.dovc ( eovc ),
.afc ( eoca ),
.vca ( eoswa ),
.di0 ( cb2e0 ),
.di1 ( cb2e1 ),
.di2 ( cb2e2 ),
.di3 ( cb2e3 ),
.dit ( cb2et ),
.doa ( eoa ),
.credit( eoc ),
.vcr ( eoswr ),
.rstn ( rstn )
);
 
// east output buffer
outpbuf #(.DW(DW), .VCN(VCN), .FT(FT), .FCPD(FCPD))
LOB (
.dia ( cb2la ),
.do0 ( lo0 ),
.do1 ( lo1 ),
.do2 ( lo2 ),
.do3 ( lo3 ),
.dot ( loft ),
.dovc ( lovc ),
.afc ( loca ),
.vca ( loswa ),
.di0 ( cb2l0 ),
.di1 ( cb2l1 ),
.di2 ( cb2l2 ),
.di3 ( cb2l3 ),
.dit ( cb2lt ),
.doa ( loa ),
.credit( loc ),
.vcr ( loswr ),
.rstn ( rstn )
);
 
// VC allocator
vcalloc #(.VCN(VCN))
VCA (
.svcra ( svcra ),
.wvcra ( wvcra ),
.nvcra ( nvcra ),
.evcra ( evcra ),
.lvcra ( lvcra ),
.sswa ( siswrt ),
.wswa ( wiswrt ),
.nswa ( niswrt ),
.eswa ( eiswrt ),
.lswa ( liswrt ),
.sosr ( soswr ),
.wosr ( woswr ),
.nosr ( noswr ),
.eosr ( eoswr ),
.losr ( loswr ),
.svcr ( svcr ),
.nvcr ( nvcr ),
.lvcr ( lvcr ),
.wvcr ( wvcr ),
.evcr ( evcr ),
.sswr ( siswr ),
.wswr ( wiswr ),
.nswr ( niswr ),
.eswr ( eiswr ),
.lswr ( liswr ),
.sosa ( soswa ),
.wosa ( woswa ),
.nosa ( noswa ),
.eosa ( eoswa ),
.losa ( loswa ),
.rstn ( rstn )
);
 
// crossbar
dcb_vc #(.DW(DW), .FT(FT), .VCN(VCN))
CB (
.dia ( {l2cba, e2cba, n2cba, w2cba, s2cba} ),
.do0 ( {cb2l0, cb2e0, cb2n0, cb2w0, cb2s0} ),
.do1 ( {cb2l1, cb2e1, cb2n1, cb2w1, cb2s1} ),
.do2 ( {cb2l2, cb2e2, cb2n2, cb2w2, cb2s2} ),
.do3 ( {cb2l3, cb2e3, cb2n3, cb2w3, cb2s3} ),
.dot ( {cb2lt, cb2et, cb2nt, cb2wt, cb2st} ),
.di0 ( {l2cb0, e2cb0, n2cb0, w2cb0, s2cb0} ),
.di1 ( {l2cb1, e2cb1, n2cb1, w2cb1, s2cb1} ),
.di2 ( {l2cb2, e2cb2, n2cb2, w2cb2, s2cb2} ),
.di3 ( {l2cb3, e2cb3, n2cb3, w2cb3, s2cb3} ),
.dit ( {l2cbt, e2cbt, n2cbt, w2cbt, s2cbt} ),
.srtg ( s2cbrtg ),
.nrtg ( n2cbrtg ),
.lrtg ( l2cbrtg ),
.wrtg ( w2cbrtg ),
.ertg ( e2cbrtg ),
.doa ( {cb2la, cb2ea, cb2na, cb2wa, cb2sa} )
);
endmodule // router
 
/vc/src/inpbuf.v
0,0 → 1,285
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The input buffer for VC routers.
History:
01/04/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbars. <wsong83@gmail.com>
17/04/2010 Remove unnecessary pipeline stages. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module inpbuf (/*AUTOARG*/
// Outputs
dia, cor, do0, do1, do2, do3, dot, dortg, vcr, swr,
// Inputs
di0, di1, di2, di3, dit, divc, coa, doa, vcra, swrt, addrx, addry,
rstn
);
 
parameter DW = 32; // data width
parameter VCN = 2; // VC number
parameter DIR = 0; // 0-4 south, west, north, east, local
parameter SN = 2; // maximal output port number
parameter PD = 3; // the depth of the input buffer pipeline
parameter SCN = DW/2; // number of 1-of-4 sub-channels
parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
// data IP
input [SCN-1:0] di0, di1, di2, di3;
input [FT-1:0] dit;
input [VCN-1:0] divc;
output dia;
 
// credit flow-control
output [VCN-1:0] cor;
input [VCN-1:0] coa;
 
// data to crossbar
output [VCN-1:0][SCN-1:0] do0,do1,do2,do3;
output [VCN-1:0][FT-1:0] dot;
output [VCN-1:0][SN-1:0] dortg;
input [VCN-1:0] doa;
 
// request to VC allocator
output [VCN-1:0][SN-1:0] vcr;
input [VCN-1:0] vcra;
 
// output to SW allocator
output [VCN-1:0][1:0] swr;
 
// routing guide for SW DEMUX
input [VCN-1:0][SN-1:0] swrt;
 
// local addresses
input [7:0] addrx, addry;
 
input rstn;
 
//-----------------------------
// VC_MUX
wire ivma, rua;
wire [SCN-1:0] di0m, di1m, di2m, di3m;
wire [FT-1:0] ditm;
wire [VCN-1:0] divcm;
wire [VCN-1:0] muxa;
// VC_BUF
wire [2*PD:0][VCN-1:0][SCN-1:0] vcd0, vcd1, vcd2, vcd3; // VC data
wire [2*PD:0][VCN-1:0][FT-1:0] vcdt; // VC flit type
wire [2*PD:0][VCN-1:0][SCN-1:0] vcdad, vcdadn; // VC ack
wire [2*PD:0][VCN-1:0] vcdat, vcdatn; // VC data ack and type ack
wire [1:0][VCN-1:0] vcda; // the comman ack
 
// control path
wire [2*PD:2*PD-2][VCN-1:0][1:0] vcft; // flit type on control path
wire [2*PD:2*PD-2][VCN-1:0] vcfta, vcftan; // flit type ack, on control path
wire [VCN-1:0] vcdam; // need an extra ack internal signal
wire [VCN-1:0][SN-1:0] rtg; // routing direction guide
wire [VCN-1:0] doan;
// last stage of input buffer
wire [VCN-1:0] vcor;
wire [VCN-1:0] vcog;
wire [VCN-1:0] swa;
 
genvar gbd, gvc, gsub, i;
 
//---------------------------------------------
// the input VCDMUX
vcdmux #(.VCN(VCN), .DW(DW))
IVM (
.dia ( ivma ),
.do0 ( vcd0[0] ),
.do1 ( vcd1[0] ),
.do2 ( vcd2[0] ),
.do3 ( vcd3[0] ),
.dot ( vcdt[0] ),
.di0 ( di0m ),
.di1 ( di1m ),
.di2 ( di2m ),
.di3 ( di3m ),
.dit ( ditm ),
.divc ( divcm ),
.doa ( muxa )
);
 
//c2 IVMA (.a0(ivma), .a1(rua), .q(dia)); divc is not checked
ctree #(.DW(3)) ACKT(.ci({ivma, rua, (|divcm)}), .co(dia));
assign di0m = rstn ? di0 : 0;
assign di1m = rstn ? di1 : 0;
assign di2m = rstn ? di2 : 0;
assign di3m = rstn ? di3 : 0;
assign ditm = rstn ? dit : 0;
assign divcm = rstn ? divc : 0;
 
//---------------------------------------------
// the VC buffers
generate
for(gbd=0; gbd<PD*2-2; gbd++) begin:BFN
for(gvc=0; gvc<VCN; gvc++) begin:V
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
DP (
.dia ( vcdad[gbd][gvc][gsub] ),
.do0 ( vcd0[gbd+1][gvc][gsub] ),
.do1 ( vcd1[gbd+1][gvc][gsub] ),
.do2 ( vcd2[gbd+1][gvc][gsub] ),
.do3 ( vcd3[gbd+1][gvc][gsub] ),
.di0 ( vcd0[gbd][gvc][gsub] ),
.di1 ( vcd1[gbd][gvc][gsub] ),
.di2 ( vcd2[gbd][gvc][gsub] ),
.di3 ( vcd3[gbd][gvc][gsub] ),
.doa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
end // block: SC
pipen #(.DW(FT))
TP (
.d_in ( vcdt[gbd][gvc] ),
.d_in_a ( vcdat[gbd][gvc] ),
.d_out ( vcdt[gbd+1][gvc] ),
.d_out_a ( vcdatn[gbd+1][gvc] )
);
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rstn;
end // block: V
end // block: BFN
 
for(gvc=0; gvc<VCN; gvc++) begin:BFNV
if(PD>1) begin:ACKG
ctree #(.DW(SCN+1)) ACKT(.ci({vcdat[0],vcdad[0]}), .co(muxa[gvc]));
assign vcdad[PD*2-2][gvc] = {SCN{vcda[0][gvc]}};
assign vcdat[PD*2-2] = vcda[0][gvc];
end else begin
assign muxa[gvc] = vcda[0][gvc];
end
end // block: V
endgenerate
 
// the last two stages of VC buffers, separate flit type and data
generate
for(gbd=PD*2-2; gbd<PD*2; gbd++) begin:BFL2
for(gvc=0; gvc<VCN; gvc++) begin:V
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
DP (
.dia ( vcdad[gbd][gvc][gsub] ),
.do0 ( vcd0[gbd+1][gvc][gsub] ),
.do1 ( vcd1[gbd+1][gvc][gsub] ),
.do2 ( vcd2[gbd+1][gvc][gsub] ),
.do3 ( vcd3[gbd+1][gvc][gsub] ),
.di0 ( vcd0[gbd][gvc][gsub] ),
.di1 ( vcd1[gbd][gvc][gsub] ),
.di2 ( vcd2[gbd][gvc][gsub] ),
.di3 ( vcd3[gbd][gvc][gsub] ),
.doa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
end // block: SC
pipen #(.DW(FT))
TP (
.d_in ( vcdt[gbd][gvc] ),
.d_in_a ( vcdat[gbd][gvc] ),
.d_out ( vcdt[gbd+1][gvc] ),
.d_out_a ( vcdatn[gbd+1][gvc] )
);
 
assign vcdatn[gbd+1][gvc] = (~vcdat[gbd+1][gvc])&rstn;
 
pipen #(.DW(2))
CTP (
.d_in ( vcft[gbd][gvc] ),
.d_in_a ( vcfta[gbd][gvc] ),
.d_out ( vcft[gbd+1][gvc] ),
.d_out_a ( vcftan[gbd+1][gvc] )
);
 
assign vcftan[gbd+1][gvc] = (~vcfta[gbd+1][gvc])&rstn;
end // block: V
end // block: BFL2
 
for(gvc=0; gvc<VCN; gvc++) begin:BFL2V
ctree #(.DW(SCN+2)) ACKT(.ci({vcfta[PD*2-2][gvc], vcdat[PD*2-2][gvc], vcdad[PD*2-2][gvc]}), .co(vcda[0][gvc]));
assign vcdat[PD*2][gvc] = vcda[1][gvc];
assign vcdad[PD*2][gvc] = {SCN{vcda[1][gvc]}};
assign vcfta[PD*2][gvc] = swa[gvc];
assign vcft[PD*2-2][gvc] = {vcdt[PD*2-2][gvc][FT-1], |vcdt[PD*2-2][gvc][FT-2:0]};
assign swr[gvc] = vcft[PD*2][gvc];
end
 
endgenerate
 
// the routing guide pipeline stage
generate
for(gvc=0; gvc<VCN; gvc++) begin:R
pipen #(.DW(SN))
RP (
.d_in ( swrt[gvc] ),
.d_in_a ( swa[gvc] ),
.d_out ( rtg[gvc] ),
.d_out_a ( (~vcda[1][gvc])&rstn )
);
end
endgenerate
 
generate
for(gvc=0; gvc<VCN; gvc++) begin:LPS
 
// credit control
dc2 FCP (.q(cor[gvc]), .d(|rtg[gvc]), .a((~coa[gvc])&rstn));
 
// output name conversation
assign do0[gvc] = vcd0[PD*2][gvc];
assign do1[gvc] = vcd1[PD*2][gvc];
assign do2[gvc] = vcd2[PD*2][gvc];
assign do3[gvc] = vcd3[PD*2][gvc];
 
assign dot[gvc] = vcdt[PD*2][gvc];
assign dortg[gvc] = rtg[gvc];
 
c2 AC (.q(vcda[1][gvc]), .a0(cor[gvc]), .a1(doa[gvc]));
 
end // block: LPS
endgenerate
// routing unit
rtu #(.VCN(VCN), .DIR(DIR), .SN(SN), .PD(2))
RTC (
.dia ( rua ),
.dort ( vcr ),
.rstn ( rstn ),
.di0 ( di0m[3:0] ),
.di1 ( di1m[3:0] ),
.di2 ( di2m[3:0] ),
.di3 ( di3m[3:0] ),
.dit ( ditm ),
.divc ( divcm ),
.addrx ( addrx ),
.addry ( addry ),
.doa ( vcra )
);
endmodule // inpbuf
 
 
 
 
/vc/src/outpbuf.v
0,0 → 1,127
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The output buffer for VC routers.
History:
04/04/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbars. <wsong83@gmail.com>
08/05/2010 Remove unnecessary pipeline stages. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module outpbuf (/*AUTOARG*/
// Outputs
dia, do0, do1, do2, do3, dot, dovc, afc, vca,
// Inputs
di0, di1, di2, di3, dit, doa, credit, vcr, rstn
);
parameter DW = 32; // data width
parameter VCN = 4; // VC number
parameter FT = 3; // flit type, now 3, HOF, BOF, EOF
parameter FCPD = 3; // the depth of the credit pipeline
parameter SCN = DW/2;
 
//data in
input [SCN-1:0] di0, di1, di2, di3;
input [FT-1:0] dit;
output dia;
 
// data out
output [SCN-1:0] do0, do1, do2, do3;
output [FT-1:0] dot;
output [VCN-1:0] dovc;
input doa;
 
// credit
input [VCN-1:0] credit;
output [VCN-1:0] afc;
 
// vc requests in
input [VCN-1:0] vcr;
output [VCN-1:0] vca;
 
// active-low reset
input rstn;
 
//--------------------------------------------------------------
wire [VCN-1:0] vcro, vcg, vcgl, vcrm;
wire [SCN-1:0] doan, diad;
wire dian, diavc, diavcn, diat;
genvar i, gsub;
// flow control controller
fcctl #(.VCN(VCN), .PD(FCPD))
FCU (
.afc ( afc ),
.ro ( vcro ),
.credit ( credit ),
.ri ( vcr ),
.rst ( ~rstn )
);
 
// VC arbiter
mutex_arb #(.wd(VCN)) Sch (.req(vcro), .gnt(vcg));
 
// the control logic for VC arbiter
generate
for(i=0; i<VCN; i++)begin:SCEN
c2 C (.a0(vcg[i]), .a1(diavcn), .q(vcgl[i]));
end
endgenerate
assign diavcn = (~diavc)&rstn;
 
// output data buffer
generate
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
L0D (
.dia ( diad[gsub] ),
.do0 ( do0[gsub] ),
.do1 ( do1[gsub] ),
.do2 ( do2[gsub] ),
.do3 ( do3[gsub] ),
.di0 ( di0[gsub] ),
.di1 ( di1[gsub] ),
.di2 ( di2[gsub] ),
.di3 ( di3[gsub] ),
.doa ( doan[gsub] )
);
assign doan[gsub] = (~doa)&rstn;
end // block: SC
endgenerate
 
pipen #(.DW(FT))
L0T (
.d_in ( dit ),
.d_in_a ( diat ),
.d_out ( dot ),
.d_out_a ( (~doa)&rstn )
);
ctree #(.DW(SCN+2)) ACKT (.ci({diavc,diat, diad}), .co(dia));
pipen #(.DW(VCN))
LSV (
.d_in ( vcgl ),
.d_in_a ( diavc ),
.d_out ( dovc ),
.d_out_a ( (~doa)&rstn )
);
 
assign vca = dovc;
 
endmodule // outpbuf
 
 

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