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Rev 10 → Rev 11

/common/src/pipe4.v
0,0 → 1,71
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
General pipeline stage using the 4-phase 1-of-4 QDI protocol.
*** SystemVerilog is used ***
History:
05/05/2009 Initial version. <wsong83@gmail.com>
17/04/2011 Remove the common ack generation. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module pipe4(/*AUTOARG*/
// Outputs
ia, o0, o1, o2, o3,
// Inputs
i0, i1, i2, i3, oa
`ifdef ENABLE_EOF
, i4, o4
`endif
);
parameter DW = 32; // the data width of the pipeline stage
parameter SCN = DW/2; // the number of 1-of-4 sub-stage required
input [SCN-1:0] i0, i1, i2, i3, oa;
output [SCN-1:0] o0, o1, o2, o3, ia;
 
`ifdef ENABLE_EOF
input o4; // the eof bit
output i4;
`endif
// internal signals
wire [2*SCN-2:0] tack;
// generate the ack line
genvar i;
// the data pipe stage
generate for (i=0; i<SCN; i++) begin:DD
dc2 DC0 (.d(i0[i]), .a(oa[i]), .q(o0[i]));
dc2 DC1 (.d(i1[i]), .a(oa[i]), .q(o1[i]));
dc2 DC2 (.d(i2[i]), .a(oa[i]), .q(o2[i]));
dc2 DC3 (.d(i3[i]), .a(oa[i]), .q(o3[i]));
end endgenerate
 
// the eof bit
`ifdef ENABLE_EOF
dc2 DD_DC4 (.d(i4), .a(oa[SCN-1]), .q(o4));
`endif
 
// generate the input ack
assign ia = o0|o1|o2|o3;
 
endmodule
 
 
 
/common/src/ctree.v
0,0 → 1,45
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
C-element tree, usually for common ack generation.
*** SystemVerilog is used ***
History:
17/04/2011 Initial version. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module ctree (/*AUTOARG*/
// Outputs
co,
// Inputs
ci
);
 
parameter DW = 2; // the total number of leaves of the C-element tree
 
input [DW-1:0] ci; // all input leaves
output co; // the combined output
 
wire [2*DW-2:0] dat;
genvar i;
assign dat[DW-1:0] = ci;
generate for (i=0; i<DW-1; i=i+1) begin:AT
c2 CT (.a0(dat[i*2]), .a1(dat[i*2+1]), .q(dat[i+DW]));
end endgenerate
 
assign co = dat[2*DW-2];
 
endmodule // ctree
 
/common/src/tree_arb.v
0,0 → 1,106
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
M-to-1 asynchronous tree arbiter.
History:
03/09/2009 Initial version. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module tree_arb (/*AUTOARG*/
// Outputs
gnt,
// Inputs
req
) ;
 
// parameters
parameter MR = 2; // the number of request inputs
localparam TrLev = mlog2(MR)-1; // the number of levels of the tree
input [MR-1:0] req; // the request input
output [MR-1:0] gnt; // the grant output
 
// generate variables
genvar i, j, k;
 
// internal wires
wire [MR*2:0] mreq; // the internal request lines
wire [MR*2:0] mgnt; // the internal gnt lines
wire [1:0] rgnt; // the positive gnt of the root mutex
 
// the hardware block
generate
if (MR == 1) // special case: only one input
begin: MA_1
assign gnt = req;
end
else if(MR == 2) // special case: only two input
begin: MA_2
mutex ME0 (
.a ( req[0] ),
.b ( req[1] ),
.qa ( gnt[0] ),
.qb ( gnt[1] )
);
end
else
begin: MA_N
 
mutex ME0 (
.a ( mreq[0] ),
.b ( mreq[1] ),
.qa ( rgnt[0] ),
.qb ( rgnt[1] )
);
 
assign mgnt[1:0] = ~rgnt;
 
for (i=1; 2**(i+1)<MR; i=i+1) begin: L
for (j=0; j<2**i; j=j+1) begin: T
tarb TA (
.ngnt ( mgnt[(2**i-1)*2+j*2+1:(2**i-1)*2+j*2] ),
.ntgnt ( mgnt[(2**(i-1)-1)*2+j] ),
.req ( mreq[(2**i-1)*2+j*2+1:(2**i-1)*2+j*2] ),
.treq ( mreq[(2**(i-1)-1)*2+j] )
);
end
end
 
for (j=0; j<MR-(2**TrLev); j=j+1) begin: LF
tarb TA (
.ngnt ( mgnt[(2**TrLev-1)*2+j*2+1:(2**TrLev-1)*2+j*2] ),
.ntgnt ( mgnt[(2**(TrLev-1)-1)*2+j] ),
.req ( mreq[(2**TrLev-1)*2+j*2+1:(2**TrLev-1)*2+j*2] ),
.treq ( mreq[(2**(TrLev-1)-1)*2+j] )
);
end
 
assign gnt = ~(mgnt[2*MR-3:MR-2]);
assign mreq[2*MR-3:MR-2] = req;
 
end
endgenerate
 
// log_2 function
function integer mlog2;
input integer MR;
begin
for( mlog2 = 0; 2**mlog2<MR; mlog2=mlog2+1)
begin
end
end
endfunction // mlog2
 
endmodule // tree_arb
 
 
/common/src/mutex_arb.v
0,0 → 1,48
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
M-to-1 asynchronous multi-way MUTEX arbiter.
History:
24/05/2009 Initial version. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module mutex_arb (/*AUTOARG*/
// Outputs
gnt,
// Inputs
req
);
parameter wd = 4; // the number of request inputs
 
input [wd-1:0] req;
output [wd-1:0] gnt;
 
genvar i,j;
wire [wd-1:0] arb_w [wd-1:0];
wire [wd-1:0] gnt;
generate
for(i=0; i<wd; i=i+1) begin:lv
for(j=i+1; j<wd; j=j+1) begin:b
mutex ME ( .a(arb_w[i][j-1]), .b(arb_w[j][i]), .qa(arb_w[i][j]), .qb(arb_w[j][i+1]));
end
assign arb_w[i][0] = req[i];
assign gnt[i] = arb_w[i][wd-1];
end
endgenerate
endmodule // mutex_arb
 

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