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/sdm/src/clos_sch.v
0,0 → 1,232
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Clos scheduler
*** SystemVerilog is used ***
References
For the detail structure, please refer to Section 6.3.1 of the thesis:
Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
History:
11/12/2009 Initial version. <wsong83@gmail.com>
10/06/2010 Change to use PIM structure <wsong83@gmail.com>
23/08/2010 Fix the non-QDI request withdraw process <wsong83@gmail.com>
23/09/2010 Modified for Clos SDM router <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module clos_sch (/*AUTOARG*/
// Outputs
sack, wack, nack, eack, lack, imc, scfg, ncfg, wcfg, ecfg, lcfg,
// Inputs
sreq, nreq, lreq, wreq, ereq, rst_n
);
 
parameter M = 2; // the number of CMs
parameter N = 2; // the number of ports in IMs/OMs
 
// reuests from all input buffers
input [N-1:0][3:0] sreq, nreq, lreq;
input [N-1:0][1:0] wreq, ereq;
 
// ack to input buffers
output [N-1:0] sack, wack, nack, eack, lack;
 
// IM acks
wire [4:0][N-1:0] imra;
wire [4:0][N-1:0] cmra;
 
// IM cfgs and CM cfgs
output [4:0][M-1:0][N-1:0] imc;
output [M-1:0][1:0] scfg, ncfg;
output [M-1:0][3:0] wcfg, ecfg, lcfg;
 
input rst_n; // reset, active low
 
// the requests from IMs to CMs
wire [M-1:0][1:0] wr, er;
wire [M-1:0][3:0] sr, nr, lr;
wire [M-1:0] sra, wra, nra, era, lra;
`ifndef ENABLE_CRRD
wire [M-1:0][4:0] cms; // the states from CMs
 
wire [M-1:0][3:0] scms, ncms, lcms;
wire [M-1:0][1:0] wcms, ecms;
`endif
genvar i;
 
// IM schedulers
im_alloc #(.VCN(N), .CMN(M), .SN(4))
SIM (
.IMr ( sreq ),
.IMa ( imra[0] ),
`ifndef ENABLE_CRRD
.CMs ( scms ),
`endif
.cfg ( imc[0] ),
.rst_n ( rst_n )
);
rcb #(.NN(N), .MN(M), .DW(4))
SRIM (
.ireq ( sreq ),
.ira ( cmra[0] ),
.oreq ( sr ),
.ora ( sra ),
.gnt ( imc[0] )
);
 
// the C-element to force the request withdrawal sequence
generate for(i=0; i<N; i++) begin: SA
c2 UA (.q(sack[i]), .a0(imra[0][i]), .a1(cmra[0][i]));
end endgenerate
 
im_alloc #(.VCN(N), .CMN(M), .SN(2))
WIM (
.IMr ( wreq ),
.IMa ( imra[1] ),
`ifndef ENABLE_CRRD
.CMs ( wcms ),
`endif
.cfg ( imc[1] ),
.rst_n ( rst_n )
);
 
rcb #(.NN(N), .MN(M), .DW(2))
WRIM (
.ireq ( wreq ),
.ira ( cmra[1] ),
.oreq ( wr ),
.ora ( wra ),
.gnt ( imc[1] )
);
 
generate for(i=0; i<N; i++) begin: WA
c2 UA (.q(wack[i]), .a0(imra[1][i]), .a1(cmra[1][i]));
end endgenerate
 
im_alloc #(.VCN(N), .CMN(M), .SN(4))
NIM (
.IMr ( nreq ),
.IMa ( imra[2] ),
`ifndef ENABLE_CRRD
.CMs ( ncms ),
`endif
.cfg ( imc[2] ),
.rst_n ( rst_n )
);
 
rcb #(.NN(N), .MN(M), .DW(4))
NRIM (
.ireq ( nreq ),
.ira ( cmra[2] ),
.oreq ( nr ),
.ora ( nra ),
.gnt ( imc[2] )
);
 
generate for(i=0; i<N; i++) begin: NA
c2 UA (.q(nack[i]), .a0(imra[2][i]), .a1(cmra[2][i]));
end endgenerate
 
im_alloc #(.VCN(N), .CMN(M), .SN(2))
EIM (
.IMr ( ereq ),
.IMa ( imra[3] ),
`ifndef ENABLE_CRRD
.CMs ( ecms ),
`endif
.cfg ( imc[3] ),
.rst_n ( rst_n )
);
 
rcb #(.NN(N), .MN(M), .DW(2))
ERIM (
.ireq ( ereq ),
.ira ( cmra[3] ),
.oreq ( er ),
.ora ( era ),
.gnt ( imc[3] )
);
 
generate for(i=0; i<N; i++) begin: EA
c2 UA (.q(eack[i]), .a0(imra[3][i]), .a1(cmra[3][i]));
end endgenerate
 
im_alloc #(.VCN(N), .CMN(M), .SN(4))
LIM (
.IMr ( lreq ),
.IMa ( imra[4] ),
`ifndef ENABLE_CRRD
.CMs ( lcms ),
`endif
.cfg ( imc[4] ),
.rst_n ( rst_n )
);
 
rcb #(.NN(N), .MN(M), .DW(4))
LRIM (
.ireq ( lreq ),
.ira ( cmra[4] ),
.oreq ( lr ),
.ora ( lra ),
.gnt ( imc[4] )
);
 
generate for(i=0; i<N; i++) begin: LA
c2 UA (.q(lack[i]), .a0(imra[4][i]), .a1(cmra[4][i]));
end endgenerate
 
// CM schedulers
generate
for(i=0; i<M; i=i+1) begin: CMSch
cm_alloc S (
.sra ( sra[i] ),
.wra ( wra[i] ),
.nra ( nra[i] ),
.era ( era[i] ),
.lra ( lra[i] ),
.scfg ( scfg[i] ),
.ncfg ( ncfg[i] ),
.wcfg ( wcfg[i] ),
.ecfg ( ecfg[i] ),
.lcfg ( lcfg[i] ),
`ifndef ENABLE_CRRD
.s ( cms[i] ),
`endif
.wr ( wr[i] ),
.er ( er[i] ),
.sr ( sr[i] ),
.nr ( nr[i] ),
.lr ( lr[i] )
);
`ifndef ENABLE_CRRD
assign scms[i] = {cms[i][4], cms[i][3], cms[i][2], cms[i][1]};
assign wcms[i] = {cms[i][4], cms[i][3]};
assign ncms[i] = {cms[i][4], cms[i][3], cms[i][1], cms[i][0]};
assign ecms[i] = {cms[i][4], cms[i][1]};
assign lcms[i] = {cms[i][3], cms[i][2], cms[i][1], cms[i][0]};
`endif
end
endgenerate
 
endmodule // clos_sch
 
/sdm/src/im_alloc.v
0,0 → 1,123
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
IM allocator (the IM dispatcher in the thesis)
*** SystemVerilog is used ***
References
For the detail structure, please refer to Section 6.3.1 of the thesis:
Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
History:
05/09/2009 Initial version. <wsong83@gmail.com>
10/10/2009 Add the reset port. <wsong83@gmail.com>
05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
10/06/2010 [Major] change to use PIM structure. <wsong83@gmail.com>
23/08/2010 Fix the non-QDI request withdraw process. <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module im_alloc (/*AUTOARG*/
`ifndef ENABLE_CRRD
CMs,
`endif
// Outputs
IMa, cfg,
// Inputs
IMr, rst_n
) ;
// parameters
parameter VCN = 2; // the number of virtual circuits on one port
parameter CMN = 2; // the number of central modules
parameter SN = 2; // the possible output port choice of a port
 
input [VCN-1:0][SN-1:0] IMr; // the requests from virtual circuits
output [VCN-1:0] IMa; // switch ready, ack for the request
 
`ifndef ENABLE_CRRD
input [CMN-1:0][SN-1:0] CMs; // the states from CMs
`endif
input rst_n; // the negtive active reset
 
output [CMN-1:0][VCN-1:0] cfg; // the matrix configuration signals
 
// internal wires
`ifdef ENABLE_CRRD
`ifdef ENABLE_MRMA
wire [VCN-1:0] IPr; // request to the MRMA
wire [CMN-1:0] OPrdy, OPblk; // OP ready and blocked status
wire [CMN:0] OPrst_n; // the buffered resets to avoid metastability
`else
wire [VCN-1:0][CMN-1:0] IPr; // request to the MNMA
`endif
`else
// using the feedback from CMs
wire [VCN-1:0][CMN-1:0][SN-1:0] IPrm; // to generate the practical IPr
wire [VCN-1:0][CMN-1:0] IPr;
`endif
// generate variables
genvar i, j, k;
 
//----------------------------------------
// the PIM crossbar allocator
`ifndef ENABLE_MRMA
mnma #(.N(VCN), .M(CMN))
PIMA (
.cfg ( cfg ),
.r ( IPr ),
.ra ( IMa )
);
 
generate
for(i=0; i<VCN; i++) begin: IPC
for(j=0; j<CMN; j++) begin: OPC
`ifdef ENABLE_CRRD
IPr[i][j] = |IMr[i];
`else
IPr[i][j] = |IPrm[i][j];
for(k=0; k<SN; k++) begin: DIRC
c2p IPRen (.q(IPrm[i][j][k]), .a0(IMr[i][k]), .a1(~CMs[j][k]));
end
`endif
end
end // block: IPC
endgenerate
`else
mrma #(.N(VCN), .M(CMN))
PIMA (
.ca ( IMa ),
.ra ( OPblk ),
.cfg ( cfg ),
.c ( IPr ),
.r ( OPrdy ),
.rst_n ( rst_n )
);
generate
for(i=0; i<CMN; i++) begin: OPC
delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
assign OPrdy[i] = (~OPblk[i])&OPrst_n[i+1];
end
 
for(i=0; i<VCN; i++) begin: IPC
assign IPr[i] = |IMr[i];
end
endgenerate
`endif // !`ifndef ENABLE_MRMA
endmodule // im_alloc
/sdm/src/router.v
16,7 → 16,7
28/05/2009 Initial version. <wsong83@gmail.com>
23/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com>
22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
489,7 → 489,8
.nreq ( nreq ),
.lreq ( lreq ),
.wreq ( wreq ),
.ereq ( ereq )
.ereq ( ereq ),
.rst_n ( rst_n )
);
`endif
 
/sdm/src/sdm_sch.v
0,0 → 1,242
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Crossbar based SDM switch allocator
*** SystemVerilog is used ***
References
For the detail structure, please refer to Section 6.3.1 of the thesis:
Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
History:
28/09/2009 Initial version. <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module sdm_sch (/*AUTOARG*/
// Outputs
sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg,
// Inputs
sreq, nreq, lreq, wreq, ereq
);
parameter VCN = 2; // the number of virtual circuits per port
 
// income requests
input [VCN-1:0][3:0] sreq, nreq, lreq;
input [VCN-1:0][1:0] wreq, ereq;
 
// ack to input buffers
output [VCN-1:0] sack, wack, nack, eack, lack;
 
// configuration to the crossbar
output [VCN-1:0][1:0][VCN-1:0] scfg, ncfg;
output [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg;
 
input rst_n; // active low global reset
 
// requests to arbiters
`ifndef ENABLE_MRMA
wire [1:0][VCN-1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals
wire [3:0][VCN-1:0][VCN-1:0] r2w, r2e, r2l;
`else
wire [1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals
wire [3:0][VCN-1:0] r2w, r2e, r2l;
`endif
 
// ack from arbiters
wire [VCN-1:0][3:0] a2s, a2n, a2l;
wire [VCN-1:0][1:0] a2w, a2e;
 
// ack of the arbiters
wire [1:0][VCN-1:0] r2sa, r2na;
wire [3:0][VCN-1:0] r2wa, r2ea, r2la;
 
`ifdef ENABLE_MRMA
wire [VCN:0] OPrst_n; // the buffered resets to avoid metastability
wire [VCN-1:0] SOPrdy, SOPblk; // OP ready and blocked status
wire [VCN-1:0] WOPrdy, WOPblk; // OP ready and blocked status
wire [VCN-1:0] NOPrdy, NOPblk; // OP ready and blocked status
wire [VCN-1:0] EOPrdy, EOPblk; // OP ready and blocked status
wire [VCN-1:0] LOPrdy, LOPblk; // OP ready and blocked status
`endif
genvar i,j;
 
// wire shuffle
generate for(i=0; i<VCN; i++) begin: SHUF
`ifndef ENABLE_MRMA
for(j=0; j<VCN; j++) begin: CO
assign r2s[0][i][j] = nreq[i][0];
assign r2s[1][i][j] = lreq[i][0];
assign r2w[0][i][j] = sreq[i][0];
assign r2w[1][i][j] = nreq[i][1];
assign r2w[2][i][j] = ereq[i][0];
assign r2w[3][i][j] = lreq[i][1];
assign r2n[0][i][j] = sreq[i][1];
assign r2n[1][i][j] = lreq[i][2];
assign r2e[0][i][j] = sreq[i][2];
assign r2e[1][i][j] = wreq[i][0];
assign r2e[2][i][j] = nreq[i][2];
assign r2e[3][i][j] = lreq[i][3];
assign r2l[0][i][j] = sreq[i][3];
assign r2l[1][i][j] = wreq[i][1];
assign r2l[2][i][j] = nreq[i][3];
assign r2l[3][i][j] = ereq[i][1];
end // block: CO
`else // !`ifndef ENABLE_MRMA
assign r2s[0][i] = nreq[i][0];
assign r2s[1][i] = lreq[i][0];
assign r2w[0][i] = sreq[i][0];
assign r2w[1][i] = nreq[i][1];
assign r2w[2][i] = ereq[i][0];
assign r2w[3][i] = lreq[i][1];
assign r2n[0][i] = sreq[i][1];
assign r2n[1][i] = lreq[i][2];
assign r2e[0][i] = sreq[i][2];
assign r2e[1][i] = wreq[i][0];
assign r2e[2][i] = nreq[i][2];
assign r2e[3][i] = lreq[i][3];
assign r2l[0][i] = sreq[i][3];
assign r2l[1][i] = wreq[i][1];
assign r2l[2][i] = nreq[i][3];
assign r2l[3][i] = ereq[i][1];
`endif // !`ifndef ENABLE_MRMA
assign a2s[i][0] = r2wa[0][i];
assign a2s[i][1] = r2na[0][i];
assign a2s[i][2] = r2ea[0][i];
assign a2s[i][3] = r2la[0][i];
assign a2w[i][0] = r2ea[1][i];
assign a2w[i][1] = r2la[1][i];
assign a2n[i][0] = r2sa[0][i];
assign a2n[i][1] = r2wa[1][i];
assign a2n[i][2] = r2ea[2][i];
assign a2n[i][3] = r2la[2][i];
assign a2e[i][0] = r2wa[2][i];
assign a2e[i][1] = r2la[3][i];
assign a2l[i][0] = r2sa[1][i];
assign a2l[i][1] = r2wa[3][i];
assign a2l[i][2] = r2na[1][i];
assign a2l[i][3] = r2ea[3][i];
assign sack[i] = |a2s[i];
assign wack[i] = |a2w[i];
assign nack[i] = |a2n[i];
assign eack[i] = |a2e[i];
assign lack[i] = |a2l[i];
 
end // block: SHUF
endgenerate
 
// output port arbiter/allocators
`ifndef ENABLE_MRMA
mnma #(.N(2*VCN), .M(VCN))
SCBA (
.r ( r2s ),
.ra ( r2sa ),
.cfg ( scfg )
);
 
mnma #(.N(4*VCN), .M(VCN))
WCBA (
.r ( r2w ),
.ra ( r2wa ),
.cfg ( wcfg )
);
 
mnma #(.N(2*VCN), .M(VCN))
NCBA (
.r ( r2n ),
.ra ( r2na ),
.cfg ( ncfg )
);
 
mnma #(.N(4*VCN), .M(VCN))
ECBA (
.r ( r2e ),
.ra ( r2ea ),
.cfg ( ecfg )
);
 
mnma #(.N(4*VCN), .M(VCN))
LCBA (
.r ( r2l ),
.ra ( r2la ),
.cfg ( lcfg )
);
`else // !`ifndef ENABLE_MRMA
mrma #(.N(2*VCN), .M(VCN))
SCBA (
.ca ( r2sa ),
.ra ( SOPblk ),
.cfg ( scfg ),
.c ( r2s ),
.r ( SOPrdy ),
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
WCBA (
.ca ( r2wa ),
.ra ( WOPblk ),
.cfg ( wcfg ),
.c ( r2w ),
.r ( WOPrdy ),
.rst_n ( rst_n )
);
 
mrma #(.N(2*VCN), .M(VCN))
NCBA (
.ca ( r2na ),
.ra ( NOPblk ),
.cfg ( ncfg ),
.c ( r2n ),
.r ( NOPrdy ),
.rst_n ( rst_n )
);
 
mrma #(.N(4*VCN), .M(VCN))
ECBA (
.ca ( r2ea ),
.ra ( EOPblk ),
.cfg ( ecfg ),
.c ( r2e ),
.r ( EOPrdy ),
.rst_n ( rst_n )
);
mrma #(.N(4*VCN), .M(VCN))
LCBA (
.ca ( r2la ),
.ra ( LOPblk ),
.cfg ( lcfg ),
.c ( r2l ),
.r ( LOPrdy ),
.rst_n ( rst_n )
);
generate
for(i=0; i<VCN; i++) begin: OPC
delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
assign SOPrdy[i] = (~SOPblk[i])&SOPrst_n[i+1];
assign WOPrdy[i] = (~WOPblk[i])&WOPrst_n[i+1];
assign NOPrdy[i] = (~NOPblk[i])&NOPrst_n[i+1];
assign EOPrdy[i] = (~EOPblk[i])&EOPrst_n[i+1];
assign LOPrdy[i] = (~LOPblk[i])&LOPrst_n[i+1];
end
endgenerate
`endif // !`ifndef ENABLE_MRMA
endmodule // sdm_sch
/sdm/src/cm_alloc.v
0,0 → 1,95
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
CM allocator (the CM dispatcher in the thesis)
*** SystemVerilog is used ***
References
For the detail structure, please refer to Section 6.3.1 of the thesis:
Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011.
History:
08/09/2009 Initial version. <wsong83@gmail.com>
20/09/2010 Modified for the Clos SDM router <wsong83@cs.man.ac.uk>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module cm_alloc (/*AUTOARG*/
`ifndef ENABLE_CRRD
s,
`endif
// Outputs
sra, wra, nra, era, lra, scfg, ncfg, wcfg, ecfg, lcfg,
// Inputs
wr, er, sr, nr, lr
) ;
 
//requests from all IMs
input [1:0] wr, er;
input [3:0] sr, nr, lr;
 
// ack to IMs
output sra, wra, nra, era, lra;
 
// the configuration to the local CM
output [1:0] scfg, ncfg;
output [3:0] wcfg, ecfg, lcfg;
 
// when using the asynchronous dispatching algorithm, status is sent back to IMs
`ifndef ENABLE_CRRD
output [4:0] s;
`endif
 
// arbiters
mutex_arb #(2)
SA ( .req ( {lr[0], nr[0]} ),
.gnt ( scfg )
);
 
mutex_arb #(4)
WA ( .req ( {lr[1], er[0], nr[1], sr[0]} ),
.gnt ( wcfg )
);
 
mutex_arb #(2)
NA ( .req ( {lr[2], sr[1]} ),
.gnt ( ncfg )
);
 
mutex_arb #(4)
EA ( .req ( {lr[3], nr[2], wr[0], sr[2]} ),
.gnt ( ecfg )
);
 
mutex_arb #(4)
LA ( .req ( {er[1], nr[3], wr[1], sr[3]} ),
.gnt ( lcfg )
);
 
// generating the ack
assign sra = |{wcfg[0], ncfg[0], ecfg[0], lcfg[0]};
assign wra = |{ecfg[1], lcfg[1]};
assign nra = |{scfg[0], wcfg[1], ecfg[2], lcfg[2]};
assign era = |{wcfg[2], lcfg[3]};
assign lra = |{scfg[1], wcfg[3], ncfg[1], ecfg[3]};
 
// generating the status
`ifndef ENABLE_CRRD
assign s = {|lcfg, |ecfg, |ncfg, |wcfg, |scfg};
`endif
 
endmodule // cm_alloc
 
 
sdm/src/cm_alloc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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