Subversion Repositories async_sdm_noc

/common/src/mrma.v File deleted

/common/src/pipe4.v File deleted

/common/src/ctree.v File deleted

/common/src/tree_arb.v File deleted

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/common/src/mutex_arb.v File deleted

/common/src/rcb.v File deleted

/common/src/dcb_xy.v File deleted

common/src/dcb_xy.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: common/src/mnma.v =================================================================== --- common/src/mnma.v (revision 19) +++ common/src/mnma.v (nonexistent) @@ -1,92 +0,0 @@ -/* - Asynchronous SDM NoC - (C)2011 Wei Song - Advanced Processor Technologies Group - Computer Science, the Univ. of Manchester, UK - - Authors: - Wei Song wsong83@gmail.com - - License: LGPL 3.0 or later - - M-N Match allocator - *** SystemVerilog is used *** - - References - Thomas E. Anderson, Susan S. Owicki, James B. Saxe and Charles P. Thacker, High-speed switch scheduling for local-area networks, ACM Transactions on Computer Systems, 1993(11), 319-352. - - For the detail structure, please refer to Section 6.3.1 of the thesis: - Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011. - - History: - 09/06/2010 Initial version. - 08/03/2011 Tree arbiter cannot be used as the requests are not allowed to drop before ack. - 24/05/2011 Clean up for opensource. - -*/ - -module mnma(/*AUTOARG*/ - // Outputs - cfg, - // Inputs - r - ); - parameter N = 2; // number of input requests - parameter M = 2; // number of resources - - input [N-1:0][M-1:0] r; // input requests - output [M-1:0][N-1:0] cfg; // configuration to the crssbar - - wire [M-1:0][N-1:0] OPr; - wire [M-1:0][N-1:0] OPg; - wire [M-1:0][N-1:0][M-1:0] OPren; - wire [N-1:0][M-1:0] IPr; - wire [N-1:0][M-1:0] IPg; - - genvar i,j,k; - - //------------------------------------- - // OP arbiters - generate - for(i=0; ik is settle - end - and AND_OPRen (OPr[i][j], r[j][i] ,(~|OPren[i][j])); - assign cfg[i][j] = IPg[j][i]; - assign IPr[j][i] = OPg[i][j]; - end // block: CI - end // block: CO - endgenerate - -endmodule // mnma - - Index: common/src/dcb.v =================================================================== --- common/src/dcb.v (revision 19) +++ common/src/dcb.v (nonexistent) @@ -1,113 +0,0 @@ -/* - Asynchronous SDM NoC - (C)2011 Wei Song - Advanced Processor Technologies Group - Computer Science, the Univ. of Manchester, UK - - Authors: - Wei Song wsong83@gmail.com - - License: LGPL 3.0 or later - - Data crossbar for wormhole and SDM routers. - *** SystemVerilog is used *** - - History: - 17/07/2010 Initial version. - 23/05/2011 Clean up for opensource. - -*/ - -// the router structure definitions -`include "define.v" - -module dcb (/*AUTOARG*/ - // Outputs - o0, o1, o2, o3, ia, o4, - // Inputs - i0, i1, i2, i3, oa, i4, cfg - ); - - parameter NN = 2; // number of input ports - parameter MN = 3; // number of output ports - parameter DW = 8; // data-width of a port - parameter SCN = DW/2; // number of 1-of-4 sub-channels for one port - - input [NN-1:0][SCN-1:0] i0, i1, i2, i3; // input ports - output [MN-1:0][SCN-1:0] o0, o1, o2, o3; // output ports - -`ifdef ENABLE_CHANNEL_SLICING - output [NN-1:0][SCN-1:0] ia, o4; // eof and ack - input [MN-1:0][SCN-1:0] oa, i4; -`else - output [NN-1:0] ia, o4; // eof and ack - input [MN-1:0] oa, i4; -`endif - - input [MN-1:0][NN-1:0] cfg; // crossbar configuration - - wire [MN-1:0][SCN-1:0][NN-1:0] dm0, dm1, dm2, dm3; - -`ifdef ENABLE_CHANNEL_SLICING - wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4; -`else - wire [NN-1:0][MN-1:0] am, dm4; -`endif - - genvar i, j, k; - - generate - for(i=0; i -# 21/05/2011 Change to the Nangate cell library. - -set_dont_touch mutex -set_dont_touch delay - -uniquify -force - -# C-gates on control path -foreach_in_collection celln [get_references -hierarchical c2_*] { - set_disable_timing [get_object_name $celln]/U2 -from B -to Z - set_disable_timing [get_object_name $celln]/U3 -from B -to Z -} - -# C-gates on data path, feedback and data input are disabled from timing analysis -foreach_in_collection celln [get_references -hierarchical dc2_*] { - set_disable_timing [get_object_name $celln]/U1 -from B -to Z - set_disable_timing [get_object_name $celln]/U2 -from A -to Z - set_disable_timing [get_object_name $celln]/U2 -from B -to Z - set_disable_timing [get_object_name $celln]/U3 -from B -to Z -} - -# c2n gates -foreach_in_collection celln [get_references -hierarchical c2n_*] { - set_disable_timing [get_object_name $celln]/U1 -from B -to Z -} - -# c2p gates -foreach_in_collection celln [get_references -hierarchical c2p_*] { - set_disable_timing [get_object_name $celln]/U1 -from B -to O -} - -# mutex gates -foreach_in_collection celln [get_references -hierarchical mutex_*] { - set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN - set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN - set_dont_touch [get_object_name $celln]/U2 - set_dont_touch [get_object_name $celln]/U3 -} - -# c2p1 gates -foreach_in_collection celln [get_references -hierarchical c2p1_*] { - set_disable_timing [get_object_name $celln]/U2 -from B -to Z - set_disable_timing [get_object_name $celln]/U3 -from B -to Z -} - -# tarb -foreach_in_collection celln [get_references -hierarchical tarb_*] { - set_disable_timing [get_object_name $celln]/U2 -from A -to Z - set_disable_timing [get_object_name $celln]/U3 -from A -to Z -} - -# cr_blk -foreach_in_collection celln [get_references -hierarchical cr_blk_*] { - set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z -} - Index: common/script/tech.tcl =================================================================== --- common/script/tech.tcl (revision 19) +++ common/script/tech.tcl (nonexistent) @@ -1,28 +0,0 @@ -# Asynchronous SDM NoC -# (C)2011 Wei Song -# Advanced Processor Technologies Group -# Computer Science, the Univ. of Manchester, UK -# -# Authors: -# Wei Song wsong83@gmail.com -# -# License: LGPL 3.0 or later -# -# Script for cell library setting up. -# currently using the Nangate 45nm cell lib. -# -# History: -# 05/07/2009 Initial version. -# 20/05/2011 Change to the Nangate cell library. - -set rm_lib_dirs "../../lib" - -set rm_library "Nangate_typ.db" - -set search_path [concat ${search_path} "${rm_lib_dirs}/"] - -set synthetic_library dw_foundation.sldb -set link_library [list *] -set link_library [concat ${link_library} ${rm_library} $synthetic_library] -set target_library "${rm_library}" - Index: AUTHORS =================================================================== --- AUTHORS (revision 19) +++ AUTHORS (nonexistent) @@ -1,3 +0,0 @@ -Wei Song wsong83@gmail.com Computer Science, the University of Manchester, Manchester M13 9PL, United Kingdom -Doug Edwards doug@cs.man.ac.uk Computer Science, the University of Manchester, Manchester M13 9PL, United Kingdom -