Subversion Repositories async_sdm_noc

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common/src/dcb_xy.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: common/src/mnma.v =================================================================== --- common/src/mnma.v (revision 19) +++ common/src/mnma.v (nonexistent) @@ -1,92 +0,0 @@ -/* - Asynchronous SDM NoC - (C)2011 Wei Song - Advanced Processor Technologies Group - Computer Science, the Univ. of Manchester, UK - - Authors: - Wei Song wsong83@gmail.com - - License: LGPL 3.0 or later - - M-N Match allocator - *** SystemVerilog is used *** - - References - Thomas E. Anderson, Susan S. Owicki, James B. Saxe and Charles P. Thacker, High-speed switch scheduling for local-area networks, ACM Transactions on Computer Systems, 1993(11), 319-352. - - For the detail structure, please refer to Section 6.3.1 of the thesis: - Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011. - - History: - 09/06/2010 Initial version. - 08/03/2011 Tree arbiter cannot be used as the requests are not allowed to drop before ack. - 24/05/2011 Clean up for opensource. - -*/ - -module mnma(/*AUTOARG*/ - // Outputs - cfg, - // Inputs - r - ); - parameter N = 2; // number of input requests - parameter M = 2; // number of resources - - input [N-1:0][M-1:0] r; // input requests - output [M-1:0][N-1:0] cfg; // configuration to the crssbar - - wire [M-1:0][N-1:0] OPr; - wire [M-1:0][N-1:0] OPg; - wire [M-1:0][N-1:0][M-1:0] OPren; - wire [N-1:0][M-1:0] IPr; - wire [N-1:0][M-1:0] IPg; - - genvar i,j,k; - - //------------------------------------- - // OP arbiters - generate - for(i=0; ik is settle - end - and AND_OPRen (OPr[i][j], r[j][i] ,(~|OPren[i][j])); - assign cfg[i][j] = IPg[j][i]; - assign IPr[j][i] = OPg[i][j]; - end // block: CI - end // block: CO - endgenerate - -endmodule // mnma - - Index: common/src/dcb.v =================================================================== --- common/src/dcb.v (revision 19) +++ common/src/dcb.v (nonexistent) @@ -1,113 +0,0 @@ -/* - Asynchronous SDM NoC - (C)2011 Wei Song - Advanced Processor Technologies Group - Computer Science, the Univ. of Manchester, UK - - Authors: - Wei Song wsong83@gmail.com - - License: LGPL 3.0 or later - - Data crossbar for wormhole and SDM routers. - *** SystemVerilog is used *** - - History: - 17/07/2010 Initial version. - 23/05/2011 Clean up for opensource. - -*/ - -// the router structure definitions -`include "define.v" - -module dcb (/*AUTOARG*/ - // Outputs - o0, o1, o2, o3, ia, o4, - // Inputs - i0, i1, i2, i3, oa, i4, cfg - ); - - parameter NN = 2; // number of input ports - parameter MN = 3; // number of output ports - parameter DW = 8; // data-width of a port - parameter SCN = DW/2; // number of 1-of-4 sub-channels for one port - - input [NN-1:0][SCN-1:0] i0, i1, i2, i3; // input ports - output [MN-1:0][SCN-1:0] o0, o1, o2, o3; // output ports - -`ifdef ENABLE_CHANNEL_SLICING - output [NN-1:0][SCN-1:0] ia, o4; // eof and ack - input [MN-1:0][SCN-1:0] oa, i4; -`else - output [NN-1:0] ia, o4; // eof and ack - input [MN-1:0] oa, i4; -`endif - - input [MN-1:0][NN-1:0] cfg; // crossbar configuration - - wire [MN-1:0][SCN-1:0][NN-1:0] dm0, dm1, dm2, dm3; - -`ifdef ENABLE_CHANNEL_SLICING - wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4; -`else - wire [NN-1:0][MN-1:0] am, dm4; -`endif - - genvar i, j, k; - - generate - for(i=0; i - 05/11/2009 Speed up the arbiter. - 24/05/2011 Clean up for opensource. - -*/ - -module mrma (/*AUTOARG*/ - // Outputs - ca, ra, cfg, - // Inputs - c, r, rst_n - ); - - // parameters - parameter N = 2; // the number of requests/clients - parameter M = 2; // the number of resources - - input [N-1:0] c; // requests/clients - output [N-1:0] ca; // requests ack - - input [M-1:0] r; // resources - output [M-1:0] ra; // resource ack - - output [M-1:0][N-1:0] cfg; // the generated configuration - wire [N-1:0][M-1:0] scfg; - - wire [M-1:0][N-1:0] hs; // match results - wire [M-1:0][N-1:0] blk; // blockage - wire [N-1:0][M-1:0] cblk; // shuffled blockage - wire [M-1:0] rblk; // resource blockage - wire [N-1:0] cblk; // client blockage - wire [N-1:0] cg, cm; // client requests - wire [M-1:0] rg, rm; // resource requests - - input rst_n; // active low reset - - // generate variables - genvar i, j; - - - // input arbiters - tree_arb #(N) CIArb ( - .req ( cm ), - .gnt ( cg ) - ); - - tree_arb #(M) RIArb ( - .req ( rm ), - .gnt ( rg ) - ); - - generate - // tile matrix - for (i=0; i - 17/04/2011 Replace the common ack generation. - 23/05/2011 Clean up for opensource. - -*/ - -// the router structure definitions -`include "define.v" - -module pipe4(/*AUTOARG*/ - // Outputs - ia, o0, o1, o2, o3, - // Inputs - i0, i1, i2, i3, oa -`ifdef ENABLE_EOF - , i4, o4 -`endif - ); - - parameter DW = 32; // the data width of the pipeline stage - parameter SCN = DW/2; // the number of 1-of-4 sub-stage required - - input [SCN-1:0] i0, i1, i2, i3; - output [SCN-1:0] o0, o1, o2, o3; - input oa; // input ack - output ia; // output ack - -`ifdef ENABLE_EOF - input o4; // the eof bit - output i4; -`endif - - // internal signals - wire [2*SCN-2:0] tack; - - // generate the ack line - genvar i; - - // the data pipe stage - generate for (i=0; i - 23/05/2011 Clean up for opensource. - -*/ - -module ctree (/*AUTOARG*/ - // Outputs - co, - // Inputs - ci - ); - - parameter DW = 2; // the total number of leaves of the C-element tree - - input [DW-1:0] ci; // all input leaves - output co; // the combined output - - wire [2*DW-2:0] dat; - genvar i; - - assign dat[DW-1:0] = ci; - - generate for (i=0; i