OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches
    from Rev 38 to Rev 39
    ↔ Reverse comparison
  •

Rev 38 → Rev 39

/init/vc/src/fcctl.v
0,0 → 1,62
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Flow control unit.
History:
31/03/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbar. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module fcctl ( /*AUTOARG*/
// Outputs
afc, ro,
// Inputs
credit, ri, rst
);
parameter VCN = 2; // number of VCs per direction
parameter PD = 3; // depth of an input VC buffer
input [VCN-1:0] credit; // credit input from the next router
output [VCN-1:0] afc; // ack for the credit input
input [VCN-1:0] ri; // VC request from VCA
output [VCN-1:0] ro; // credit grant output
input rst; // active high reset
 
wire [PD:0][VCN-1:0] cp, cpa;
 
genvar i,j;
 
// the credit pipeline
generate
for(i=0; i<PD; i++) begin: P
for(j=0; j<VCN; j++) begin: V
cpipe CP (.cia(cpa[i][j]), .co(cp[i+1][j]), .rst(rst), .ci(cp[i][j]), .coa(cpa[i+1][j]));
end
end
endgenerate
 
// grant a credit to a VC request
generate
for(i=0; i<VCN; i++) begin:R
dc2 CR (.a(ri[i]), .d(cp[PD][i]), .q(cpa[PD][i]));
end
endgenerate
 
assign ro = cpa[PD];
assign cp[0] = credit;
assign afc = cpa[0];
 
endmodule // fcctl
 
/init/vc/src/dcb_vc.v
0,0 → 1,310
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
data crossbar for the VC router
History:
04/04/2010 Initial version. <wsong83@gmail.com>
12/05/2010 Use MPxP crossbar. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module dcb_vc (/*AUTOARG*/
// Outputs
dia, do0, do1, do2, do3, dot,
// Inputs
di0, di1, di2, di3, dit, srtg, nrtg, lrtg, wrtg, ertg, doa
);
parameter DW = 32; // data width of a VC
parameter FT = 3; // wire count of the flit tyoe bus
parameter VCN = 2; // number of VC per direction
parameter SCN = DW/2;
 
input [4:0][VCN-1:0][SCN-1:0] di0, di1, di2, di3; // data input
input [4:0][VCN-1:0][FT-1:0] dit; // flit type input
output [4:0][VCN-1:0] dia; // input ack
input [VCN-1:0][3:0] srtg, nrtg, lrtg; // routing guide
input [VCN-1:0][1:0] wrtg, ertg;
 
output [4:0][SCN-1:0] do0, do1, do2, do3; // data output
output [4:0][FT-1:0] dot; // flit type output
input [4:0] doa; // output ack
 
// internal wires
wire [VCN-1:0][3:0][SCN-1:0] s0, s1, s2, s3;
wire [VCN-1:0][3:0][FT-1:0] sft;
wire [VCN-1:0][3:0] sa;
wire [VCN-1:0][1:0][SCN-1:0] w0, w1, w2, w3;
wire [VCN-1:0][1:0][FT-1:0] wft;
wire [VCN-1:0][1:0] wa;
wire [VCN-1:0][3:0][SCN-1:0] n0, n1, n2, n3;
wire [VCN-1:0][3:0][FT-1:0] nft;
wire [VCN-1:0][3:0] na;
wire [VCN-1:0][1:0][SCN-1:0] e0, e1, e2, e3;
wire [VCN-1:0][1:0][FT-1:0] eft;
wire [VCN-1:0][1:0] ea;
wire [VCN-1:0][3:0][SCN-1:0] l0, l1, l2, l3;
wire [VCN-1:0][3:0][FT-1:0] lft;
wire [VCN-1:0][3:0] la;
 
wire [3:0][SCN-1:0][VCN-1:0] ss0, ss1, ss2, ss3;
wire [3:0][FT-1:0][VCN-1:0] ssft;
wire [1:0][SCN-1:0][VCN-1:0] sw0, sw1, sw2, sw3;
wire [1:0][FT-1:0][VCN-1:0] swft;
wire [3:0][SCN-1:0][VCN-1:0] sn0, sn1, sn2, sn3;
wire [3:0][FT-1:0][VCN-1:0] snft;
wire [1:0][SCN-1:0][VCN-1:0] se0, se1, se2, se3;
wire [1:0][FT-1:0][VCN-1:0] seft;
wire [3:0][SCN-1:0][VCN-1:0] sl0, sl1, sl2, sl3;
wire [3:0][FT-1:0][VCN-1:0] slft;
 
wire [3:0][SCN-1:0] ms0, ms1, ms2, ms3;
wire [3:0][FT-1:0] msft;
wire [1:0][SCN-1:0] mw0, mw1, mw2, mw3;
wire [1:0][FT-1:0] mwft;
wire [3:0][SCN-1:0] mn0, mn1, mn2, mn3;
wire [3:0][FT-1:0] mnft;
wire [1:0][SCN-1:0] me0, me1, me2, me3;
wire [1:0][FT-1:0] meft;
wire [3:0][SCN-1:0] ml0, ml1, ml2, ml3;
wire [3:0][FT-1:0] mlft;
 
genvar i,j,k;
generate
// demux using the routing guides
for(i=0; i<VCN; i++) begin: IMX
vcdmux #(.DW(DW), .VCN(4))
SDMX(
.dia ( dia[0][i] ),
.do0 ( s0[i] ),
.do1 ( s1[i] ),
.do2 ( s2[i] ),
.do3 ( s3[i] ),
.dot ( sft[i] ),
.di0 ( di0[0][i] ),
.di1 ( di1[0][i] ),
.di2 ( di2[0][i] ),
.di3 ( di3[0][i] ),
.dit ( dit[0][i] ),
.divc ( srtg[i] ),
.doa ( sa[i] )
);
vcdmux #(.DW(DW), .VCN(2))
WDMX(
.dia ( dia[1][i] ),
.do0 ( w0[i] ),
.do1 ( w1[i] ),
.do2 ( w2[i] ),
.do3 ( w3[i] ),
.dot ( wft[i] ),
.di0 ( di0[1][i] ),
.di1 ( di1[1][i] ),
.di2 ( di2[1][i] ),
.di3 ( di3[1][i] ),
.dit ( dit[1][i] ),
.divc ( wrtg[i] ),
.doa ( wa[i] )
);
 
vcdmux #(.DW(DW), .VCN(4))
NDMX(
.dia ( dia[2][i] ),
.do0 ( n0[i] ),
.do1 ( n1[i] ),
.do2 ( n2[i] ),
.do3 ( n3[i] ),
.dot ( nft[i] ),
.di0 ( di0[2][i] ),
.di1 ( di1[2][i] ),
.di2 ( di2[2][i] ),
.di3 ( di3[2][i] ),
.dit ( dit[2][i] ),
.divc ( nrtg[i] ),
.doa ( na[i] )
);
vcdmux #(.DW(DW), .VCN(2))
EDMX(
.dia ( dia[3][i] ),
.do0 ( e0[i] ),
.do1 ( e1[i] ),
.do2 ( e2[i] ),
.do3 ( e3[i] ),
.dot ( eft[i] ),
.di0 ( di0[3][i] ),
.di1 ( di1[3][i] ),
.di2 ( di2[3][i] ),
.di3 ( di3[3][i] ),
.dit ( dit[3][i] ),
.divc ( ertg[i] ),
.doa ( ea[i] )
);
 
vcdmux #(.DW(DW), .VCN(4))
LDMX(
.dia ( dia[4][i] ),
.do0 ( l0[i] ),
.do1 ( l1[i] ),
.do2 ( l2[i] ),
.do3 ( l3[i] ),
.dot ( lft[i] ),
.di0 ( di0[4][i] ),
.di1 ( di1[4][i] ),
.di2 ( di2[4][i] ),
.di3 ( di3[4][i] ),
.dit ( dit[4][i] ),
.divc ( lrtg[i] ),
.doa ( la[i] )
);
// acknowledgement
c2 SA0 (.a0(srtg[i][0]), .a1(doa[1]), .q(sa[i][0]));
c2 SA1 (.a0(srtg[i][1]), .a1(doa[2]), .q(sa[i][1]));
c2 SA2 (.a0(srtg[i][2]), .a1(doa[3]), .q(sa[i][2]));
c2 SA3 (.a0(srtg[i][3]), .a1(doa[4]), .q(sa[i][3]));
c2 WA0 (.a0(wrtg[i][0]), .a1(doa[3]), .q(wa[i][0]));
c2 WA1 (.a0(wrtg[i][1]), .a1(doa[4]), .q(wa[i][1]));
c2 NA0 (.a0(nrtg[i][0]), .a1(doa[0]), .q(na[i][0]));
c2 NA1 (.a0(nrtg[i][1]), .a1(doa[1]), .q(na[i][1]));
c2 NA2 (.a0(nrtg[i][2]), .a1(doa[3]), .q(na[i][2]));
c2 NA3 (.a0(nrtg[i][3]), .a1(doa[4]), .q(na[i][3]));
c2 EA0 (.a0(ertg[i][0]), .a1(doa[1]), .q(ea[i][0]));
c2 EA1 (.a0(ertg[i][1]), .a1(doa[4]), .q(ea[i][1]));
c2 LA0 (.a0(lrtg[i][0]), .a1(doa[0]), .q(la[i][0]));
c2 LA1 (.a0(lrtg[i][1]), .a1(doa[1]), .q(la[i][1]));
c2 LA2 (.a0(lrtg[i][2]), .a1(doa[2]), .q(la[i][2]));
c2 LA3 (.a0(lrtg[i][3]), .a1(doa[3]), .q(la[i][3]));
 
end // block: IMX
endgenerate
 
generate
for(i=0; i<VCN; i++) begin: V
for(j=0; j<4; j++) begin: D0
for(k=0; k<SCN; k++) begin: D
assign ss0[j][k][i] = s0[i][j][k];
assign ss1[j][k][i] = s1[i][j][k];
assign ss2[j][k][i] = s2[i][j][k];
assign ss3[j][k][i] = s3[i][j][k];
assign sn0[j][k][i] = n0[i][j][k];
assign sn1[j][k][i] = n1[i][j][k];
assign sn2[j][k][i] = n2[i][j][k];
assign sn3[j][k][i] = n3[i][j][k];
assign sl0[j][k][i] = l0[i][j][k];
assign sl1[j][k][i] = l1[i][j][k];
assign sl2[j][k][i] = l2[i][j][k];
assign sl3[j][k][i] = l3[i][j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign ssft[j][k][i] = sft[i][j][k];
assign snft[j][k][i] = nft[i][j][k];
assign slft[j][k][i] = lft[i][j][k];
end // block: T
end // block: D0
for(j=0; j<2; j++) begin: D1
for(k=0; k<SCN; k++) begin: D
assign sw0[j][k][i] = w0[i][j][k];
assign sw1[j][k][i] = w1[i][j][k];
assign sw2[j][k][i] = w2[i][j][k];
assign sw3[j][k][i] = w3[i][j][k];
assign se0[j][k][i] = e0[i][j][k];
assign se1[j][k][i] = e1[i][j][k];
assign se2[j][k][i] = e2[i][j][k];
assign se3[j][k][i] = e3[i][j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign swft[j][k][i] = wft[i][j][k];
assign seft[j][k][i] = eft[i][j][k];
end // block: T
end // block: D1
end
 
for(j=0; j<4; j++) begin: D2
for(k=0; k<SCN; k++) begin: D
assign ms0[j][k] = |ss0[j][k];
assign ms1[j][k] = |ss1[j][k];
assign ms2[j][k] = |ss2[j][k];
assign ms3[j][k] = |ss3[j][k];
assign mn0[j][k] = |sn0[j][k];
assign mn1[j][k] = |sn1[j][k];
assign mn2[j][k] = |sn2[j][k];
assign mn3[j][k] = |sn3[j][k];
assign ml0[j][k] = |sl0[j][k];
assign ml1[j][k] = |sl1[j][k];
assign ml2[j][k] = |sl2[j][k];
assign ml3[j][k] = |sl3[j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign msft[j][k] = |ssft[j][k];
assign mnft[j][k] = |snft[j][k];
assign mlft[j][k] = |slft[j][k];
end
end // block: D2
 
for(j=0; j<2; j++) begin: D4
for(k=0; k<SCN; k++) begin: D
assign mw0[j][k] = |sw0[j][k];
assign mw1[j][k] = |sw1[j][k];
assign mw2[j][k] = |sw2[j][k];
assign mw3[j][k] = |sw3[j][k];
assign me0[j][k] = |se0[j][k];
assign me1[j][k] = |se1[j][k];
assign me2[j][k] = |se2[j][k];
assign me3[j][k] = |se3[j][k];
end // block: D
for(k=0; k<FT; k++) begin: T
assign mwft[j][k] = |swft[j][k];
assign meft[j][k] = |seft[j][k];
end // block: T
end // block: D4
endgenerate
// south output
assign do0[0] = mn0[0]|ml0[0];
assign do1[0] = mn1[0]|ml1[0];
assign do2[0] = mn2[0]|ml2[0];
assign do3[0] = mn3[0]|ml3[0];
assign dot[0] = mnft[0]|mlft[0];
 
// west output
assign do0[1] = ms0[0]|mn0[1]|me0[0]|ml0[1];
assign do1[1] = ms1[0]|mn1[1]|me1[0]|ml1[1];
assign do2[1] = ms2[0]|mn2[1]|me2[0]|ml2[1];
assign do3[1] = ms3[0]|mn3[1]|me3[0]|ml3[1];
assign dot[1] = msft[0]|mnft[1]|meft[0]|mlft[1];
 
// south output
assign do0[2] = ms0[1]|ml0[2];
assign do1[2] = ms1[1]|ml1[2];
assign do2[2] = ms2[1]|ml2[2];
assign do3[2] = ms3[1]|ml3[2];
assign dot[2] = msft[1]|mlft[2];
 
// east output
assign do0[3] = ms0[2]|mw0[0]|mn0[2]|ml0[3];
assign do1[3] = ms1[2]|mw1[0]|mn1[2]|ml1[3];
assign do2[3] = ms2[2]|mw2[0]|mn2[2]|ml2[3];
assign do3[3] = ms3[2]|mw3[0]|mn3[2]|ml3[3];
assign dot[3] = msft[2]|mwft[0]|mnft[2]|mlft[3];
 
// local output
assign do0[4] = ms0[3]|mw0[1]|mn0[3]|me0[1];
assign do1[4] = ms1[3]|mw1[1]|mn1[3]|me1[1];
assign do2[4] = ms2[3]|mw2[1]|mn2[3]|me2[1];
assign do3[4] = ms3[3]|mw3[1]|mn3[3]|me3[1];
assign dot[4] = msft[3]|mwft[1]|mnft[3]|meft[1];
 
 
endmodule // dcb_vc
/init/vc/src/ddmux.v
0,0 → 1,57
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Demux for a 1-of-n buffer stage.
History:
31/03/2010 Initial version. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module ddmux ( /*AUTOARG*/
// Outputs
d_in_a, d_out,
// Inputs
d_in, d_sel, d_out_a
);
parameter VCN = 2; // number of output VCs
parameter DW = 32; // data width of the input
 
input [DW-1:0] d_in;
input [VCN-1:0] d_sel;
output d_in_a;
 
output [VCN-1:0][DW-1:0] d_out;
input [VCN-1:0] d_out_a;
genvar i,j;
 
/*
generate
for (i=0; i<VCN; i++) begin: VCD
for(j=0; j<DW; j++) begin: D
c2 C (.a0(d_in[j]), .a1(d_sel[i]), .q(d_out[i][j]));
end
end
endgenerate
*/
generate
for (i=0; i<VCN; i++) begin: VCD
assign d_out[i] = d_sel[i] ? d_in : 0;
end
endgenerate
assign d_in_a = |d_out_a;
 
endmodule // ddmux
 
/init/vc/src/vcdmux.v
0,0 → 1,71
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Demux for a VC buffer stage.
History:
31/03/2010 Initial version. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
module vcdmux ( /*AUTOARG*/
// Outputs
dia, do0, do1, do2, do3, dot,
// Inputs
di0, di1, di2, di3, dit, divc, doa
);
parameter VCN = 2; // number of output VCs
parameter DW = 32; // data width of the input
parameter SCN = DW/2;
 
input [SCN-1:0] di0, di1, di2, di3;
input [2:0] dit;
input [VCN-1:0] divc;
output dia;
 
output [VCN-1:0][SCN-1:0] do0, do1, do2, do3;
output [VCN-1:0][2:0] dot;
input [VCN-1:0] doa;
genvar i,j;
 
/*
generate
for (i=0; i<VCN; i++) begin: VCD
for(j=0; j<SCN; j++) begin: D
c2 C0 (.a0(di0[j]), .a1(divc[i]), .q(do0[i][j]));
c2 C1 (.a0(di1[j]), .a1(divc[i]), .q(do1[i][j]));
c2 C2 (.a0(di2[j]), .a1(divc[i]), .q(do2[i][j]));
c2 C3 (.a0(di3[j]), .a1(divc[i]), .q(do3[i][j]));
end
for(j=0; j<3; j++) begin: T
c2 C0 (.a0(dit[j]), .a1(divc[i]), .q(dot[i][j]));
end
end
endgenerate
*/
generate
for (i=0; i<VCN; i++) begin: VCD
assign do0[i] = divc[i] ? di0 : 0;
assign do1[i] = divc[i] ? di1 : 0;
assign do2[i] = divc[i] ? di2 : 0;
assign do3[i] = divc[i] ? di3 : 0;
assign dot[i] = divc[i] ? dit : 0;
end
endgenerate
 
assign dia = |doa;
 
endmodule // vcdmux
 
/init/vc/src/vca.v
0,0 → 1,418
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
VC allocator.
History:
05/04/2010 Initial version. <wsong83@gmail.com>
29/09/2010 Use the asynchronous PIM alg. (MNMA) <wsong83@gmail.com>
03/10/2010 Add VCREN c2n gates to defer the withdrawal of request until data switch is withdrawn. <wsong83@gmail.com>
02/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module vcalloc (/*AUTOARG*/
// Outputs
svcra, wvcra, nvcra, evcra, lvcra, sswa, wswa, nswa, eswa, lswa,
sosr, wosr, nosr, eosr, losr,
// Inputs
svcr, nvcr, lvcr, wvcr, evcr, sswr, wswr, nswr, eswr, lswr, sosa,
wosa, nosa, eosa, losa, rstn
);
 
parameter VCN = 4; // number of VCs
 
input [VCN-1:0][3:0] svcr, nvcr, lvcr; // VC requests from input VCs
input [VCN-1:0][1:0] wvcr, evcr;
output [VCN-1:0] svcra,wvcra, nvcra, evcra, lvcra; // ack to VC requests
input [VCN-1:0][1:0] sswr, wswr, nswr, eswr, lswr; // SW requests from input VCs
output [VCN-1:0][3:0] sswa, nswa, lswa; // ack/routing guide to input VCs
output [VCN-1:0][1:0] wswa, eswa;
output [VCN-1:0] sosr, wosr, nosr, eosr, losr; // SW requests to output VCs
input [VCN-1:0] sosa, wosa, nosa, eosa, losa;
input rstn; // active-low reset
wire [VCN-1:0][3:0] msvcr, mnvcr, mlvcr; // shuffled VC requests
wire [VCN-1:0][1:0] mwvcr, mevcr;
 
wire [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; // configuration signals from VCA to Req CB
wire [VCN-1:0][1:0][VCN-1:0] scfg, ncfg;
 
wire [VCN-1:0][3:0][VCN-1:0] mwcfg, mecfg, mlcfg; // the cfg before the AND gates
wire [VCN-1:0][1:0][VCN-1:0] mscfg, mncfg;
wire [VCN-1:0][3:0][VCN-1:0] wcfga, ecfga, lcfga; // cfg ack from req CB
wire [VCN-1:0][1:0][VCN-1:0] scfga, ncfga;
`ifndef ENABLE_MRMA
wire [1:0][VCN-1:0][VCN-1:0] i2sr, i2nr; // input to output requests
wire [3:0][VCN-1:0][VCN-1:0] i2wr, i2er, i2lr;
`else
wire [1:0][VCN-1:0] i2sr, i2nr; // input to output requests
wire [3:0][VCN-1:0] i2wr, i2er, i2lr;
`endif
wire [1:0][VCN-1:0] i2sa, i2na; // ack for i2(dir)r
wire [3:0][VCN-1:0] i2wa, i2ea, i2la;
 
// other wires for shuffle purposes
wire [VCN-1:0][3:0][VCN-1:0] svcram, nvcram, lvcram;
wire [VCN-1:0][1:0][VCN-1:0] wvcram, evcram;
wire [VCN-1:0][3:0][VCN-1:0] svcrami, nvcrami, lvcrami;
wire [VCN-1:0][1:0][VCN-1:0] wvcrami, evcrami;
wire [VCN-1:0][3:0] svcrai, nvcrai, lvcrai;
wire [VCN-1:0][1:0] wvcrai, evcrai;
wire [VCN-1:0][3:0] svcraii, nvcraii, lvcraii;
wire [VCN-1:0][1:0] wvcraii, evcraii;
`ifdef ENABLE_MRMA
wire [VCN:0] vcrst_n; // the buffered resets to avoid metastability
wire [VCN-1:0] svcrdy, svcrdya; // south vc ready status
wire [VCN-1:0] wvcrdy, wvcrdya; // west vc ready status
wire [VCN-1:0] nvcrdy, nvcrdya; // north vc ready status
wire [VCN-1:0] evcrdy, evcrdya; // east vc ready status
wire [VCN-1:0] lvcrdy, lvcrdya; // local vc ready status
`endif
 
genvar i, j;
generate
for(i=0; i<VCN; i++) begin:SF
assign svcra[i] = {svcrai[i][0]|svcrai[i][1]|svcrai[i][2]|svcrai[i][3]};
assign wvcra[i] = {wvcrai[i][0]|wvcrai[i][1]};
assign nvcra[i] = {nvcrai[i][0]|nvcrai[i][1]|nvcrai[i][2]|nvcrai[i][3]};
assign evcra[i] = {evcrai[i][0]|evcrai[i][1]};
assign lvcra[i] = {lvcrai[i][0]|lvcrai[i][1]|lvcrai[i][2]|lvcrai[i][3]};
or VCRENn0( mnvcr[i][0], nvcr[i][0], (|nvcram[i][0])&rstn);
or VCRENl0( mlvcr[i][0], lvcr[i][0], (|lvcram[i][0])&rstn);
or VCRENs0( msvcr[i][0], svcr[i][0], (|svcram[i][0])&rstn);
or VCRENn1( mnvcr[i][1], nvcr[i][1], (|nvcram[i][1])&rstn);
or VCRENe0( mevcr[i][0], evcr[i][0], (|evcram[i][0])&rstn);
or VCRENl1( mlvcr[i][1], lvcr[i][1], (|lvcram[i][1])&rstn);
or VCRENs1( msvcr[i][1], svcr[i][1], (|svcram[i][1])&rstn);
or VCRENl2( mlvcr[i][2], lvcr[i][2], (|lvcram[i][2])&rstn);
or VCRENs2( msvcr[i][2], svcr[i][2], (|svcram[i][2])&rstn);
or VCRENw0( mwvcr[i][0], wvcr[i][0], (|wvcram[i][0])&rstn);
or VCRENn2( mnvcr[i][2], nvcr[i][2], (|nvcram[i][2])&rstn);
or VCRENl3( mlvcr[i][3], lvcr[i][3], (|lvcram[i][3])&rstn);
or VCRENs3( msvcr[i][3], svcr[i][3], (|svcram[i][3])&rstn);
or VCRENw1( mwvcr[i][1], wvcr[i][1], (|wvcram[i][1])&rstn);
or VCRENn3( mnvcr[i][3], nvcr[i][3], (|nvcram[i][3])&rstn);
or VCRENe1( mevcr[i][1], evcr[i][1], (|evcram[i][1])&rstn);
 
and VCAOs0 (svcrai[i][0], (|svcrami[i][0]), svcraii[i][0]);
and VCAOs1 (svcrai[i][1], (|svcrami[i][1]), svcraii[i][1]);
and VCAOs2 (svcrai[i][2], (|svcrami[i][2]), svcraii[i][2]);
and VCAOs3 (svcrai[i][3], (|svcrami[i][3]), svcraii[i][3]);
and VCAOw0 (wvcrai[i][0], (|wvcrami[i][0]), wvcraii[i][0]);
and VCAOw1 (wvcrai[i][1], (|wvcrami[i][1]), wvcraii[i][1]);
and VCAOn0 (nvcrai[i][0], (|nvcrami[i][0]), nvcraii[i][0]);
and VCAOn1 (nvcrai[i][1], (|nvcrami[i][1]), nvcraii[i][1]);
and VCAOn2 (nvcrai[i][2], (|nvcrami[i][2]), nvcraii[i][2]);
and VCAOn3 (nvcrai[i][3], (|nvcrami[i][3]), nvcraii[i][3]);
and VCAOe0 (evcrai[i][0], (|evcrami[i][0]), evcraii[i][0]);
and VCAOe1 (evcrai[i][1], (|evcrami[i][1]), evcraii[i][1]);
and VCAOl0 (lvcrai[i][0], (|lvcrami[i][0]), lvcraii[i][0]);
and VCAOl1 (lvcrai[i][1], (|lvcrami[i][1]), lvcraii[i][1]);
and VCAOl2 (lvcrai[i][2], (|lvcrami[i][2]), lvcraii[i][2]);
and VCAOl3 (lvcrai[i][3], (|lvcrami[i][3]), lvcraii[i][3]);
or VCAIs0 (svcraii[i][0], (~svcr[i][0]), (|svcram[i][0]));
or VCAIs1 (svcraii[i][1], (~svcr[i][1]), (|svcram[i][1]));
or VCAIs2 (svcraii[i][2], (~svcr[i][2]), (|svcram[i][2]));
or VCAIs3 (svcraii[i][3], (~svcr[i][3]), (|svcram[i][3]));
or VCAIw0 (wvcraii[i][0], (~wvcr[i][0]), (|wvcram[i][0]));
or VCAIw1 (wvcraii[i][1], (~wvcr[i][1]), (|wvcram[i][1]));
or VCAIn0 (nvcraii[i][0], (~nvcr[i][0]), (|nvcram[i][0]));
or VCAIn1 (nvcraii[i][1], (~nvcr[i][1]), (|nvcram[i][1]));
or VCAIn2 (nvcraii[i][2], (~nvcr[i][2]), (|nvcram[i][2]));
or VCAIn3 (nvcraii[i][3], (~nvcr[i][3]), (|nvcram[i][3]));
or VCAIe0 (evcraii[i][0], (~evcr[i][0]), (|evcram[i][0]));
or VCAIe1 (evcraii[i][1], (~evcr[i][1]), (|evcram[i][1]));
or VCAIl0 (lvcraii[i][0], (~lvcr[i][0]), (|lvcram[i][0]));
or VCAIl1 (lvcraii[i][1], (~lvcr[i][1]), (|lvcram[i][1]));
or VCAIl2 (lvcraii[i][2], (~lvcr[i][2]), (|lvcram[i][2]));
or VCAIl3 (lvcraii[i][3], (~lvcr[i][3]), (|lvcram[i][3]));
`ifdef ENABLE_MRMA
assign i2sr[0][i] = mnvcr[i][0];
assign i2sr[1][i] = mlvcr[i][0];
assign i2wr[0][i] = msvcr[i][0];
assign i2wr[1][i] = mnvcr[i][1];
assign i2wr[2][i] = mevcr[i][0];
assign i2wr[3][i] = mlvcr[i][1];
assign i2nr[0][i] = msvcr[i][1];
assign i2nr[1][i] = mlvcr[i][2];
assign i2er[0][i] = msvcr[i][2];
assign i2er[1][i] = mwvcr[i][0];
assign i2er[2][i] = mnvcr[i][2];
assign i2er[3][i] = mlvcr[i][3];
assign i2lr[0][i] = msvcr[i][3];
assign i2lr[1][i] = mwvcr[i][1];
assign i2lr[2][i] = mnvcr[i][3];
assign i2lr[3][i] = mevcr[i][1];
`endif // `ifndef ENABLE_MRMA
 
for(j=0; j<VCN; j++) begin : CO
`ifndef ENABLE_MRMA
assign i2sr[0][i][j] = mnvcr[i][0];
assign i2sr[1][i][j] = mlvcr[i][0];
assign i2wr[0][i][j] = msvcr[i][0];
assign i2wr[1][i][j] = mnvcr[i][1];
assign i2wr[2][i][j] = mevcr[i][0];
assign i2wr[3][i][j] = mlvcr[i][1];
assign i2nr[0][i][j] = msvcr[i][1];
assign i2nr[1][i][j] = mlvcr[i][2];
assign i2er[0][i][j] = msvcr[i][2];
assign i2er[1][i][j] = mwvcr[i][0];
assign i2er[2][i][j] = mnvcr[i][2];
assign i2er[3][i][j] = mlvcr[i][3];
assign i2lr[0][i][j] = msvcr[i][3];
assign i2lr[1][i][j] = mwvcr[i][1];
assign i2lr[2][i][j] = mnvcr[i][3];
assign i2lr[3][i][j] = mevcr[i][1];
`endif // `ifndef ENABLE_MRMA
assign svcram[i][0][j] = wcfga[j][0][i];
assign svcram[i][1][j] = ncfga[j][0][i];
assign svcram[i][2][j] = ecfga[j][0][i];
assign svcram[i][3][j] = lcfga[j][0][i];
assign wvcram[i][0][j] = ecfga[j][1][i];
assign wvcram[i][1][j] = lcfga[j][1][i];
assign nvcram[i][0][j] = scfga[j][0][i];
assign nvcram[i][1][j] = wcfga[j][1][i];
assign nvcram[i][2][j] = ecfga[j][2][i];
assign nvcram[i][3][j] = lcfga[j][2][i];
assign evcram[i][0][j] = wcfga[j][2][i];
assign evcram[i][1][j] = lcfga[j][3][i];
assign lvcram[i][0][j] = scfga[j][1][i];
assign lvcram[i][1][j] = wcfga[j][3][i];
assign lvcram[i][2][j] = ncfga[j][1][i];
assign lvcram[i][3][j] = ecfga[j][3][i];
 
assign svcrami[i][0][j] = mwcfg[j][0][i];
assign svcrami[i][1][j] = mncfg[j][0][i];
assign svcrami[i][2][j] = mecfg[j][0][i];
assign svcrami[i][3][j] = mlcfg[j][0][i];
assign wvcrami[i][0][j] = mecfg[j][1][i];
assign wvcrami[i][1][j] = mlcfg[j][1][i];
assign nvcrami[i][0][j] = mscfg[j][0][i];
assign nvcrami[i][1][j] = mwcfg[j][1][i];
assign nvcrami[i][2][j] = mecfg[j][2][i];
assign nvcrami[i][3][j] = mlcfg[j][2][i];
assign evcrami[i][0][j] = mwcfg[j][2][i];
assign evcrami[i][1][j] = mlcfg[j][3][i];
assign lvcrami[i][0][j] = mscfg[j][1][i];
assign lvcrami[i][1][j] = mwcfg[j][3][i];
assign lvcrami[i][2][j] = mncfg[j][1][i];
assign lvcrami[i][3][j] = mecfg[j][3][i];
 
and CFGENw0 (wcfg[j][0][i], svcr[i][0], mwcfg[j][0][i]);
and CFGENn0 (ncfg[j][0][i], svcr[i][1], mncfg[j][0][i]);
and CFGENe0 (ecfg[j][0][i], svcr[i][2], mecfg[j][0][i]);
and CFGENl0 (lcfg[j][0][i], svcr[i][3], mlcfg[j][0][i]);
and CFGENe1 (ecfg[j][1][i], wvcr[i][0], mecfg[j][1][i]);
and CFGENl1 (lcfg[j][1][i], wvcr[i][1], mlcfg[j][1][i]);
and CFGENs0 (scfg[j][0][i], nvcr[i][0], mscfg[j][0][i]);
and CFGENw1 (wcfg[j][1][i], nvcr[i][1], mwcfg[j][1][i]);
and CFGENe2 (ecfg[j][2][i], nvcr[i][2], mecfg[j][2][i]);
and CFGENl2 (lcfg[j][2][i], nvcr[i][3], mlcfg[j][2][i]);
and CFGENw2 (wcfg[j][2][i], evcr[i][0], mwcfg[j][2][i]);
and CFGENl3 (lcfg[j][3][i], evcr[i][1], mlcfg[j][3][i]);
and CFGENs1 (scfg[j][1][i], lvcr[i][0], mscfg[j][1][i]);
and CFGENw3 (wcfg[j][3][i], lvcr[i][1], mwcfg[j][3][i]);
and CFGENn1 (ncfg[j][1][i], lvcr[i][2], mncfg[j][1][i]);
and CFGENe3 (ecfg[j][3][i], lvcr[i][3], mecfg[j][3][i]);
end // block: CO
end // block: SF
endgenerate
// the requests crossbar
rcb #(.VCN(VCN))
RSW (
.ro ( {losr, eosr, nosr, wosr, sosr} ),
.srt ( sswa ),
.wrt ( wswa ),
.nrt ( nswa ),
.ert ( eswa ),
.lrt ( lswa ),
.ri ( {lswr, eswr, nswr, wswr, sswr} ),
.go ( {losa, eosa, nosa, wosa, sosa} ),
.wctl ( wcfg ),
.ectl ( ecfg ),
.lctl ( lcfg ),
.sctl ( scfg ),
.nctl ( ncfg ),
.wctla ( wcfga ),
.ectla ( ecfga ),
.lctla ( lcfga ),
.sctla ( scfga ),
.nctla ( ncfga )
);
 
// the VC allocators
`ifndef ENABLE_MRMA
mnma #(.N(2*VCN), .M(VCN))
SVA (
.r ( i2sr ),
.cfg ( mscfg ),
.ra ( )
);
 
mnma #(.N(4*VCN), .M(VCN))
WVA (
.r ( i2wr ),
.cfg ( mwcfg ),
.ra ( )
);
mnma #(.N(2*VCN), .M(VCN))
NVA (
.r ( i2nr ),
.cfg ( mncfg ),
.ra ( )
);
 
mnma #(.N(4*VCN), .M(VCN))
EVA (
.r ( i2er ),
.cfg ( mecfg ),
.ra ( )
);
 
mnma #(.N(4*VCN), .M(VCN))
LVA (
.r ( i2lr ),
.cfg ( mlcfg ),
.ra ( )
);
`else // !`ifndef ENABLE_MRMA
mrma #(.N(2*VCN), .M(VCN))
SVA (
.c ( i2sr ),
.cfg ( mscfg ),
.ca ( ),
.r ( svcrdy ),
.ra ( svcrdya ),
.rst_n ( rstn )
);
 
mrma #(.N(4*VCN), .M(VCN))
WVA (
.c ( i2wr ),
.cfg ( mwcfg ),
.ca ( ),
.r ( wvcrdy ),
.ra ( wvcrdya ),
.rst_n ( rstn )
);
mrma #(.N(2*VCN), .M(VCN))
NVA (
.c ( i2nr ),
.cfg ( mncfg ),
.ca ( ),
.r ( nvcrdy ),
.ra ( nvcrdya ),
.rst_n ( rstn )
);
 
mrma #(.N(4*VCN), .M(VCN))
EVA (
.c ( i2er ),
.cfg ( mecfg ),
.ca ( ),
.r ( evcrdy ),
.ra ( evcrdya ),
.rst_n ( rstn )
);
 
mrma #(.N(4*VCN), .M(VCN))
LVA (
.c ( i2lr ),
.cfg ( mlcfg ),
.ca ( ),
.r ( lvcrdy ),
.ra ( lvcrdya ),
.rst_n ( rstn )
);
 
generate
for(i=0; i<VCN; i++) begin: OPC
delay DLY ( .q(vcrst_n[i+1]), .a(vcrst_n[i])); // dont touch
assign svcrdy[i] = (~svcrdya[i])&vcrst_n[i+1];
assign wvcrdy[i] = (~wvcrdya[i])&vcrst_n[i+1];
assign nvcrdy[i] = (~nvcrdya[i])&vcrst_n[i+1];
assign evcrdy[i] = (~evcrdya[i])&vcrst_n[i+1];
assign lvcrdy[i] = (~lvcrdya[i])&vcrst_n[i+1];
end
endgenerate
 
assign vcrst_n[0] = rst_n;
 
`endif // !`ifndef ENABLE_MRMA
endmodule // vcalloc
 
/* logic of the control logic generated from petrify
 
// Verilog model for vca_ctl
// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
// CPU time for synthesis (host <unknown>): 0.04 seconds
// Estimated area = 72.00
 
// The circuit is self-resetting and does not need reset pin.
 
module vca_ctl_net (
vcri,
cfg,
vcrai,
vcro,
cfgen,
vcrao
);
 
input vcri;
input cfg;
input vcrai;
 
output vcro;
output cfgen;
output vcrao;
 
 
// Functions not mapped into library gates:
// ----------------------------------------
 
// Equation: vcro = vcri + vcrai
or _U0 (vcro, vcrai, vcri);
 
// Equation: cfgen = vcri
buf _U1 (cfgen, vcri);
 
// Equation: vcrao = cfg (vcri' + vcrai)
not _U1 (_X1, vcri);
and _U2 (_X0, vcrai, cfg);
and _U3 (_X2, cfg, _X1);
or _U4 (vcrao, _X0, _X2);
 
 
// signal values at the initial state:
// !vcri !cfg !vcrai !vcro !cfgen !vcrao
endmodule
*/
init/vc/src/vca.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: init/vc/src/rtu.v =================================================================== --- init/vc/src/rtu.v (nonexistent) +++ init/vc/src/rtu.v (revision 39) @@ -0,0 +1,185 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + The routing calculation unit in every input buffer. + p0 -> L -> p1 -> RTC -> p2 -> L -> p3 -> DEMUX -> p[0] -> L -> p[1] -> L -> p[2] -> L -> p[3] -> L -> p[4] + + History: + 02/04/2010 Initial version. + 02/06/2011 Clean up for opensource. + +*/ + +module rtu (/*AUTOARG*/ + // Outputs + dia, dort, + // Inputs + rstn, di0, di1, di2, di3, dit, divc, addrx, addry, doa + ); + parameter VCN = 2; + parameter DIR = 0; + parameter SN = 4; + parameter PD = 2; + + input rstn; + input [3:0] di0, di1, di2, di3; + input [2:0] dit; + input [VCN-1:0] divc; + output dia; + + input [7:0] addrx, addry; + + output [VCN-1:0][SN-1:0] dort; + input [VCN-1:0] doa; + + //------------------------------------------ + wire p0an, p0ap, p0den, p0ad, p0avc; + wire [3:0] p1d0, p1d1, p1d2, p1d3; + wire [VCN-1:0] p1vc; + wire p1a, p1ad, p1avc, p1an; + wire [SN-1:0] p2d; + wire [VCN-1:0] p2vc; + wire p2a, p2ad, p2avc, p2an; + wire [SN-1:0] p3d; + wire [VCN-1:0] p3vc; + wire p3a, p3an; + wire [PD*2:0][VCN-1:0][SN-1:0] pd; + wire [PD*2:0][VCN-1:0] pda, pdan; + + wire [2:0] x_cmp [1:0]; + wire [2:0] y_cmp [1:0]; + wire [5:0] dec; + wire ds, dw, dn, de, dl; + + + genvar gvc, gbd, i; + + //------------------------------------------ + // p0 -> L -> p1 + + c2 CP0DE ( .a0(dit[0]), .a1(p1an), .q(p0den)); + c2 CP0A ( .a0(p0ad), .a1(p0avc), .q(p0ap)); + assign p0an = |dit[2:1]; + assign dia = p0an | p0ap; + + pipe4 #(.DW(8)) + L0D ( + .dia ( p0ad ), + .do0 ( p1d0 ), + .do1 ( p1d1 ), + .do2 ( p1d2 ), + .do3 ( p1d3 ), + .di0 ( di0 ), + .di1 ( di1 ), + .di2 ( di2 ), + .di3 ( di3 ), + .doa ( p0den ) + ); + + pipen #(.DW(VCN)) + L0V ( + .d_in ( divc ), + .d_in_a ( p0avc ), + .d_out ( p1vc ), + .d_out_a ( p0den ) + ); + + // p1 -> RTC -> p2 + comp4 X0 ( .a({p1d3[0], p1d2[0], p1d1[0], p1d0[0]}), .b(addrx[3:0]), .q(x_cmp[0])); + comp4 X1 ( .a({p1d3[1], p1d2[1], p1d1[1], p1d0[1]}), .b(addrx[7:4]), .q(x_cmp[1])); + comp4 Y0 ( .a({p1d3[2], p1d2[2], p1d1[2], p1d0[2]}), .b(addry[3:0]), .q(y_cmp[0])); + comp4 Y1 ( .a({p1d3[3], p1d2[3], p1d1[3], p1d0[3]}), .b(addry[7:4]), .q(y_cmp[1])); + + assign dec[0] = x_cmp[1][0] | (x_cmp[1][2]&x_cmp[0][0]); // frame x > addr x + assign dec[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x + assign dec[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x + assign dec[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y + assign dec[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y + assign dec[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y + + assign ds = dec[0]; + assign dw = dec[2]&dec[4]; + assign dn = dec[1]; + assign de = dec[2]&dec[3]; + assign dl = dec[2]&dec[5]; + + assign p2d = + DIR == 0 ? {dl, de, dn, dw} : // south port + DIR == 1 ? {dl, de} : // west port + DIR == 2 ? {dl, de, dw, ds} : // north port + DIR == 3 ? {dl, dw} : // east port + {de, dn, dw, ds} ; // local port + + assign p2vc = p1vc; + assign p1an = p2an; + + // p2 -> L -> p3 + + c2 CP2A ( .a0(p2ad), .a1(p2avc), .q(p2a)); + assign p2an = (~p2a) & rstn; + + pipen #(.DW(SN)) + L2R ( + .d_in ( p2d ), + .d_in_a ( p2ad ), + .d_out ( p3d ), + .d_out_a ( p3an ) + ); + + pipen #(.DW(VCN)) + L2V ( + .d_in ( p2vc ), + .d_in_a ( p2avc ), + .d_out ( p3vc ), + .d_out_a ( p3an ) + ); + + // p3 -> DEMUX -> pd[0] + ddmux #(.DW(SN), .VCN(VCN)) + RTDM ( + .d_in_a ( p3a ), + .d_out ( pd[0] ), + .d_in ( p3d ), + .d_sel ( p3vc ), + .d_out_a ( pda[0]) + ); + + assign p3an = (~p3a) & rstn; + + // pd pipeline + generate + for(gbd=0; gbd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.