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Rev 41 → Rev 42

/init/sdm/syn/script/source.tcl
12,6 → 12,7
#
# History:
# 26/05/2011 Initial version. <wsong83@gmail.com>
# 02/06/2011 Use separated comp4 file. <wsong83@gmail.com>
 
# the common verilog source files between VC and SDM
analyze -format verilog ../../common/src/cell_lib.v
25,6 → 26,7
analyze -format sverilog ../../common/src/pipe4.v
analyze -format sverilog ../../common/src/rcb.v
analyze -format verilog ../../common/src/tree_arb.v
analyze -format verilog ../../common/src/comp4.v
 
# the private code of wormhole/SDM routers
analyze -format sverilog ../src/clos_sch.v
/init/vc/src/router.v
361,39 → 361,39
 
// VC allocator
vcalloc #(.VCN(VCN))
VCA (
.svcra ( svcra ),
.wvcra ( wvcra ),
.nvcra ( nvcra ),
.evcra ( evcra ),
.lvcra ( lvcra ),
.sswa ( siswrt ),
.wswa ( wiswrt ),
.nswa ( niswrt ),
.eswa ( eiswrt ),
.lswa ( liswrt ),
.sosr ( soswr ),
.wosr ( woswr ),
.nosr ( noswr ),
.eosr ( eoswr ),
.losr ( loswr ),
.svcr ( svcr ),
.nvcr ( nvcr ),
.lvcr ( lvcr ),
.wvcr ( wvcr ),
.evcr ( evcr ),
.sswr ( siswr ),
.wswr ( wiswr ),
.nswr ( niswr ),
.eswr ( eiswr ),
.lswr ( liswr ),
.sosa ( soswa ),
.wosa ( woswa ),
.nosa ( noswa ),
.eosa ( eoswa ),
.losa ( loswa ),
.rstn ( rstn )
);
ALLOC (
.svcra ( svcra ),
.wvcra ( wvcra ),
.nvcra ( nvcra ),
.evcra ( evcra ),
.lvcra ( lvcra ),
.sswa ( siswrt ),
.wswa ( wiswrt ),
.nswa ( niswrt ),
.eswa ( eiswrt ),
.lswa ( liswrt ),
.sosr ( soswr ),
.wosr ( woswr ),
.nosr ( noswr ),
.eosr ( eoswr ),
.losr ( loswr ),
.svcr ( svcr ),
.nvcr ( nvcr ),
.lvcr ( lvcr ),
.wvcr ( wvcr ),
.evcr ( evcr ),
.sswr ( siswr ),
.wswr ( wiswr ),
.nswr ( niswr ),
.eswr ( eiswr ),
.lswr ( liswr ),
.sosa ( soswa ),
.wosa ( woswa ),
.nosa ( noswa ),
.eosa ( eoswa ),
.losa ( loswa ),
.rstn ( rstn )
);
 
// crossbar
dcb_vc #(.DW(DW), .FT(FT), .VCN(VCN))
/init/vc/src/inpbuf.v
132,16 → 132,16
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
DP (
.dia ( vcdad[gbd][gvc][gsub] ),
.do0 ( vcd0[gbd+1][gvc][gsub] ),
.do1 ( vcd1[gbd+1][gvc][gsub] ),
.do2 ( vcd2[gbd+1][gvc][gsub] ),
.do3 ( vcd3[gbd+1][gvc][gsub] ),
.di0 ( vcd0[gbd][gvc][gsub] ),
.di1 ( vcd1[gbd][gvc][gsub] ),
.di2 ( vcd2[gbd][gvc][gsub] ),
.di3 ( vcd3[gbd][gvc][gsub] ),
.doa ( vcdadn[gbd+1][gvc][gsub] )
.ia ( vcdad[gbd][gvc][gsub] ),
.o0 ( vcd0[gbd+1][gvc][gsub] ),
.o1 ( vcd1[gbd+1][gvc][gsub] ),
.o2 ( vcd2[gbd+1][gvc][gsub] ),
.o3 ( vcd3[gbd+1][gvc][gsub] ),
.i0 ( vcd0[gbd][gvc][gsub] ),
.i1 ( vcd1[gbd][gvc][gsub] ),
.i2 ( vcd2[gbd][gvc][gsub] ),
.i3 ( vcd3[gbd][gvc][gsub] ),
.oa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
end // block: SC
177,16 → 177,16
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
DP (
.dia ( vcdad[gbd][gvc][gsub] ),
.do0 ( vcd0[gbd+1][gvc][gsub] ),
.do1 ( vcd1[gbd+1][gvc][gsub] ),
.do2 ( vcd2[gbd+1][gvc][gsub] ),
.do3 ( vcd3[gbd+1][gvc][gsub] ),
.di0 ( vcd0[gbd][gvc][gsub] ),
.di1 ( vcd1[gbd][gvc][gsub] ),
.di2 ( vcd2[gbd][gvc][gsub] ),
.di3 ( vcd3[gbd][gvc][gsub] ),
.doa ( vcdadn[gbd+1][gvc][gsub] )
.ia ( vcdad[gbd][gvc][gsub] ),
.o0 ( vcd0[gbd+1][gvc][gsub] ),
.o1 ( vcd1[gbd+1][gvc][gsub] ),
.o2 ( vcd2[gbd+1][gvc][gsub] ),
.o3 ( vcd3[gbd+1][gvc][gsub] ),
.i0 ( vcd0[gbd][gvc][gsub] ),
.i1 ( vcd1[gbd][gvc][gsub] ),
.i2 ( vcd2[gbd][gvc][gsub] ),
.i3 ( vcd3[gbd][gvc][gsub] ),
.oa ( vcdadn[gbd+1][gvc][gsub] )
);
assign vcdadn[gbd+1][gvc][gsub] = (~vcdad[gbd+1][gvc][gsub])&rstn;
end // block: SC
/init/vc/src/outpbuf.v
86,16 → 86,16
for(gsub=0; gsub<SCN; gsub++) begin:SC
pipe4 #(.DW(2))
L0D (
.dia ( diad[gsub] ),
.do0 ( do0[gsub] ),
.do1 ( do1[gsub] ),
.do2 ( do2[gsub] ),
.do3 ( do3[gsub] ),
.di0 ( di0[gsub] ),
.di1 ( di1[gsub] ),
.di2 ( di2[gsub] ),
.di3 ( di3[gsub] ),
.doa ( doan[gsub] )
.ia ( diad[gsub] ),
.o0 ( do0[gsub] ),
.o1 ( do1[gsub] ),
.o2 ( do2[gsub] ),
.o3 ( do3[gsub] ),
.i0 ( di0[gsub] ),
.i1 ( di1[gsub] ),
.i2 ( di2[gsub] ),
.i3 ( di3[gsub] ),
.oa ( doan[gsub] )
);
assign doan[gsub] = (~doa)&rstn;
end // block: SC
/init/vc/src/vca.v
243,7 → 243,7
endgenerate
// the requests crossbar
rcb #(.VCN(VCN))
rcb_vc #(.VCN(VCN))
RSW (
.ro ( {losr, eosr, nosr, wosr, sosr} ),
.srt ( sswa ),
/init/vc/src/rtu.v
72,16 → 72,16
pipe4 #(.DW(8))
L0D (
.dia ( p0ad ),
.do0 ( p1d0 ),
.do1 ( p1d1 ),
.do2 ( p1d2 ),
.do3 ( p1d3 ),
.di0 ( di0 ),
.di1 ( di1 ),
.di2 ( di2 ),
.di3 ( di3 ),
.doa ( p0den )
.ia ( p0ad ),
.o0 ( p1d0 ),
.o1 ( p1d1 ),
.o2 ( p1d2 ),
.o3 ( p1d3 ),
.i0 ( di0 ),
.i1 ( di1 ),
.i2 ( di2 ),
.i3 ( di3 ),
.oa ( p0den )
);
 
pipen #(.DW(VCN))
/init/vc/syn/script/source.tcl
22,6 → 22,7
analyze -format sverilog ../../common/src/pipe4.v
analyze -format sverilog ../../common/src/pipen.v
analyze -format verilog ../../common/src/tree_arb.v
analyze -format verilog ../../common/src/comp4.v
 
# the private code of wormhole/SDM routers
analyze -format sverilog ../src/cpipe.v
/init/vc/syn/script/constraint.tcl
25,6 → 25,18
 
######### break the timing loops in the design ##############
 
# the cross points in the VCA
foreach_in_collection celln [get_references -hierarchical RCBB_*] {
set_disable_timing [get_object_name $celln]/I1 -from B -to Z
set_disable_timing [get_object_name $celln]/I0/U1 -from B -to Z
set_disable_timing [get_object_name $celln]/I0/U3 -from A -to Z
set_disable_timing [get_object_name $celln]/I3/U1 -from A -to Z
set_disable_timing [get_object_name $celln]/I3/U2 -from A -to Z
 
}
 
set_disable_timing [get_cells ALLOC/*VCAO*] -from A -to Z
 
# set some timing path ending points
set DPD []
set DPA []

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