OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches
    from Rev 43 to Rev 44
    ↔ Reverse comparison
  •

Rev 43 → Rev 44

/init/sdm/tb/ni.h
15,7 → 15,7
20/08/2008 Initial version. <wsong83@gmail.com>
30/09/2010 Use template style packet definition. <wsong83@gmail.com>
16/10/2010 Support SDM. <wsong83@gmail.com>
30/05/2011 CLean up for opensource. <wsong83@gmail.com>
30/05/2011 Clean up for opensource. <wsong83@gmail.com>
 
*/
 
/init/vc/define.h
0,0 → 1,51
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The define file for the SystemC test modules
History:
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
#ifndef NOC_DEF_H_
#define NOC_DEF_H_
 
#define SC_INCLUDE_DYNAMIC_PROCESSES
#include "sim_ana.h"
#include "pdu_def.h"
 
// channel bandwidth
const unsigned int ChBW = 1; // the data width of a single virtual circuit in unit of bytes
const unsigned int SubChN = 1; // the number of virtual circuits or VCs per direction
const unsigned int FSIZE_MAX = 512; // the longest frame has 512 bytes of data
 
const unsigned int DIMX = 4; // the X size of the mesh network
const unsigned int DIMY = 4; // the Y size of the mesh network
const unsigned int FLEN = 64; // the payload size of a frame in unit of bytes
 
const unsigned int BufDepth = 2; // the depth of the input buffer (only useful in VC routers to determine the inital tokens in output ports)
 
const double FFreq = 0.1; // Node injection rate, in unit of MFlit/second, 0 means the maximal inject rate
 
const double Record_Period = 1e3 * 1e3; // the interval of recording the average performance to log files, in unit of ps
const double Warm_UP = 0e4 * 1e3; // the warm up time of performance analysis, in unit of ps
const double SIM_TIME = 1e3 * 1e3; // the overall simulation time of the netowrk, in unit of ns
 
extern sim_ana * ANA; // declaration of the global simulation analysis module
 
typedef pdu_flit<ChBW> FLIT; // define the template of flit
typedef pdu_frame<ChBW> FRAME; // define the template of frame
 
// Channel Slicing will alter the port format
// #define ENABLE_CHANNEL_CLISING
 
#endif
/init/vc/tb/netnode.v
0,0 → 1,68
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The SystemC module of network node including the processing element and the network interface.
Currently the transmission FIFO is 500 frame deep.
History:
27/02/2011 Initial version. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
`include "define.v"
 
module NetNode (
doa, doc, do0, do1, do2, do3, doft, dovc, doca,
dia, dic, di0, di1, di2, di3, dift, divc, dica,
rst_n)
//
// The foreign attribute string value must be a SystemC value.
//
(* integer foreign = "SystemC";
*);
//
// Verilog port names must match port names exactly as they appear in the
// sc_module class in SystemC; they must also match in order, mode, and type.
//
parameter DW = 32;
parameter VCN = 1;
parameter FT = 3;
parameter x = 2;
parameter y = 2;
parameter SCN = DW/2;
output doa ;
output [VCN-1:0] doc ;
input [SCN-1:0] do0 ;
input [SCN-1:0] do1 ;
input [SCN-1:0] do2 ;
input [SCN-1:0] do3 ;
input [FT-1:0] doft;
input [VCN-1:0] dovc;
input [VCN-1:0] doca;
input dia;
input [VCN-1:0] dic;
output [SCN-1:0] di0;
output [SCN-1:0] di1;
output [SCN-1:0] di2;
output [SCN-1:0] di3;
output [FT-1:0] dift;
output [VCN-1:0] divc;
output [VCN-1:0] dica;
 
input rst_n;
 
endmodule // NetNode
 
/init/vc/tb/netnode.h
0,0 → 1,148
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The SystemC module of network node including the processing element and the network interface.
Currently the transmission FIFO is 500 frame deep.
History:
26/02/2011 Initial version. <wsong83@gmail.com>
04/03/2011 Support VC router. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
#ifndef NETNODE_H_
#define NETNODE_H_
 
#include "define.h"
#include <systemc.h>
#include "ni.h"
#include "procelem.h"
#include "rtdriver.h"
 
class NetNode : public sc_module {
public:
RTDriver * LIOD; /* driving and convert I/O to/from router local port */
Network_Adapter * NI; /* network interface */
ProcElem * PE; /* processor element */
 
// signals for router
sc_out< sc_logic > doa ;
sc_out< sc_lv<SubChN > > doc ;
sc_in< sc_lv<ChBW*4 > > do0 ;
sc_in< sc_lv<ChBW*4 > > do1 ;
sc_in< sc_lv<ChBW*4 > > do2 ;
sc_in< sc_lv<ChBW*4 > > do3 ;
sc_in< sc_lv<3> > doft;
sc_in< sc_lv<SubChN > > dovc;
sc_in< sc_lv<SubChN > > doca;
sc_in< sc_logic > dia;
sc_in< sc_lv<SubChN > > dic;
sc_out< sc_lv<ChBW*4 > > di0;
sc_out< sc_lv<ChBW*4 > > di1;
sc_out< sc_lv<ChBW*4 > > di2;
sc_out< sc_lv<ChBW*4 > > di3;
sc_out< sc_lv<3> > dift;
sc_out< sc_lv<SubChN > > divc;
sc_out< sc_lv<SubChN > > dica;
 
sc_in<sc_logic > rst_n; /* global active-low reset */
 
// signals between IOD and NI
sc_fifo<pdu_flit<ChBW> > * NI2P ; /* flit fifo, from NI to IO driver */
sc_fifo<pdu_flit<ChBW> > * P2NI ; /* flit fifo, from IO driver to NI */
sc_signal<bool> CP [SubChN]; /* credit input */
sc_signal<bool> CPa [SubChN]; /* credit ack */
 
// signals between NI and FG/FS
sc_fifo<pdu_frame<ChBW> > * FIQ; /* the frame fifo, from PE to NI */
sc_fifo<pdu_frame<ChBW> > * FOQ; /* the frame fifo, from NI to PE */
sc_signal<bool> brst_n; /* the reset in the SystemC modules */
 
int x, y; /* private local address */
 
SC_CTOR(NetNode)
: doa("doa"), doc("doc"),
do0("do0"), do1("do1"), do2("do2"), do3("do3"),
doft("doft"), dovc("dovc"), doca("doca"),
dia("dia"), dic("dic"),
di0("di0"), di1("di1"), di2("di2"), di3("di3"),
dift("dift"), divc("divc"), dica("dica"),
rst_n("rst_n")
{
// dynamically get the parameters from Verilog test bench
ncsc_get_param("x", x);
ncsc_get_param("y", y);
 
// initialization
LIOD = new RTDriver("LIOD");
NI = new Network_Adapter("NI", x, y);
PE = new ProcElem("PE", x, y);
NI2P = new sc_fifo<pdu_flit<ChBW> >(1);
P2NI = new sc_fifo<pdu_flit<ChBW> >(1);
FIQ = new sc_fifo<pdu_frame<ChBW> >(500);/* currently the fifo from PE is 500 frame deep */
FOQ = new sc_fifo<pdu_frame<ChBW> >(1);
 
// connections
LIOD->NI2P(*NI2P);
LIOD->P2NI(*P2NI);
LIOD->rtid[0](di0);
LIOD->rtod[0](do0);
LIOD->rtid[1](di1);
LIOD->rtod[1](do1);
LIOD->rtid[2](di2);
LIOD->rtod[2](do2);
LIOD->rtid[3](di3);
LIOD->rtod[3](do3);
LIOD->rtift(dift);
LIOD->rtivc(divc);
LIOD->rtia(dia);
LIOD->rtic(dic);
LIOD->rtica(dica);
LIOD->rtoft(doft);
LIOD->rtovc(dovc);
LIOD->rtoa(doa);
LIOD->rtoc(doc);
LIOD->rtoca(doca);
for(unsigned int j=0; j<SubChN; j++) {
LIOD->CP[j](CP[j]);
LIOD->CPa[j](CPa[j]);
}
 
NI->frame_in(*FIQ);
NI->frame_out(*FOQ);
NI->IP(*P2NI);
NI->OP(*NI2P);
for(unsigned int j=0; j<SubChN; j++) {
NI->CP[j](CP[j]);
NI->CPa[j](CPa[j]);
}
PE->rst_n(brst_n);
PE->Fout(*FIQ);
PE->Fin(*FOQ);
 
brst_n.write(false);
 
SC_METHOD(rst_proc);
sensitive << rst_n;
}
 
void rst_proc() {
bool mrst_n;
mrst_n = rst_n.read().is_01() ? rst_n.read().to_bool() : false;
brst_n.write(mrst_n);
}
};
 
 
#endif
/init/vc/tb/noc_top.v
0,0 → 1,160
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The mesh network for simulation.
History:
03/03/2011 Initial version. <wsong83@gmail.com>
04/03/2011 Support VC. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module noc_top(/*AUTOARG*/
// Inputs
rst_n
);
input rst_n;
 
parameter DW = 32;
parameter VCN = 1;
parameter FT = 3;
parameter DIMX = 8;
parameter DIMY = 8;
parameter SCN = DW/2;
 
wire [DIMX-1:0][DIMY-1:0][3:0][SCN-1:0] di0, di1, di2, di3;
wire [DIMX-1:0][DIMY-1:0][3:0][SCN-1:0] do0, do1, do2, do3;
wire [DIMX-1:0][DIMY-1:0][3:0] dia, doa;
wire [DIMX-1:0][DIMY-1:0][3:0][FT-1:0] dift, doft;
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] divc, dovc;
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] dic, doc;
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] dica, doca;
 
genvar x, y;
 
generate for(x=0; x<DIMX; x++) begin: DX
for(y=0; y<DIMY; y++) begin: DY
node_top #(.DW(DW), .VCN(VCN), .FT(FT), .x(x), .y(y))
NN (
.si0 (di0[x][y][0]), .si1 (di1[x][y][0]), .si2 (di2[x][y][0]), .si3 (di3[x][y][0]), .sia (dia[x][y][0]), .sift(dift[x][y][0]), .sivc(divc[x][y][0]), .sic(dic[x][y][0]), .sica(dica[x][y][0]),
.wi0 (di0[x][y][1]), .wi1 (di1[x][y][1]), .wi2 (di2[x][y][1]), .wi3 (di3[x][y][1]), .wia (dia[x][y][1]), .wift(dift[x][y][1]), .wivc(divc[x][y][1]), .wic(dic[x][y][1]), .wica(dica[x][y][1]),
.ni0 (di0[x][y][2]), .ni1 (di1[x][y][2]), .ni2 (di2[x][y][2]), .ni3 (di3[x][y][2]), .nia (dia[x][y][2]), .nift(dift[x][y][2]), .nivc(divc[x][y][2]), .nic(dic[x][y][2]), .nica(dica[x][y][2]),
.ei0 (di0[x][y][3]), .ei1 (di1[x][y][3]), .ei2 (di2[x][y][3]), .ei3 (di3[x][y][3]), .eia (dia[x][y][3]), .eift(dift[x][y][3]), .eivc(divc[x][y][3]), .eic(dic[x][y][3]), .eica(dica[x][y][3]),
.so0 (do0[x][y][0]), .so1 (do1[x][y][0]), .so2 (do2[x][y][0]), .so3 (do3[x][y][0]), .soa (doa[x][y][0]), .soft(doft[x][y][0]), .sovc(dovc[x][y][0]), .soc(doc[x][y][0]), .soca(doca[x][y][0]),
.wo0 (do0[x][y][1]), .wo1 (do1[x][y][1]), .wo2 (do2[x][y][1]), .wo3 (do3[x][y][1]), .woa (doa[x][y][1]), .woft(doft[x][y][1]), .wovc(dovc[x][y][1]), .woc(doc[x][y][1]), .woca(doca[x][y][1]),
.no0 (do0[x][y][2]), .no1 (do1[x][y][2]), .no2 (do2[x][y][2]), .no3 (do3[x][y][2]), .noa (doa[x][y][2]), .noft(doft[x][y][2]), .novc(dovc[x][y][2]), .noc(doc[x][y][2]), .noca(doca[x][y][2]),
.eo0 (do0[x][y][3]), .eo1 (do1[x][y][3]), .eo2 (do2[x][y][3]), .eo3 (do3[x][y][3]), .eoa (doa[x][y][3]), .eoft(doft[x][y][3]), .eovc(dovc[x][y][3]), .eoc(doc[x][y][3]), .eoca(doca[x][y][3]),
.rst_n(rst_n)
);
// north link
if(x==0) begin
assign di0[x][y][2] = do0[x][y][2];
assign di1[x][y][2] = do1[x][y][2];
assign di2[x][y][2] = do2[x][y][2];
assign di3[x][y][2] = do3[x][y][2];
assign doa[x][y][2] = dia[x][y][2];
assign dift[x][y][2] = doft[x][y][2];
assign divc[x][y][2] = dovc[x][y][2];
assign doc[x][y][2] = dic[x][y][2];
assign dica[x][y][2] = doca[x][y][2];
end else begin
assign di0[x][y][2] = do0[x-1][y][0];
assign di1[x][y][2] = do1[x-1][y][0];
assign di2[x][y][2] = do2[x-1][y][0];
assign di3[x][y][2] = do3[x-1][y][0];
assign doa[x-1][y][0] = dia[x][y][2];
assign dift[x][y][2] = doft[x-1][y][0];
assign divc[x][y][2] = dovc[x-1][y][0];
assign doc[x-1][y][0] = dic[x][y][2];
assign dica[x][y][2] = doca[x-1][y][0];
end
 
// south link
if(x==DIMX-1) begin
assign di0[x][y][0] = do0[x][y][0];
assign di1[x][y][0] = do1[x][y][0];
assign di2[x][y][0] = do2[x][y][0];
assign di3[x][y][0] = do3[x][y][0];
assign doa[x][y][0] = dia[x][y][0];
assign dift[x][y][0] = doft[x][y][0];
assign divc[x][y][0] = dovc[x][y][0];
assign doc[x][y][0] = dic[x][y][0];
assign dica[x][y][0] = doca[x][y][0];
end else begin
assign di0[x][y][0] = do0[x+1][y][2];
assign di1[x][y][0] = do1[x+1][y][2];
assign di2[x][y][0] = do2[x+1][y][2];
assign di3[x][y][0] = do3[x+1][y][2];
assign doa[x+1][y][2] = dia[x][y][0];
assign dift[x][y][0] = doft[x+1][y][2];
assign divc[x][y][0] = dovc[x+1][y][2];
assign doc[x+1][y][2] = dic[x][y][0];
assign dica[x][y][0] = doca[x+1][y][2];
end
 
// west link
if(y==0) begin
assign di0[x][y][1] = do0[x][y][1];
assign di1[x][y][1] = do1[x][y][1];
assign di2[x][y][1] = do2[x][y][1];
assign di3[x][y][1] = do3[x][y][1];
assign doa[x][y][1] = dia[x][y][1];
assign dift[x][y][1] = doft[x][y][1];
assign divc[x][y][1] = dovc[x][y][1];
assign doc[x][y][1] = dic[x][y][1];
assign dica[x][y][1] = doca[x][y][1];
end else begin
assign di0[x][y][1] = do0[x][y-1][3];
assign di1[x][y][1] = do1[x][y-1][3];
assign di2[x][y][1] = do2[x][y-1][3];
assign di3[x][y][1] = do3[x][y-1][3];
assign doa[x][y-1][3] = dia[x][y][1];
assign dift[x][y][1] = doft[x][y-1][3];
assign divc[x][y][1] = dovc[x][y-1][3];
assign doc[x][y-1][3] = dic[x][y][1];
assign dica[x][y][1] = doca[x][y-1][3];
end // else: !if(y==0)
 
// east link
if(y==DIMY-1) begin
assign di0[x][y][3] = do0[x][y][3];
assign di1[x][y][3] = do1[x][y][3];
assign di2[x][y][3] = do2[x][y][3];
assign di3[x][y][3] = do3[x][y][3];
assign doa[x][y][3] = dia[x][y][3];
assign dift[x][y][3] = doft[x][y][3];
assign divc[x][y][3] = dovc[x][y][3];
assign doc[x][y][3] = dic[x][y][3];
assign dica[x][y][3] = doca[x][y][3];
end else begin
assign di0[x][y][3] = do0[x][y+1][1];
assign di1[x][y][3] = do1[x][y+1][1];
assign di2[x][y][3] = do2[x][y+1][1];
assign di3[x][y][3] = do3[x][y+1][1];
assign doa[x][y+1][1] = dia[x][y][3];
assign dift[x][y][3] = doft[x][y+1][1];
assign divc[x][y][3] = dovc[x][y+1][1];
assign doc[x][y+1][1] = dic[x][y][3];
assign dica[x][y][3] = doca[x][y+1][1];
end // else: !if(y==DIMY-1)
 
end // block: DY
end // block: DX
endgenerate
endmodule // noc_top
/init/vc/tb/ni.cpp
0,0 → 1,147
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
A SystemC network adapter/interface for NoC simulation.
History:
23/12/2008 Initial version. <wsong83@gmail.com>
30/09/2010 Use template style packet definition. <wsong83@gmail.com>
16/10/2010 Support SDM. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
 
*/
 
#include "ni.h"
 
Network_Adapter::Network_Adapter(
sc_module_name name // module name
,unsigned int x // location x
,unsigned int y // location y
):
sc_module(name),
frame_in("FrmIn"),
frame_out("FrmOut"),
IP("IP"),
OP("OP"),
loc_x(x),
loc_y(y),
oflit(1)
{
sc_spawn_options opt;
 
for(unsigned int i=0; i<SubChN; i++) {
token[i] = BufDepth/2;
}
 
for(unsigned int i=0; i<SubChN; i++) {
sc_spawn(sc_bind(&Network_Adapter::ibuffer_thread, this, i), NULL, &opt);
sc_spawn(sc_bind(&Network_Adapter::obuffer_thread, this, i), NULL, &opt);
sc_spawn(sc_bind(&Network_Adapter::credit_update, this, i), NULL, &opt);
}
SC_THREAD(oport);
SC_THREAD(iport);
 
}
 
Network_Adapter::~Network_Adapter()
{
}
 
// read in the incoming frame
void Network_Adapter::ibuffer_thread(unsigned int ii){
FRAME mframe;
FLIT mflit;
 
while(1){
mframe.clear();
while(1) {
mflit = iflit[ii].read();
mframe << mflit;
if(mflit.ftype == F_TL) break;
}
 
frame_out->write(mframe);
}
}
 
// send out a frame
void Network_Adapter::obuffer_thread(unsigned int ii){
 
FRAME mframe;
FLIT mflit;
 
while(1){
mframe = frame_in->read();
while(1) {
mframe >> mflit;
mflit.vcn = ii;
 
//fetch a token
if(token[ii] == 0)
wait(token_arrive[ii]);
token[ii]--;
 
oflit.write(mflit);
 
if(mflit.ftype == F_TL) break;
}
}
}
 
 
void Network_Adapter::oport() {
FLIT mflit;
while(1) {
mflit = oflit.read();
OP->write(mflit);
}
}
 
void Network_Adapter::iport() {
FLIT mflit;
while(1) {
mflit = IP->read();
iflit[mflit.vcn].write(mflit);
}
}
 
void Network_Adapter::credit_update(unsigned int ii) {
 
CPa[ii].write(false);
while(1) {
if(!CP[ii].read())
wait(CP[ii].posedge_event());
token[ii]++;
token_arrive[ii].notify();
CPa[ii].write(true);
 
wait(CP[ii].negedge_event());
CPa[ii].write(false);
}
}
bool Network_Adapter::check_frame(const FRAME& frame)
{
// TODO: check the integerity, dummy right noe
return true;
}
 
 
 
 
/init/vc/tb/noctb.v
0,0 → 1,48
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Test bench.
History:
03/03/2011 Initial version. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
`timescale 1ns/1ps
 
module noctb;
parameter DW = 8; // the data width of a single virtual circuit
parameter VCN = 2; // the number of VCs per direction
parameter DIMX = 4; // the X dimension
parameter DIMY = 4; // the Y dimension
reg rst_n;
noc_top #(.DW(DW), .VCN(VCN), .DIMX(DIMX), .DIMY(DIMY))
NoC (.rst_n(rst_n)); // the mesh network
 
AnaProc ANAM(); // the global performance analyser
initial begin
rst_n = 0;
 
# 133;
 
rst_n = 1;
 
end
 
endmodule // noctb
 
 
 
/init/vc/tb/rtwrapper.v
0,0 → 1,283
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The wrapper for the synthesized router.
History:
28/05/2009 Initial version. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module router_hdl(/*AUTOARG*/
// Outputs
sia, wia, nia, eia, lia, sic, wic, nic, eic, lic, so0, so1, so2,
so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3,
lo0, lo1, lo2, lo3, soft, woft, noft, eoft, loft, sovc, wovc, novc,
eovc, lovc, soca, woca, noca, eoca, loca,
// Inputs
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift,
sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa,
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rstn
);
 
parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router
parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN
parameter FT = 3;// the number of types of flits
parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit
input [SCN-1:0] si0, si1, si2, si3;
input [SCN-1:0] wi0, wi1, wi2, wi3;
input [SCN-1:0] ni0, ni1, ni2, ni3;
input [SCN-1:0] ei0, ei1, ei2, ei3;
input [SCN-1:0] li0, li1, li2, li3;
input [FT-1:0] sift, wift, nift, eift, lift;
input [VCN-1:0] sivc, wivc, nivc, eivc, livc;
output sia, wia, nia, eia, lia;
output [VCN-1:0] sic, wic, nic, eic, lic;
input [VCN-1:0] sica, wica, nica, eica, lica;
output [SCN-1:0] so0, so1, so2, so3;
output [SCN-1:0] wo0, wo1, wo2, wo3;
output [SCN-1:0] no0, no1, no2, no3;
output [SCN-1:0] eo0, eo1, eo2, eo3;
output [SCN-1:0] lo0, lo1, lo2, lo3;
output [FT-1:0] soft, woft, noft, eoft, loft;
output [VCN-1:0] sovc, wovc, novc, eovc, lovc;
input soa, woa, noa, eoa, loa;
input [VCN-1:0] soc, woc, noc, eoc, loc;
output [VCN-1:0] soca, woca, noca, eoca, loca;
 
input [7:0] addrx, addry;
input rst_n;
wire [SCN-1:0] psi0, psi1, psi2, psi3;
wire [SCN-1:0] pwi0, pwi1, pwi2, pwi3;
wire [SCN-1:0] pni0, pni1, pni2, pni3;
wire [SCN-1:0] pei0, pei1, pei2, pei3;
wire [SCN-1:0] pli0, pli1, pli2, pli3;
wire [FT-1:0] psift, pwift, pnift, peift, plift;
wire [VCN-1:0] psivc, pwivc, pnivc, peivc, plivc;
wire psia, pwia, pnia, peia, plia;
wire [VCN-1:0] psic, pwic, pnic, peic, plic;
wire [VCN-1:0] psica, pwica, pnica, peica, plica;
wire [SCN-1:0] pso0, pso1, pso2, pso3;
wire [SCN-1:0] pwo0, pwo1, pwo2, pwo3;
wire [SCN-1:0] pno0, pno1, pno2, pno3;
wire [SCN-1:0] peo0, peo1, peo2, peo3;
wire [SCN-1:0] plo0, plo1, plo2, plo3;
wire [FT-1:0] psoft, pwoft, pnoft, peoft, ploft;
wire [VCN-1:0] psovc, pwovc, pnovc, peovc, plovc;
wire psoa, pwoa, pnoa, peoa, ploa;
wire [VCN-1:0] psoc, pwoc, pnoc, peoc, ploc;
wire [VCN-1:0] psoca, pwoca, pnoca, peoca, ploca;
wire [7:0] paddrx, paddry;
wire prst_n;
 
router RT (
.sia ( psia ),
.wia ( pwia ),
.nia ( pnia ),
.eia ( peia ),
.lia ( plia ),
.sic ( psic ),
.wic ( pwic ),
.nic ( pnic ),
.eic ( peic ),
.lic ( plic ),
.so0 ( pso0 ),
.so1 ( pso1 ),
.so2 ( pso2 ),
.so3 ( pso3 ),
.wo0 ( pwo0 ),
.wo1 ( pwo1 ),
.wo2 ( pwo2 ),
.wo3 ( pwo3 ),
.no0 ( pno0 ),
.no1 ( pno1 ),
.no2 ( pno2 ),
.no3 ( pno3 ),
.eo0 ( peo0 ),
.eo1 ( peo1 ),
.eo2 ( peo2 ),
.eo3 ( peo3 ),
.lo0 ( plo0 ),
.lo1 ( plo1 ),
.lo2 ( plo2 ),
.lo3 ( plo3 ),
.soft ( psoft ),
.woft ( pwoft ),
.noft ( pnoft ),
.eoft ( peoft ),
.loft ( ploft ),
.sovc ( psovc ),
.wovc ( pwovc ),
.novc ( pnovc ),
.eovc ( peovc ),
.lovc ( plovc ),
.soca ( psoca ),
.woca ( pwoca ),
.noca ( pnoca ),
.eoca ( peoca ),
.loca ( ploca ),
.si0 ( psi0 ),
.si1 ( psi1 ),
.si2 ( psi2 ),
.si3 ( psi3 ),
.wi0 ( pwi0 ),
.wi1 ( pwi1 ),
.wi2 ( pwi2 ),
.wi3 ( pwi3 ),
.ni0 ( pni0 ),
.ni1 ( pni1 ),
.ni2 ( pni2 ),
.ni3 ( pni3 ),
.ei0 ( pei0 ),
.ei1 ( pei1 ),
.ei2 ( pei2 ),
.ei3 ( pei3 ),
.li0 ( pli0 ),
.li1 ( pli1 ),
.li2 ( pli2 ),
.li3 ( pli3 ),
.sift ( psift ),
.wift ( pwift ),
.nift ( pnift ),
.eift ( peift ),
.lift ( plift ),
.sivc ( psivc ),
.wivc ( pwivc ),
.nivc ( pnivc ),
.eivc ( peivc ),
.livc ( plivc ),
.sica ( psica ),
.wica ( pwica ),
.nica ( pnica ),
.eica ( peica ),
.lica ( plica ),
.soa ( psoa ),
.woa ( pwoa ),
.noa ( pnoa ),
.eoa ( peoa ),
.loa ( ploa ),
.soc ( psoc ),
.woc ( pwoc ),
.noc ( pnoc ),
.eoc ( peoc ),
.loc ( ploc ),
.addrx ( paddrx ),
.addry ( paddry ),
.rst_n ( prst_n )
);
assign sia = psia ;
assign wia = pwia ;
assign nia = pnia ;
assign eia = peia ;
assign lia = plia ;
assign sic = psic ;
assign wic = pwic ;
assign nic = pnic ;
assign eic = peic ;
assign lic = plic ;
assign so0 = pso0 ;
assign so1 = pso1 ;
assign so2 = pso2 ;
assign so3 = pso3 ;
assign wo0 = pwo0 ;
assign wo1 = pwo1 ;
assign wo2 = pwo2 ;
assign wo3 = pwo3 ;
assign no0 = pno0 ;
assign no1 = pno1 ;
assign no2 = pno2 ;
assign no3 = pno3 ;
assign eo0 = peo0 ;
assign eo1 = peo1 ;
assign eo2 = peo2 ;
assign eo3 = peo3 ;
assign lo0 = plo0 ;
assign lo1 = plo1 ;
assign lo2 = plo2 ;
assign lo3 = plo3 ;
assign soft = psoft ;
assign woft = pwoft ;
assign noft = pnoft ;
assign eoft = peoft ;
assign loft = ploft ;
assign sovc = psovc ;
assign wovc = pwovc ;
assign novc = pnovc ;
assign eovc = peovc ;
assign lovc = plovc ;
assign soca = psoca ;
assign woca = pwoca ;
assign noca = pnoca ;
assign eoca = peoca ;
assign loca = ploca ;
assign psi0 = si0 ;
assign psi1 = si1 ;
assign psi2 = si2 ;
assign psi3 = si3 ;
assign pwi0 = wi0 ;
assign pwi1 = wi1 ;
assign pwi2 = wi2 ;
assign pwi3 = wi3 ;
assign pni0 = ni0 ;
assign pni1 = ni1 ;
assign pni2 = ni2 ;
assign pni3 = ni3 ;
assign pei0 = ei0 ;
assign pei1 = ei1 ;
assign pei2 = ei2 ;
assign pei3 = ei3 ;
assign pli0 = li0 ;
assign pli1 = li1 ;
assign pli2 = li2 ;
assign pli3 = li3 ;
assign psift = sift ;
assign pwift = wift ;
assign pnift = nift ;
assign peift = eift ;
assign plift = lift ;
assign psivc = sivc ;
assign pwivc = wivc ;
assign pnivc = nivc ;
assign peivc = eivc ;
assign plivc = livc ;
assign psica = sica ;
assign pwica = wica ;
assign pnica = nica ;
assign peica = eica ;
assign plica = lica ;
assign psoa = soa ;
assign pwoa = woa ;
assign pnoa = noa ;
assign peoa = eoa ;
assign ploa = loa ;
assign psoc = soc ;
assign pwoc = woc ;
assign pnoc = noc ;
assign peoc = eoc ;
assign ploc = loc ;
assign paddrx = addrx ;
assign paddry = addry ;
assign prst_n = rst_n ;
 
initial $sdf_annotate("../syn/file/router.sdf", RT);
endmodule
/init/vc/tb/node_top.v
0,0 → 1,125
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
A network node including a router, a NI and a processing element.
History:
03/03/2011 Initial version. <wsong83@gmail.com>
04/03/2011 Support VC. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module node_top(/*AUTOARG*/
// Outputs
sia, wia, nia, eia, sic, wic, nic, eic, so0, so1, so2, so3, wo0,
wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3, soft, woft,
noft, eoft, sovc, wovc, novc, eovc, soca, woca, noca, eoca,
// Inputs
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0,
ei1, ei2, ei3, sift, wift, nift, eift, sivc, wivc, nivc, eivc,
sica, wica, nica, eica, soa, woa, noa, eoa, soc, woc, noc, eoc,
rst_n
);
parameter DW = 32;
parameter VCN = 1;
parameter FT = 3;
parameter x = 0;
parameter y = 0;
parameter SCN = DW/2;
 
input [SCN-1:0] si0, si1, si2, si3;
input [SCN-1:0] wi0, wi1, wi2, wi3;
input [SCN-1:0] ni0, ni1, ni2, ni3;
input [SCN-1:0] ei0, ei1, ei2, ei3;
input [FT-1:0] sift, wift, nift, eift;
input [VCN-1:0] sivc, wivc, nivc, eivc;
output sia, wia, nia, eia;
output [VCN-1:0] sic, wic, nic, eic;
input [VCN-1:0] sica, wica, nica, eica;
 
output [SCN-1:0] so0, so1, so2, so3;
output [SCN-1:0] wo0, wo1, wo2, wo3;
output [SCN-1:0] no0, no1, no2, no3;
output [SCN-1:0] eo0, eo1, eo2, eo3;
output [FT-1:0] soft, woft, noft, eoft;
output [VCN-1:0] sovc, wovc, novc, eovc;
input soa, woa, noa, eoa;
input [VCN-1:0] soc, woc, noc, eoc;
output [VCN-1:0] soca, woca, noca, eoca;
 
wire [SCN-1:0] li0, li1, li2, li3;
wire [SCN-1:0] lo0, lo1, lo2, lo3;
wire [FT-1:0] lift;
wire [VCN-1:0] livc;
wire lia;
wire [VCN-1:0] lic;
wire [VCN-1:0] lica;
wire [FT-1:0] loft;
wire [VCN-1:0] lovc;
wire loa;
wire [VCN-1:0] loc;
wire [VCN-1:0] loca;
 
input rst_n;
 
// the network node
NetNode #(.DW(DW), .VCN(VCN), .FT(FT), .x(x), .y(y))
Node (
.doa(loa), .doc(loc),
.do0(lo0), .do1(lo1), .do2(lo2), .do3(lo3),
.doft(loft), .dovc(lovc), .doca(loca),
.dia(lia), .dic(lic),
.di0(li0), .di1(li1), .di2(li2), .di3(li3),
.dift(lift), .divc(livc), .dica(lica),
.rst_n(rst_n)
);
// router wrapper
router_hdl #(.DW(DW), .VCN(VCN))
RTN (
.so0(so0), .so1(so1), .so2(so2), .so3(so3), .soa(soa), .soft(soft), .sovc(sovc), .soc(soc), .soca(soca),
.wo0(wo0), .wo1(wo1), .wo2(wo2), .wo3(wo3), .woa(woa), .woft(woft), .wovc(wovc), .woc(woc), .woca(woca),
.no0(no0), .no1(no1), .no2(no2), .no3(no3), .noa(noa), .noft(noft), .novc(novc), .noc(noc), .noca(noca),
.eo0(eo0), .eo1(eo1), .eo2(eo2), .eo3(eo3), .eoa(eoa), .eoft(eoft), .eovc(eovc), .eoc(eoc), .eoca(eoca),
.lo0(lo0), .lo1(lo1), .lo2(lo2), .lo3(lo3), .loa(loa), .loft(loft), .lovc(lovc), .loc(loc), .loca(loca),
.si0(si0), .si1(si1), .si2(si2), .si3(si3), .sia(sia), .sift(sift), .sivc(sivc), .sic(sic), .sica(sica),
.wi0(wi0), .wi1(wi1), .wi2(wi2), .wi3(wi3), .wia(wia), .wift(wift), .wivc(wivc), .wic(wic), .wica(wica),
.ni0(ni0), .ni1(ni1), .ni2(ni2), .ni3(ni3), .nia(nia), .nift(nift), .nivc(nivc), .nic(nic), .nica(nica),
.ei0(ei0), .ei1(ei1), .ei2(ei2), .ei3(ei3), .eia(eia), .eift(eift), .eivc(eivc), .eic(eic), .eica(eica),
.li0(li0), .li1(li1), .li2(li2), .li3(li3), .lia(lia), .lift(lift), .livc(livc), .lic(lic), .lica(lica),
.addrx (b2chain(x)),
.addry (b2chain(y)),
.rstn (rst_n)
);
 
// binary to 1-of-4 (Chain) converter
function [7:0] b2chain;
input [3:0] data;
begin
b2chain[0] = (data[1:0] == 2'b00);
b2chain[1] = (data[1:0] == 2'b01);
b2chain[2] = (data[1:0] == 2'b10);
b2chain[3] = (data[1:0] == 2'b11);
b2chain[4] = (data[3:2] == 2'b00);
b2chain[5] = (data[3:2] == 2'b01);
b2chain[6] = (data[3:2] == 2'b10);
b2chain[7] = (data[3:2] == 2'b11);
end
endfunction
 
endmodule // node_top
/init/vc/tb/ni.h
0,0 → 1,69
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Network interface for the VC router.
History:
20/08/2008 Initial version. <wsong83@gmail.com>
30/09/2010 Use template style packet definition. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
 
*/
 
#ifndef NETWORK_ADAPTER_H_
#define NETWORK_ADAPTER_H_
 
#include "define.h"
#include <systemc.h>
 
SC_MODULE(Network_Adapter)
{
public:
SC_HAS_PROCESS(Network_Adapter);
Network_Adapter(
sc_module_name name // module name
,unsigned int x // location x
,unsigned int y // location y
);
~Network_Adapter();
// interface with processor
sc_port<sc_fifo_in_if<FRAME> > frame_in; // frame for transmission
sc_port<sc_fifo_out_if<FRAME> > frame_out; // frame for receiving
// interface with router
sc_port<sc_fifo_in_if<FLIT> > IP [SubChN]; // input port from IO driver
sc_port<sc_fifo_out_if<FLIT> > OP [SubChN]; // output port to IO driver
sc_in<bool> CP [SubChN]; // the credit input from the router input buffer
sc_out<bool> CPa [SubChN]; // ack to the credit
 
private:
unsigned int loc_x,loc_y; // location information
sc_fifo<FLIT> oflit; // the current flit under transmission
sc_fifo<FLIT> iflit [SubChN]; // the current flits under receiving from all input VCs
unsigned int token [SubChN]; // the token ready for each output VC
sc_event token_arrive [SubChN]; // the token ready event
// functional thread
void ibuffer_thread(unsigned int); // input buffer respond thread
void obuffer_thread(unsigned int); // output buffer respond thread
void oport(); // the thread transmitting flit
void iport(); // the thread receiving flits
void credit_update(unsigned int); // receive credits and update the available tokens
 
// other functions
bool check_frame(const FRAME& frame); // check the correctness of frame received
};
 
#endif
 
/init/vc/tb/netnode.cpp
0,0 → 1,23
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The SystemC module of network node including the processing element and the network interface.
Currently the transmission FIFO is 500 frame deep.
History:
26/02/2011 Initial version. <wsong83@gmail.com>
*/
 
#include "netnode.h"
 
NCSC_MODULE_EXPORT(NetNode)
 
/init/vc/sim/compile.sh
0,0 → 1,58
#!/bin/bash
#
# Asynchronous SDM NoC
# (C)2011 Wei Song
# Advanced Processor Technologies Group
# Computer Science, the Univ. of Manchester, UK
#
# Authors:
# Wei Song wsong83@gmail.com
#
# License: LGPL 3.0 or later
#
# The script to compile the SystemC/Verilog mixed NoC simulation
#
# History:
# 05/06/2011 CLean up for opensource. <wsong83@gmail.com>
#
 
# make sure the LDVHOME environment is ready for NC-Simulator, IUS/LDV, Cadence
export NCSC_GCC=${LDVHOME}/tools/systemc/gcc/bin/g++
 
CXXFLAG="-c -g -Wall -I../../common/tb -I../tb -I../"
 
# remove the files from last run
rm -fr INCA_libs
rm *.o
rm *.so
 
# compile verilog files
# cell library
ncvlog -nowarn RECOMP ../../lib/NangateOpenCellLibrary_typical_conditional.v
# synthesized design
ncvlog ../syn/file/router_syn.v
# other verilog test bench files
ncvlog -incdir ../ ../../common/tb/anaproc.v
ncvlog -sv -incdir ../ ../tb/rtwrapper.v
ncvlog -incdir ../ ../tb/netnode.v
ncvlog -sv -incdir ../ ../tb/noc_top.v
ncvlog -sv -incdir ../ ../tb/node_top.v
ncvlog ../tb/noctb.v
 
#compile SystemC files
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../../common/tb/sim_ana.cpp
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../../common/tb/anaproc.cpp
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/netnode.cpp
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/ni.cpp
ncsc -compiler $NCSC_GCC -cflags "${CXXFLAG}" ../tb/rtdriver.cpp
 
# build the run time link library
${NCSC_GCC} -Wl -shared -o sysc.so -L${CDS_LNX86_ROOT}/ldv_2009_sc/tools/lib \
sim_ana.o anaproc.o netnode.o ni.o rtdriver.o \
${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libncscCoSim_sh.so \
${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libncscCoroutines_sh.so \
${CDS_LNX86_ROOT}/ldv_2009_sc/tools/systemc/lib/gnu/libsystemc_sh.so
 
# elaborate the simulation
ncelab -timescale 1ns/1ps -access +rwc -loadsc sysc.so worklib.noctb
 
init/vc/sim/compile.sh Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: init/vc/syn/script/compile.tcl =================================================================== --- init/vc/syn/script/compile.tcl (revision 43) +++ init/vc/syn/script/compile.tcl (revision 44) @@ -15,7 +15,7 @@ # 31/05/2009 Initial version. set rm_top router -set rm_para "VCN=>2, DW=>8, PD=>2" +set rm_para "VCN=>2, DW=>8, PD=>1" # working directory if {[file exists work ] && [file isdirectory work ]} {
/init/vc/define.v
13,8 → 13,9
History:
20/09/2009 Initial version. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
05/06/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
// currently VC router does not have any configurable structure variables
// Whether use the MRMA instead of MNMA allocators in the VC allocator
// `define ENABLE_MRMA

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.