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https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc/branches
- from Rev 58 to Rev 59
- ↔ Reverse comparison
Rev 58 → Rev 59
/clos_opt/common/src/minus1.v
12,13 → 12,13
1-of-4 data decrease by one |
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History: |
10/06/2010 Initial version. <wsong83@gmail.com> |
11/06/2010 Initial version. <wsong83@gmail.com> |
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*/ |
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module minus1 (/*AUTOARG*/ |
// Outputs |
d_o, co, zero, nzero, |
d_o, zero, nzero, |
// Inputs |
en, nen, d_i |
); |
26,7 → 26,6
input en, nen; // enable and disable |
input [3:0] d_i; // the data to be reduced by one |
output [3:0] d_o; // the data output of deduction |
output co; // the carry output |
output zero; // the zero output |
output nzero; // the non-zero status |
|
43,7 → 42,7
c2 CD0 (.a0(d_i[1]), .a1(en), .q(d_d[0])); |
c2 CD1 (.a0(d_i[2]), .a1(en), .q(d_d[1])); |
c2 CD2 (.a0(d_i[3]), .a1(en), .q(d_d[2])); |
c2 CD2 (.a0(d_i[0]), .a1(en), .q(d_d[2])); |
c2 CD3 (.a0(d_i[0]), .a1(en), .q(d_d[2])); |
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assign d_o = d_d | d_r; |
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/clos_opt/common/src/addr_dec.v
12,21 → 12,27
Reduce the XY address by one |
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History: |
10/06/2010 Initial version. <wsong83@gmail.com> |
11/06/2010 Initial version. <wsong83@gmail.com> |
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*/ |
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module addr_dec(/*AUTOARG*/); |
module addr_dec(/*AUTOARG*/ |
// Outputs |
xo, yo, |
// Inputs |
xi, yi |
); |
input [7:0] xi, yi; // the addresses input |
output [7:0] xo, yo; // the addresses output |
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wire [7:0] xm, ym; // internal deduction output |
wire [3:0] co, zero, nzero, en, nen; // internal control bit |
wire [3:0] zero, nzero, en, nen; // internal control bit |
wire xzero; // high when addr X is zero |
wire yzero; // high when addr Y is zero |
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// address X |
minus1 DECX0 ( |
.d_o ( xm[3:0] ), |
.co ( co[0] ), |
.zero ( zero[0] ), |
.nzero ( nzero[0] ), |
.en ( en[0] ), |
36,7 → 42,6
|
minus1 DECX1 ( |
.d_o ( xm[7:4] ), |
.co ( co[1] ), |
.zero ( zero[1] ), |
.nzero ( nzero[1] ), |
.en ( en[1] ), |
47,7 → 52,6
// address Y |
minus1 DECY0 ( |
.d_o ( ym[3:0] ), |
.co ( co[2] ), |
.zero ( zero[2] ), |
.nzero ( nzero[2] ), |
.en ( en[2] ), |
57,7 → 61,6
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minus1 DECY1 ( |
.d_o ( ym[7:4] ), |
.co ( co[3] ), |
.zero ( zero[3] ), |
.nzero ( nzero[3] ), |
.en ( en[3] ), |
66,5 → 69,15
); |
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// handle the control bits |
assign en[0] = |nzero[1:0]; // reduce the |
assign |
assign en[0] = |nzero[1:0]; |
ctree #(2) XHE (.ci({zero[0],nzero[1]}), .co(en[1])); |
c2 XZF (.a0(zero[0]), .a1(zero[1]), .q(xzero)); |
ctree #(2) YLE (.ci({xzero,|nzero[3:2]}), .co(en[2])); |
ctree #(3) YHE (.ci({xzero,zero[2],nzero[3]}), .co(en[3])); |
assign nen[0] = xzero; |
assign nen[1] = zero[1]|nzero[0]; |
c2 YZF (.a0(zero[2]), .a1(zero[3]), .q(yzero)); |
assign nen[2] = (|nzero[1:0])|yzero; |
assign nen[3] = (|nzero[2:0])|zero[3]; |
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endmodule // addr_dec |