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Rev 61 → Rev 62
/clos_opt/clos_opt/define.v
0,0 → 1,55
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Router configuration header file for SDM routers. |
|
Possible configuration combinations: |
* Wormhole (set VCN to 1) |
ENABLE_EOF [ENABLE_CHANNEL_SLICING] [ENABLE_LOOKAHEAD] |
* SDM (set VCN > 1 without define ENABLE_CLOS) |
ENABLE_EOF [ENABLE_CHANNEL_SLICING] [ENABLE_LOOKAHEAD] [ENABLE_MRMA] |
* SDM-Clos (set VCN > 1 and define ENABLE_CLOS) |
ENABLE_EOF ENABLE_CLOS [ENABLE_CHANNEL_SLICING] [ENABLE_LOOKAHEAD] [ENABLE_CRRD [ENABLE_MRMA]] [ENABLE_BUFFERED_CLOS] |
|
The combinations not presented above are illegal, which may produce unexpected failures. |
|
History: |
20/09/2009 Initial version. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
26/05/2011 Add ENABLE_MRMA and configuration explanations. <wsong83@gmail.com> |
21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com> |
|
*/ |
|
// if VCN > 1, set ENABLE_CLOS to use the 2-stage Clos switch for less switching area |
// `define ENABLE_CLOS |
|
// Using the asynchronous virsion of the Concurrent round-robine dispatching |
// algorithm for the 2-stage Clos can save some area but introduce a 5% |
// throughput loss |
// `define ENABLE_CRRD |
|
// for the SDM router using crossbars and the Clos router using CRRD |
// algorithm, using the multi-resource match arbiter may save the area in |
// switch allocators |
// `define ENABLE_MRMA |
|
// set to enable channel slicing for fast data paths |
// `define ENABLE_CHANNEL_SLICING |
|
// set to use the early acknowledge of lokkahead pipelines in the critical cycle |
// `define ENABLE_LOOKAHEAD |
|
// always set in wormhole and SDM routers to enable the eof bit in data pipeline stages |
`define ENABLE_EOF |
|
// set to insert buffers inside the Clos switch |
`define ENABLE_BUFFERED_CLOS |
/clos_opt/sdm/src/input_buf.v
25,7 → 25,7
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com> |
24/05/2011 Clean up for opensource. <wsong83@gmail.com> |
01/06/2011 Use the comp4 common comparator rather than the chain_comparator defined in this module. <wsong83@gmail.com> |
|
21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com> |
*/ |
|
// the router structure definitions |
73,11 → 73,11
|
`ifdef ENABLE_CHANNEL_SLICING |
wire [SCN-1:0] rtrst; // rt decoder reset for each sub-channel |
wire [PD:0][SCN-1:0] pd4, pda, pdan; // data wires for the internal pipeline stages |
wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline stages |
|
`else |
wire rtrst; // rt decode reset |
wire [PD:0] pd4, pda, pdan; // data wires for the internal pipeline satges |
wire [PD:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline satges |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
genvar i, j; |
92,16 → 92,26
.o1 ( pd1[i][j] ), |
.o2 ( pd2[i][j] ), |
.o3 ( pd3[i][j] ), |
.o4 ( pd4[i][j] ), |
//.o4 ( pd4[i][j] ), |
.ia ( pda[i+1][j] ), |
.i0 ( pd0[i+1][j] ), |
.i1 ( pd1[i+1][j] ), |
.i2 ( pd2[i+1][j] ), |
.i3 ( pd3[i+1][j] ), |
.i4 ( pd4[i+1][j] ), |
//.i4 ( pd4[i+1][j] ), |
.oa ( pdan[i][j] ) |
); |
|
pipen #(.DW(1)) |
PEoF ( |
.d_in_a ( ), |
.d_out ( pd4[i][j] ), |
.d_in ( pd4[i+1][j] ), |
.d_out_a ( pd4an[i][j] ) |
); |
|
end // block: SC |
|
|
`else // !`ifdef ENABLE_CHANNEL_SLICING |
pipe4 #(.DW(DW)) |
110,15 → 120,24
.o1 ( pd1[i] ), |
.o2 ( pd2[i] ), |
.o3 ( pd3[i] ), |
.o4 ( pd4[i] ), |
//.o4 ( pd4[i] ), |
.ia ( pda[i+1] ), |
.i0 ( pd0[i+1] ), |
.i1 ( pd1[i+1] ), |
.i2 ( pd2[i+1] ), |
.i3 ( pd3[i+1] ), |
.i4 ( pd4[i+1] ), |
//.i4 ( pd4[i+1] ), |
.oa ( pdan[i] ) |
); |
|
pipen #(.DW(1)) |
PEoF ( |
.d_in_a ( ), |
.d_out ( pd4[i] ), |
.d_in ( pd4[i+1] ), |
.d_out_a ( pd4an[i] ) |
); |
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
end // block: DP |
endgenerate |
125,6 → 144,7
|
generate for(i=1; i<PD; i++) begin: DPA |
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0; |
assign pd4an[i] = pdan[i]; |
end |
endgenerate |
|
210,6 → 230,7
.rt_err ( rt_err ), |
.rst_n ( rst_n ) |
); |
assign pd4an[0][j] = pdan[0][j]; |
end // block: SC |
`else // !`ifdef ENABLE_CHANNEL_SLICING |
subc_ctl SCH_C ( |
222,6 → 243,7
.rt_err ( rt_err ), |
.rst_n ( rst_n ) |
); |
assign pd4an[0] = pdan[0]; |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
// the router controller part |
/clos_opt/sdm/src/output_buf.v
21,6 → 21,7
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com> |
22/10/2010 Parameterize the number of pipelines in output buffers. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
21/06/2011 Move the eof logic in every pipeline stage outside the pipe4 module. <wsong83@gmail.com> |
|
*/ |
|
47,12 → 48,12
input [SCN-1:0] i4, oa; // eof and ack |
output [SCN-1:0] o4, ia; |
wire [SCN-1:0] ian_dly; |
wire [PD:0][SCN-1:0] pd4, pda, pdan; // internal eof and ack |
wire [PD:0][SCN-1:0] pd4, pda, pdan, pd4an; // internal eof and ack |
`else |
input i4, oa; // eof and ack |
output o4, ia; |
wire ian_dly; |
wire [PD:0] pd4, pda, pdan; // internal eof and ack |
wire [PD:0] pd4, pda, pdan, pd4an; // internal eof and ack |
`endif |
|
|
67,15 → 68,23
.o1 ( pd1[i][j] ), |
.o2 ( pd2[i][j] ), |
.o3 ( pd3[i][j] ), |
.o4 ( pd4[i][j] ), |
//.o4 ( pd4[i][j] ), |
.ia ( pda[i+1][j] ), |
.i0 ( pd0[i+1][j] ), |
.i1 ( pd1[i+1][j] ), |
.i2 ( pd2[i+1][j] ), |
.i3 ( pd3[i+1][j] ), |
.i4 ( pd4[i+1][j] ), |
//.i4 ( pd4[i+1][j] ), |
.oa ( pdan[i][j] ) |
); |
|
pipen #(.DW(1)) |
PEoF ( |
.d_in_a ( ), |
.d_out ( pd4[i][j] ), |
.d_in ( pd4[i+1][j] ), |
.d_out_a ( pd4an[i][j] ) |
); |
end // block: SC |
|
`else // !`ifdef ENABLE_CHANNEL_SLICING |
85,15 → 94,24
.o1 ( pd1[i] ), |
.o2 ( pd2[i] ), |
.o3 ( pd3[i] ), |
.o4 ( pd4[i] ), |
//.o4 ( pd4[i] ), |
.ia ( pda[i+1] ), |
.i0 ( pd0[i+1] ), |
.i1 ( pd1[i+1] ), |
.i2 ( pd2[i+1] ), |
.i3 ( pd3[i+1] ), |
.i4 ( pd4[i+1] ), |
//.i4 ( pd4[i+1] ), |
.oa ( pdan[i] ) |
); |
|
pipen #(.DW(1)) |
PEoF ( |
.d_in_a ( ), |
.d_out ( pd4[i] ), |
.d_in ( pd4[i+1] ), |
.d_out_a ( pd4an[i] ) |
); |
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
end // block: DP |
endgenerate |
115,6 → 133,7
assign ia[j] = pda[PD][j]|pd4[PD-1][j]; |
`endif |
assign pdan[0][j] = (~oa[j])&rst_n; |
assign pd4an[0][j] = pdan[0][j]; |
end |
`else |
`ifdef ENABLE_LOOKAHEAD |
124,6 → 143,7
assign ia = pda[PD]|pd4[PD-1]; |
`endif |
assign pdan[0] = (~oa)&rst_n; |
assign pd4an[0] = pdan[0]; |
`endif // !`ifdef ENABLE_LOOKAHEAD |
endgenerate |
|
/clos_opt/common/src/pipe4.v
16,20 → 16,15
05/05/2009 Initial version. <wsong83@gmail.com> |
17/04/2011 Replace the common ack generation. <wsong83@gmail.com> |
26/05/2011 Clean up for opensource. <wsong83@gmail.com> |
21/06/2011 Remove the eof as it makes confusion. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module pipe4(/*AUTOARG*/ |
// Outputs |
ia, o0, o1, o2, o3, |
// Inputs |
i0, i1, i2, i3, oa |
`ifdef ENABLE_EOF |
, i4, o4 |
`endif |
); |
|
parameter DW = 32; // the data width of the pipeline stage |
40,11 → 35,6
input oa; // input ack |
output ia; // output ack |
|
`ifdef ENABLE_EOF |
output o4; // the eof bit |
input i4; |
`endif |
|
// internal signals |
wire [SCN-1:0] tack; |
|
59,11 → 49,6
dc2 DC3 (.d(i3[i]), .a(oa), .q(o3[i])); |
end endgenerate |
|
// the eof bit |
`ifdef ENABLE_EOF |
dc2 DD_DC4 (.d(i4), .a(oa), .q(o4)); |
`endif |
|
// generate the input ack |
assign tack = o0|o1|o2|o3; |
ctree #(.DW(SCN)) ACKT (.ci(tack), .co(ia)); |
/clos_opt/common/src/dclos.v
16,6 → 16,7
17/07/2010 Initial version. <wsong83@gmail.com> |
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com> |
|
*/ |
|
22,7 → 23,7
// the router structure definitions |
`include "define.v" |
|
module dclos (/*AUTOARG*/ |
module dclos ( |
// Outputs |
so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, |
eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia, |
31,6 → 32,9
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, |
ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa, |
woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg |
`ifdef ENABLE_BUFFERED_CLOS |
, soa4, woa4, noa4, eoa4, loa4 |
`endif |
); |
|
parameter MN = 2; // number of CMs |
55,11 → 59,17
output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4; |
output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia; |
input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa; |
`ifdef ENABLE_BUFFERED_CLOS |
input [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers |
`endif |
`else |
input [NN-1:0] si4, wi4, ni4, ei4, li4; |
output [NN-1:0] so4, wo4, no4, eo4, lo4; |
output [NN-1:0] sia, wia, nia, eia, lia; |
input [NN-1:0] soa, woa, noa, eoa, loa; |
`ifdef ENABLE_BUFFERED_CLOS |
input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers |
`endif |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs |
77,9 → 87,15
`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4; |
wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4; |
`endif |
`else |
wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4; |
wire [MN-1:0] imosa, imowa, imona, imoea, imola; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4; |
`endif |
`endif |
|
// input of CMs |
94,8 → 110,14
wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3; |
`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0][4:0][SCN-1:0] cmoa4; |
`endif |
`else |
wire [MN-1:0][4:0] cmo4, cmoa; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0][4:0] cmoa4; |
`endif |
`endif |
|
genvar i,j,k; |
/clos_opt/common/src/dcb.v
15,6 → 15,7
History: |
17/07/2010 Initial version. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
21/06/2011 Prepare to support buffered Clos. <wsong83@gmail.com> |
|
*/ |
|
21,11 → 22,14
// the router structure definitions |
`include "define.v" |
|
module dcb (/*AUTOARG*/ |
module dcb ( |
// Outputs |
o0, o1, o2, o3, ia, o4, |
// Inputs |
i0, i1, i2, i3, oa, i4, cfg |
`ifdef ENABLE_BUFFERED_CLOS |
, o4a |
`endif |
); |
|
parameter NN = 2; // number of input ports |
39,6 → 43,9
`ifdef ENABLE_CHANNEL_SLICING |
output [NN-1:0][SCN-1:0] ia, o4; // eof and ack |
input [MN-1:0][SCN-1:0] oa, i4; |
`ifdef ENABLE_BUFFERED_CLOS |
input [MN-1:0][SCN-1:0] oa4; // the eof ack from output buffer |
`endif |
`else |
output [NN-1:0] ia, o4; // eof and ack |
input [MN-1:0] oa, i4; |
50,8 → 57,14
|
`ifdef ENABLE_CHANNEL_SLICING |
wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [NN-1:0][SCN-1:0][MN-1:0] amd, am4; |
`endif |
`else |
wire [NN-1:0][MN-1:0] am, dm4; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [NN-1:0][MN-1:0] amd, am4; |
`endif |
`endif |
|
genvar i, j, k; |
66,13 → 79,25
and A3 (dm3[i][k][j], i3[j][k], cfg[i][j]); |
`ifdef ENABLE_CHANNEL_SLICING |
and A4 (dm4[i][k][j], i4[j][k], cfg[i][j]); |
`ifdef ENABLE_BUFFERED_CLOS |
and Aad (amd[j][k][i], oa[i][k], cfg[i][j]); |
c2 Aa4 (.q(am4[j][k][i]), .a0(oa4[i][k]), .a1(cfg[i][j])); |
assign am[j][k][i] = amd[j][k][i] | am4[j][k][i]; |
`else |
and Aa (am[j][k][i], oa[i][k], cfg[i][j]); |
`endif |
`endif |
end |
|
`ifndef ENABLE_CHANNEL_SLICING |
and A4 (dm4[i][j], i4[j], cfg[i][j]); |
`ifdef ENABLE_BUFFERED_CLOS |
and Aa (amd[j][i], oa[i], cfg[i][j]); |
c2 Aa4 (.q(am4[j][i]), .a0(oa4[i]), .a1(cfg[i][j])); |
assign am[j][i] = amd[j][i] | am4[j][i]; |
`else |
and Aa (am[j][i], oa[i], cfg[i][j]); |
`endif |
`endif |
end // block: IP |
end // block: EN |