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URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

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Rev 67 → Rev 68

/clos_opt/clos_opt/src/dclos1.v
0,0 → 1,24
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
The IMs of a buffered Clos for SDM-Clos routers
*** SystemVerilog is used ***
History:
07/07/2011 Initial version. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module dclos1 (/*AUTOARG*/);
parameter
/clos_opt/clos_opt/src/im.v
0,0 → 1,148
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
An IM of a buffered Clos for SDM-Clos routers
*** SystemVerilog is used ***
History:
07/07/2011 Initial version. <wsong83@gmail.com>
*/
 
// the router structure definitions
`include "define.v"
 
module im (/*AUTOARG*/
// Outputs
do0, do1, do2, do3, deco, dia, do4,
// Inputs
di0, di1, di2, di3, deci, di4, doa, doa4, rst_n
);
parameter MN = 2; // the number of CMs
parameter NN = 2; // the number of IPs in one IM
parameter DW = 8; // the data width of a single IP
parameter SN = 2; // the number of possible output directions
parameter SCN = DW/2; // the number of sub-channels in one IP
 
input [NN-1:0][SCN-1:0] di0, di1, di2, di3; // data input
input [NN-1:0][SN-1:0] deci; // decoded dir input
output [MN-1:0][SCN-1:0] do0, do1, do2, do3; // data output
output [MN-1:0][SN-1:0] deco; // decoded dir output
 
// eof bits and ack lines
`ifdef ENABLE_CHANNEL_SLICING
input [NN-1:0][SCN-1:0] di4; // data input
output [NN-1:0][SCN-1:0] dia; // input ack
output [MN-1:0][SCN-1:0] do4; // data output
input [MN-1:0][SCN-1:0] doa, doa4; // output ack
`else
input [NN-1:0] di4; // data input
output [NN-1:0] dia; // input ack
output [MN-1:0] do4; // data output
input [MN-1:0] doa, doa4; // output ack
`endif // !`ifdef ENABLE_CHANNEL_SLICING
`ifndef ENABLE_CRRD
input [MN-1:0][SN-1:0] cms; // the states from CMs
`endif
 
input rst_n; // global active low reset
 
wire cfg; // the configuration for the IM
wire [MN-1:0][SCN-1:0] imo0, imo1, imo2, imo3; // the IM output data
wire [MN-1:0][SN-1:0] imodec; // the IM output dec
`ifdef ENABLE_CHANNEL_SLICING
wire [MN-1:0][SCN-1:0] imo4; // IM output data
wire [MN-1:0][SCN-1:0] imoa, imoa4; // IM output ack
wire [MN-1:0][SCN-1:0] eofan, eofan, doan, deca, decan; // stage control acks
`else
wire [MN-1:0] imo4; // IM data output
wire [MN-1:0] imoa, imoa4; // IM output ack
wire [MN-1:0] eofan, eofan, doan, deca, decan; // stage control acks
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
genvar i;
 
// the data crossbar
dcb #(.NN(NN), .MN(MN), .DW(DW))
IMDCB (
.o0 ( imo0 ),
.o1 ( imo1 ),
.o2 ( imo2 ),
.o3 ( imo3 ),
.o4 ( imo4 ),
.ia ( dia ),
.i0 ( di0 ),
.i1 ( di1 ),
.i2 ( di2 ),
.i3 ( di3 ),
.i4 ( di4 ),
.oa ( imoa ),
.oa4 ( imoa4 ),
.cfg ( cfg )
);
 
// the crossbar for decoded direction
cb #(.NN(NN), .MN(MN), .DW(SN))
IMDECCB (
.data_in ( deci ),
.data_out ( imodec ),
.cfg ( cfg )
);
 
// the IM dispatcher
im_alloc #(.VCN(NN), .CMN(MN), .SN(SN))
IMD (
.IMr ( deci ),
.IMa ( ),
`ifndef ENABLE_CRRD
.CMs ( cms ),
`endif
.cfg ( cfg ),
.rst_n ( rst_n )
);
 
// the buffer stage for data
generate
for(i=0; i<MN; i++) begin: OPD
`ifdef ENABLE_CHANNEL_SLICING
for(j=0; j<SCN; j++) begin:SC
pipe4 #(.DW(2))
P (
.o0 ( do0[i][j] ),
.o1 ( do1[i][j] ),
.o2 ( do2[i][j] ),
.o3 ( do3[i][j] ),
.ia ( imoa[i][j] ),
.i0 ( imo0[i][j] ),
.i1 ( imo1[i][j] ),
.i2 ( imo2[i][j] ),
.i3 ( imo3[i][j] ),
.oa ( doan[i][j] )
);
pipen #(.DW(1))
PEoF (
.d_in_a ( ),
.d_out ( do4[i][j] ),
.d_in ( imo4[i][j] ),
.d_out_a ( eofa[i][j] ),
);
ppc PCTL (
.deca ( deca[i][j] ),
.
pipen #(.DW(SN))
PDEC (
 
endmodule // im
/clos_opt/clos_opt/stg/ibctl.v
1,7 → 1,7
// Verilog model for ibctl
// Generated by petrify 4.2 (compiled 15-Oct-03 at 3:06 PM)
// CPU time for synthesis (host <unknown>): 0.07 seconds
// Estimated area = 8.00
// CPU time for synthesis (host <unknown>): 0.11 seconds
// Estimated area = 11.00
 
// The circuit is self-resetting and does not need reset pin.
 
28,20 → 28,22
// Functions not mapped into library gates:
// ----------------------------------------
 
// Equation: dia = eof + do
or _U0 (dia, do, eof);
// Equation: dia = dia eofa' dec + eof + do
not _U0 (_X0, eofa);
and _U1 (_X1, dia, _X0, dec);
or _U2 (dia, do, eof, _X1);
 
// Equation: eofa = eof' eofa + doa'
not _U1 (_X0, doa);
not _U2 (_X1, eof);
and _U3 (_X2, _X1, eofa);
or _U4 (eofa, _X0, _X2);
not _U3 (_X2, doa);
not _U4 (_X3, eof);
and _U5 (_X4, _X3, eofa);
or _U6 (eofa, _X2, _X4);
 
// Equation: deca = eof' eofa + doa'
not _U5 (_X3, doa);
not _U6 (_X4, eof);
and _U7 (_X5, _X4, eofa);
or _U8 (deca, _X3, _X5);
not _U7 (_X5, doa);
not _U8 (_X6, eof);
and _U9 (_X7, _X6, eofa);
or _U10 (deca, _X5, _X7);
 
 
// signal values at the initial state:
/clos_opt/clos_opt/stg/ibctl.g
40,6 → 40,7
dia+/2 eof-
eof- doa-/2
eof- dia-/2
dec- dia-/2
doa-/2 deca+
doa-/2 eofa+
dia-/2 dec+
/clos_opt/clos_opt/stg/ibctl.g.ps
1,6 → 1,5
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/clos_opt/common/src/cb.v
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/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Unidirectional crossbar
*** SystemVerilog is used ***
History:
07/07/2011 Initial version. <wsong83@gmail.com>
*/
 
module cb (/*AUTOARG*/
// Outputs
data_out,
// Inputs
data_in, cfg
) ;
// parameters
parameter NN = 1; // number of input ports
parameter MN = 1; // number of output ports
parameter DW = 1; // datawidth a port
 
input [NN-1:0][DW-1:0] data_in; // input data
output [MN-1:0][DW-1:0] data_out; // output requests
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration
wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for data
// generate variable
genvar i, j, k;
 
// request matrix
generate
for (i=0; i<MN; i++) begin: EN
for (j=0; j<DW; j++) begin: SC
for (k=0; k<NN; k++) begin: IP
and AC (m[i][j][k], data_in[k][j], cfg[i][k]);
end
// the OR gates
assign data_out[i][j] = |m[i][j];
end
end
endgenerate
 
endmodule // cb
 
 

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