OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches
    from Rev 69 to Rev 70
    ↔ Reverse comparison
  •

Rev 69 → Rev 70

/clos_opt/clos_opt/src/cm.v
20,11 → 20,14
// the router structure definitions
`include "define.v"
 
module cm (/*AUTOARG*/
module cm (
// Outputs
do0, do1, do2, do3, dia, do4,
// Inputs
di0, di1, di2, di3, sdec, ndec, ldec, wdec, edec, di4, doa, doa4,
`ifndef ENABLE_CRRD
cms,
`endif
rst_n
);
 
55,12 → 58,6
input rst_n; // global active low reset
 
wire [KN-1:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3; // the data output of CM
`ifdef ENABLE_CHANNEL_SLICING
wire [KN-1:0][SCN-1:0] cmo4, cmoa, cmoa4; // data and ack wires
`else
wire [KN-1:0] cmo4, cmoa, cmoa4; // data and ack wires
`endif
wire [3:0] wcfg, ecfg, lcfg; // switch configuration
wire [1:0] scfg, ncfg; // switch configuration
 
68,78 → 65,78
 
// data switch
dcb_xy #(.VCN(1), .VCW(DW))
CM (
.sia ( dia[i][0] ),
.wia ( dia[i][1] ),
.nia ( dia[i][2] ),
.eia ( dia[i][3] ),
.lia ( dia[i][4] ),
.so0 ( cmo0[i][0] ),
.so1 ( cmo1[i][0] ),
.so2 ( cmo2[i][0] ),
.so3 ( cmo3[i][0] ),
.so4 ( cmo4[i][0] ),
.wo0 ( cmo0[i][1] ),
.wo1 ( cmo1[i][1] ),
.wo2 ( cmo2[i][1] ),
.wo3 ( cmo3[i][1] ),
.wo4 ( cmo4[i][1] ),
.no0 ( cmo0[i][2] ),
.no1 ( cmo1[i][2] ),
.no2 ( cmo2[i][2] ),
.no3 ( cmo3[i][2] ),
.no4 ( cmo4[i][2] ),
.eo0 ( cmo0[i][3] ),
.eo1 ( cmo1[i][3] ),
.eo2 ( cmo2[i][3] ),
.eo3 ( cmo3[i][3] ),
.eo4 ( cmo4[i][3] ),
.lo0 ( cmo0[i][4] ),
.lo1 ( cmo1[i][4] ),
.lo2 ( cmo2[i][4] ),
.lo3 ( cmo3[i][4] ),
.lo4 ( cmo4[i][4] ),
.si0 ( di0[i][0] ),
.si1 ( di1[i][0] ),
.si2 ( di2[i][0] ),
.si3 ( di3[i][0] ),
.si4 ( di4[i][0] ),
.wi0 ( di0[i][1] ),
.wi1 ( di1[i][1] ),
.wi2 ( di2[i][1] ),
.wi3 ( di3[i][1] ),
.wi4 ( di4[i][1] ),
.ni0 ( di0[i][2] ),
.ni1 ( di1[i][2] ),
.ni2 ( di2[i][2] ),
.ni3 ( di3[i][2] ),
.ni4 ( di4[i][2] ),
.ei0 ( di0[i][3] ),
.ei1 ( di1[i][3] ),
.ei2 ( di2[i][3] ),
.ei3 ( di3[i][3] ),
.ei4 ( di4[i][3] ),
.li0 ( di0[i][4] ),
.li1 ( di1[i][4] ),
.li2 ( di2[i][4] ),
.li3 ( di3[i][4] ),
.li4 ( di4[i][4] ),
.soa ( cmoa[i][0] ),
.woa ( cmoa[i][1] ),
.noa ( cmoa[i][2] ),
.eoa ( cmoa[i][3] ),
.loa ( cmoa[i][4] ),
.soa4 ( cmoa4[i][0] ),
.woa4 ( cmoa4[i][1] ),
.noa4 ( cmoa4[i][2] ),
.eoa4 ( cmoa4[i][3] ),
.loa4 ( cmoa4[i][4] ),
.wcfg ( wcfg[i] ),
.ecfg ( ecfg[i] ),
.lcfg ( lcfg[i] ),
.scfg ( scfg[i] ),
.ncfg ( ncfg[i] )
);
CMDCB (
.sia ( dia[i][0] ),
.wia ( dia[i][1] ),
.nia ( dia[i][2] ),
.eia ( dia[i][3] ),
.lia ( dia[i][4] ),
.so0 ( do0[i][0] ),
.so1 ( do1[i][0] ),
.so2 ( do2[i][0] ),
.so3 ( do3[i][0] ),
.so4 ( do4[i][0] ),
.wo0 ( do0[i][1] ),
.wo1 ( do1[i][1] ),
.wo2 ( do2[i][1] ),
.wo3 ( do3[i][1] ),
.wo4 ( do4[i][1] ),
.no0 ( do0[i][2] ),
.no1 ( do1[i][2] ),
.no2 ( do2[i][2] ),
.no3 ( do3[i][2] ),
.no4 ( do4[i][2] ),
.eo0 ( do0[i][3] ),
.eo1 ( do1[i][3] ),
.eo2 ( do2[i][3] ),
.eo3 ( do3[i][3] ),
.eo4 ( do4[i][3] ),
.lo0 ( do0[i][4] ),
.lo1 ( do1[i][4] ),
.lo2 ( do2[i][4] ),
.lo3 ( do3[i][4] ),
.lo4 ( do4[i][4] ),
.si0 ( di0[i][0] ),
.si1 ( di1[i][0] ),
.si2 ( di2[i][0] ),
.si3 ( di3[i][0] ),
.si4 ( di4[i][0] ),
.wi0 ( di0[i][1] ),
.wi1 ( di1[i][1] ),
.wi2 ( di2[i][1] ),
.wi3 ( di3[i][1] ),
.wi4 ( di4[i][1] ),
.ni0 ( di0[i][2] ),
.ni1 ( di1[i][2] ),
.ni2 ( di2[i][2] ),
.ni3 ( di3[i][2] ),
.ni4 ( di4[i][2] ),
.ei0 ( di0[i][3] ),
.ei1 ( di1[i][3] ),
.ei2 ( di2[i][3] ),
.ei3 ( di3[i][3] ),
.ei4 ( di4[i][3] ),
.li0 ( di0[i][4] ),
.li1 ( di1[i][4] ),
.li2 ( di2[i][4] ),
.li3 ( di3[i][4] ),
.li4 ( di4[i][4] ),
.soa ( doa[i][0] ),
.woa ( doa[i][1] ),
.noa ( doa[i][2] ),
.eoa ( doa[i][3] ),
.loa ( doa[i][4] ),
.soa4 ( doa4[i][0] ),
.woa4 ( doa4[i][1] ),
.noa4 ( doa4[i][2] ),
.eoa4 ( doa4[i][3] ),
.loa4 ( doa4[i][4] ),
.wcfg ( wcfg[i] ),
.ecfg ( ecfg[i] ),
.lcfg ( lcfg[i] ),
.scfg ( scfg[i] ),
.ncfg ( ncfg[i] )
);
 
// the allocator
cm_alloc CMD (
162,7 → 159,5
.er ( edec ),
.lr ( ldec )
);
 
 
endmodule // cm
/clos_opt/clos_opt/src/im.v
24,11 → 24,11
// Outputs
do0, do1, do2, do3, deco, dia, do4,
// Inputs
di0, di1, di2, di3, deci, di4, doa, doa4
di0, di1, di2, di3, deci, di4, doa,
`ifndef ENABLE_CRRD
, cms
cms,
`endif
, rst_n
rst_n
);
parameter MN = 2; // the number of CMs
47,12 → 47,12
input [NN-1:0][SCN-1:0] di4; // data input
output [NN-1:0][SCN-1:0] dia; // input ack
output [MN-1:0][SCN-1:0] do4; // data output
input [MN-1:0][SCN-1:0] doa, doa4; // output ack
input [MN-1:0][SCN-1:0] doa; // output ack
`else
input [NN-1:0] di4; // data input
output [NN-1:0] dia; // input ack
output [MN-1:0] do4; // data output
input [MN-1:0] doa, doa4; // output ack
input [MN-1:0] doa; // output ack
`endif // !`ifdef ENABLE_CHANNEL_SLICING
`ifndef ENABLE_CRRD
/clos_opt/common/src/cb_xy.v
0,0 → 1,76
/*
Asynchronous SDM NoC
(C)2011 Wei Song
Advanced Processor Technologies Group
Computer Science, the Univ. of Manchester, UK
Authors:
Wei Song wsong83@gmail.com
License: LGPL 3.0 or later
Unidirectional crossbar using the XY routing algorithm.
*** SystemVerilog is used ***
History:
09/07/2009 Initial version. <wsong83@gmail.com>
 
*/
 
// the router structure definitions
 
module cb_xy (/*AUTOARG*/
// Outputs
so, wo, no, eo, lo,
// Inputs
si, wi, ni, ei, li, scfg, ncfg, wcfg, ecfg, lcfg
) ;
 
parameter DW = 8; // the wire count of the crossbar
 
input [DW-1:0] si, wi, ni, ei, li; // data input
output [DW-1:0] so, wo, no, eo, lo; // data output
input [1:0] scfg, ncfg; // configuration
input [3:0] wcfg, ecfg, lcfg; // configuration
// ANDed wires
wire [DW-1:0][1:0] tos, ton;
wire [DW-1:0][3:0] tow, toe, tol;
// generate
genvar i, j;
generate for (i=0; i<DW; i=i+1)
begin:OPA
and AN2S (tos[i][0], ni[i], scfg[0]);
and AL2S (tos[i][1], li[i], scfg[1]);
assign so[i] = |tos[i];
and AS2W (tow[i][0], si[i], wcfg[0]);
and AN2W (tow[i][1], ni[i], wcfg[1]);
and AE2W (tow[i][2], ei[i], wcfg[2]);
and AL2W (tow[i][3], li[i], wcfg[3]);
assign wo[i] = |tow[i];
 
and AS2N (ton[i][0], si[i], ncfg[0]);
and AL2N (ton[i][1], li[i], ncfg[1]);
assign no[i] = |ton[i];
 
and AS2E (toe[i][0], si[i], ecfg[0]);
and AW2E (toe[i][1], wi[i], ecfg[1]);
and AN2E (toe[i][2], ni[i], ecfg[2]);
and AL2E (toe[i][3], li[i], ecfg[3]);
assign eo[i] = |toe[i];
 
and AS2L (tol[i][0], si[i], lcfg[0]);
and AW2L (tol[i][1], wi[i], lcfg[1]);
and AN2L (tol[i][2], ni[i], lcfg[2]);
and AE2L (tol[i][3], ei[i], lcfg[3]);
assign lo[i] = |tol[i];
end // block: OPA
endgenerate
endmodule // cb_xy
 
 
 
clos_opt/common/src/cb_xy.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.