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    /async_sdm_noc/branches
    from Rev 76 to Rev 77
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Rev 76 → Rev 77

/clos_opt/clos_opt/src/input_buf.v
67,7 → 67,7
wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame
wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges
wire [5:0] raw_dec; // the routing decision from the comparator
wire [5:0] xy_dec; // the routing decision of the XY routing algorithm
wire [4:0] xy_dec; // the routing decision of the XY routing algorithm
wire [4:0] dec_reg; // the routing decision kept by C-gates
wire x_equal; // addr x = target x
wire rt_err; // route decoder error
82,7 → 82,7
wire deca; // the ack for routing requests
wire pda1; // the ack for the 1st pipeline stage
wire acko; // the ack from CB
wire [PD:0] pd4, pda, pdan, pd4an; // data wires for the internal pipeline satges
wire [PD:0] pd4, pda, pdan, pda4n; // data wires for the internal pipeline satges
`endif // !`ifdef ENABLE_CHANNEL_SLICING
wire decan;
 
111,7 → 111,7
.d_in_a ( ),
.d_out ( pd4[i][j] ),
.d_in ( pd4[i+1][j] ),
.d_out_a ( pd4an[i][j] )
.d_out_a ( pda4n[i][j] )
);
end // block: SC
136,7 → 136,7
.d_in_a ( ),
.d_out ( pd4[i] ),
.d_in ( pd4[i+1] ),
.d_out_a ( pd4an[i] )
.d_out_a ( pda4n[i] )
);
`endif // !`ifdef ENABLE_CHANNEL_SLICING
146,7 → 146,7
generate
for(i=2; i<PD; i++) begin: DPA
assign pdan[i] = rst_n ? ~(pda[i]|pd4[i-1]) : 0;
assign pd4an[i] = pdan[i];
assign pda4n[i] = pdan[i];
end
 
// in case only one pipeline stage is configured
203,7 → 203,7
assign xy_dec[4:2] = raw_dec[2] ? raw_dec[5:3] : 0;
// the decoded routing requests
pipen #(.DW(RN))
pipen #(.DW(5))
PDEC (
.d_in_a ( rta ),
.d_out ( dec_reg ),
/clos_opt/clos_opt/src/clos_buf.v
62,9 → 62,7
output [NN-1:0] so4, wo4, no4, eo4, lo4;
output [NN-1:0] sia, wia, nia, eia, lia;
input [NN-1:0] soa, woa, noa, eoa, loa;
// `ifdef ENABLE_BUFFERED_CLOS
input [NN-1:0] soa4, woa4, noa4, eoa4, loa4; // the eof ack from output buffers
// `endif
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
input [NN-1:0][3:0] sdec, ndec, ldec; // the routing requests
72,6 → 70,35
 
input rst_n; // global active low reset
 
wire [MN-1:0][SCN-1:0] sim0, sim1, sim2, sim3;
wire [MN-1:0][SCN-1:0] wim0, wim1, wim2, wim3;
wire [MN-1:0][SCN-1:0] nim0, nim1, nim2, nim3;
wire [MN-1:0][SCN-1:0] eim0, eim1, eim2, eim3;
wire [MN-1:0][SCN-1:0] lim0, lim1, lim2, lim3;
wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3;
wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3;
 
`ifdef ENABLE_CHANNEL_SLICING
wire [MN-1:0][SCN-1:0] sim4, wim4, nim4, eim4, lim4;
wire [MN-1:0][SCN-1:0] sima, wima, nima, eima, lima;
wire [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4;
wire [MN-1:0][4:0][SCN-1:0] cmo4;
`else
wire [MN-1:0] sim4, wim4, nim4, eim4, lim4;
wire [MN-1:0] sima, wima, nima, eima, lima;
wire [NN-1:0] soa4, woa4, noa4, eoa4, loa4;
wire [MN-1:0][4:0] cmo4;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
wire [MN-1:0][3:0] simdec, nimdec, limdec; // the routing requests
wire [MN-1:0][1:0] wimdec, eimdec; // the routing requests
 
`ifndef ENABLE_CRRD
wire [MN-1:0][3:0] sims, nims, lims;
wire [MN-1:0][1:0] wims, eims;
wire [MN-1:0][4:0] cms;
`endif
 
genvar i,j;
 
 
227,28 → 254,28
 
cm #(.KN(5), .DW(DW))
CMSW (
.do0 ( cmo0[i] ),
.do1 ( cmo1[i] ),
.do2 ( cmo2[i] ),
.do3 ( cmo3[i] ),
.dia ( cmia[i] ),
.do4 ( cmo4[i] ),
.di0 ( cmi0[i] ),
.di1 ( cmi1[i] ),
.di2 ( cmi2[i] ),
.di3 ( cmi3[i] ),
.sdec ( sdec[i] ),
.ndec ( ndec[i] ),
.ldec ( ldec[i] ),
.wdec ( wdec[i] ),
.edec ( edec[i] ),
.di4 ( cmi4[i] ),
.doa ( cmoa[i] ),
.doa4 ( cmoa4[i] ),
.do0 ( cmo0[i] ),
.do1 ( cmo1[i] ),
.do2 ( cmo2[i] ),
.do3 ( cmo3[i] ),
.dia ( cmia[i] ),
.do4 ( cmo4[i] ),
.di0 ( cmi0[i] ),
.di1 ( cmi1[i] ),
.di2 ( cmi2[i] ),
.di3 ( cmi3[i] ),
.sdec ( simdec[i] ),
.ndec ( nimdec[i] ),
.ldec ( limdec[i] ),
.wdec ( wimdec[i] ),
.edec ( eimdec[i] ),
.di4 ( cmi4[i] ),
.doa ( cmoa[i] ),
.doa4 ( cmoa4[i] ),
`ifndef ENABLE_CRRD
.cms ( cms[i] ),
.cms ( cms[i] ),
`endif
.rst_n ( rst_n )
.rst_n ( rst_n )
);
assign so0[i] = cmo0[i][0];
286,6 → 313,12
assign cmoa[i][4] = loa[i];
assign cmoa[i][4] = loa4[i];
 
assign sims[i] = {cms[i][4],cms[i][3],cms[i][2],cms[i][1]};
assign wims[i] = {cms[i][4],cms[i][3]};
assign nims[i] = {cms[i][4],cms[i][3],cms[i][1],cms[i][0]};
assign eims[i] = {cms[i][4],cms[i][1]};
assign lims[i] = {cms[i][3],cms[i][2],cms[i][1],cms[i][0]};
 
end
endgenerate
/clos_opt/clos_opt/src/router.v
87,11 → 87,13
wire [VCN-1:0][SCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;
wire [VCN-1:0][SCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;
wire [VCN-1:0][SCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;
wire [VCN-1:0][SCN-1:0] c2sa4, c2wa4, c2na4, c2ea4, c2la4;
`else
wire [VCN-1:0] s2c4, w2c4, n2c4, e2c4, l2c4;
wire [VCN-1:0] c2s4, c2w4, c2n4, c2e4, c2l4;
wire [VCN-1:0] s2ca, w2ca, n2ca, e2ca, l2ca;
wire [VCN-1:0] c2sa, c2wa, c2na, c2ea, c2la;
wire [VCN-1:0] c2sa4, c2wa4, c2na4, c2ea4, c2la4;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
 
// the requests/acks from/to input buffers to switch allocators

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