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  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc/branches
    from Rev 77 to Rev 78
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Rev 77 → Rev 78

/clos_opt/clos_opt/src/clos_buf.v
81,13 → 81,15
`ifdef ENABLE_CHANNEL_SLICING
wire [MN-1:0][SCN-1:0] sim4, wim4, nim4, eim4, lim4;
wire [MN-1:0][SCN-1:0] sima, wima, nima, eima, lima;
wire [MN-1:0][SCN-1:0] sima4, wima4, nima4, eima4, lima4;
wire [NN-1:0][SCN-1:0] soa4, woa4, noa4, eoa4, loa4;
wire [MN-1:0][4:0][SCN-1:0] cmo4;
wire [MN-1:0][4:0][SCN-1:0] cmo4, cmi4, cmia, cmoa, cmoa4;
`else
wire [MN-1:0] sim4, wim4, nim4, eim4, lim4;
wire [MN-1:0] sima, wima, nima, eima, lima;
wire [MN-1:0] sima4, wima4, nima4, eima4, lima4;
wire [NN-1:0] soa4, woa4, noa4, eoa4, loa4;
wire [MN-1:0][4:0] cmo4;
wire [MN-1:0][4:0] cmo4, cmi4, cmia, cmoa, cmoa4;
`endif // !`ifdef ENABLE_CHANNEL_SLICING
wire [MN-1:0][3:0] simdec, nimdec, limdec; // the routing requests
283,7 → 285,7
assign so2[i] = cmo2[i][0];
assign so3[i] = cmo3[i][0];
assign cmoa[i][0] = soa[i];
assign cmoa[i][0] = soa4[i];
assign cmoa4[i][0] = soa4[i];
assign wo0[i] = cmo0[i][1];
assign wo1[i] = cmo1[i][1];
290,7 → 292,7
assign wo2[i] = cmo2[i][1];
assign wo3[i] = cmo3[i][1];
assign cmoa[i][1] = woa[i];
assign cmoa[i][1] = woa4[i];
assign cmoa4[i][1] = woa4[i];
assign no0[i] = cmo0[i][2];
assign no1[i] = cmo1[i][2];
297,7 → 299,7
assign no2[i] = cmo2[i][2];
assign no3[i] = cmo3[i][2];
assign cmoa[i][2] = noa[i];
assign cmoa[i][2] = noa4[i];
assign cmoa4[i][2] = noa4[i];
assign eo0[i] = cmo0[i][3];
assign eo1[i] = cmo1[i][3];
304,7 → 306,7
assign eo2[i] = cmo2[i][3];
assign eo3[i] = cmo3[i][3];
assign cmoa[i][3] = eoa[i];
assign cmoa[i][3] = eoa4[i];
assign cmoa4[i][3] = eoa4[i];
assign lo0[i] = cmo0[i][4];
assign lo1[i] = cmo1[i][4];
311,7 → 313,7
assign lo2[i] = cmo2[i][4];
assign lo3[i] = cmo3[i][4];
assign cmoa[i][4] = loa[i];
assign cmoa[i][4] = loa4[i];
assign cmoa4[i][4] = loa4[i];
 
assign sims[i] = {cms[i][4],cms[i][3],cms[i][2],cms[i][1]};
assign wims[i] = {cms[i][4],cms[i][3]};
/clos_opt/clos_opt/src/cm.v
66,76 → 66,76
// data switch
dcb_xy #(.VCN(1), .VCW(DW))
CMDCB (
.sia ( dia[i][0] ),
.wia ( dia[i][1] ),
.nia ( dia[i][2] ),
.eia ( dia[i][3] ),
.lia ( dia[i][4] ),
.so0 ( do0[i][0] ),
.so1 ( do1[i][0] ),
.so2 ( do2[i][0] ),
.so3 ( do3[i][0] ),
.so4 ( do4[i][0] ),
.wo0 ( do0[i][1] ),
.wo1 ( do1[i][1] ),
.wo2 ( do2[i][1] ),
.wo3 ( do3[i][1] ),
.wo4 ( do4[i][1] ),
.no0 ( do0[i][2] ),
.no1 ( do1[i][2] ),
.no2 ( do2[i][2] ),
.no3 ( do3[i][2] ),
.no4 ( do4[i][2] ),
.eo0 ( do0[i][3] ),
.eo1 ( do1[i][3] ),
.eo2 ( do2[i][3] ),
.eo3 ( do3[i][3] ),
.eo4 ( do4[i][3] ),
.lo0 ( do0[i][4] ),
.lo1 ( do1[i][4] ),
.lo2 ( do2[i][4] ),
.lo3 ( do3[i][4] ),
.lo4 ( do4[i][4] ),
.si0 ( di0[i][0] ),
.si1 ( di1[i][0] ),
.si2 ( di2[i][0] ),
.si3 ( di3[i][0] ),
.si4 ( di4[i][0] ),
.wi0 ( di0[i][1] ),
.wi1 ( di1[i][1] ),
.wi2 ( di2[i][1] ),
.wi3 ( di3[i][1] ),
.wi4 ( di4[i][1] ),
.ni0 ( di0[i][2] ),
.ni1 ( di1[i][2] ),
.ni2 ( di2[i][2] ),
.ni3 ( di3[i][2] ),
.ni4 ( di4[i][2] ),
.ei0 ( di0[i][3] ),
.ei1 ( di1[i][3] ),
.ei2 ( di2[i][3] ),
.ei3 ( di3[i][3] ),
.ei4 ( di4[i][3] ),
.li0 ( di0[i][4] ),
.li1 ( di1[i][4] ),
.li2 ( di2[i][4] ),
.li3 ( di3[i][4] ),
.li4 ( di4[i][4] ),
.soa ( doa[i][0] ),
.woa ( doa[i][1] ),
.noa ( doa[i][2] ),
.eoa ( doa[i][3] ),
.loa ( doa[i][4] ),
.soa4 ( doa4[i][0] ),
.woa4 ( doa4[i][1] ),
.noa4 ( doa4[i][2] ),
.eoa4 ( doa4[i][3] ),
.loa4 ( doa4[i][4] ),
.wcfg ( wcfg[i] ),
.ecfg ( ecfg[i] ),
.lcfg ( lcfg[i] ),
.scfg ( scfg[i] ),
.ncfg ( ncfg[i] )
.sia ( dia[0] ),
.wia ( dia[1] ),
.nia ( dia[2] ),
.eia ( dia[3] ),
.lia ( dia[4] ),
.so0 ( do0[0] ),
.so1 ( do1[0] ),
.so2 ( do2[0] ),
.so3 ( do3[0] ),
.so4 ( do4[0] ),
.wo0 ( do0[1] ),
.wo1 ( do1[1] ),
.wo2 ( do2[1] ),
.wo3 ( do3[1] ),
.wo4 ( do4[1] ),
.no0 ( do0[2] ),
.no1 ( do1[2] ),
.no2 ( do2[2] ),
.no3 ( do3[2] ),
.no4 ( do4[2] ),
.eo0 ( do0[3] ),
.eo1 ( do1[3] ),
.eo2 ( do2[3] ),
.eo3 ( do3[3] ),
.eo4 ( do4[3] ),
.lo0 ( do0[4] ),
.lo1 ( do1[4] ),
.lo2 ( do2[4] ),
.lo3 ( do3[4] ),
.lo4 ( do4[4] ),
.si0 ( di0[0] ),
.si1 ( di1[0] ),
.si2 ( di2[0] ),
.si3 ( di3[0] ),
.si4 ( di4[0] ),
.wi0 ( di0[1] ),
.wi1 ( di1[1] ),
.wi2 ( di2[1] ),
.wi3 ( di3[1] ),
.wi4 ( di4[1] ),
.ni0 ( di0[2] ),
.ni1 ( di1[2] ),
.ni2 ( di2[2] ),
.ni3 ( di3[2] ),
.ni4 ( di4[2] ),
.ei0 ( di0[3] ),
.ei1 ( di1[3] ),
.ei2 ( di2[3] ),
.ei3 ( di3[3] ),
.ei4 ( di4[3] ),
.li0 ( di0[4] ),
.li1 ( di1[4] ),
.li2 ( di2[4] ),
.li3 ( di3[4] ),
.li4 ( di4[4] ),
.soa ( doa[0] ),
.woa ( doa[1] ),
.noa ( doa[2] ),
.eoa ( doa[3] ),
.loa ( doa[4] ),
.soa4 ( doa4[0] ),
.woa4 ( doa4[1] ),
.noa4 ( doa4[2] ),
.eoa4 ( doa4[3] ),
.loa4 ( doa4[4] ),
.wcfg ( wcfg ),
.ecfg ( ecfg ),
.lcfg ( lcfg ),
.scfg ( scfg ),
.ncfg ( ncfg )
);
 
// the allocator
/clos_opt/clos_opt/syn/script/source.tcl
20,6 → 20,7
analyze -format verilog ../../common/src/ctree.v
analyze -format sverilog ../../common/src/dcb.v
analyze -format sverilog ../../common/src/dcb_xy.v
analyze -format sverilog ../../common/src/cb.v
analyze -format sverilog ../../common/src/mnma.v
analyze -format sverilog ../../common/src/mrma.v
analyze -format verilog ../../common/src/mutex_arb.v
/clos_opt/clos_opt/syn/script/compile.tcl
15,7 → 15,7
# 31/05/2009 Initial version. <wsong83@gmail.com>
 
set rm_top router
set rm_para "VCN=>1, DW=>8, IPD=>1, OPD=>1"
set rm_para "VCN=>2, DW=>8, IPD=>1, OPD=>1"
 
# working directory
if {[file exists work ] && [file isdirectory work ]} {
/clos_opt/clos_opt/define.v
30,7 → 30,7
*/
 
// if VCN > 1, set ENABLE_CLOS to use the 2-stage Clos switch for less switching area
// `define ENABLE_CLOS
`define ENABLE_CLOS
 
// Using the asynchronous virsion of the Concurrent round-robine dispatching
// algorithm for the 2-stage Clos can save some area but introduce a 5%

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