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https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc/tags/v0.2/common/src
- from Rev 47 to Rev 56
- ↔ Reverse comparison
Rev 47 → Rev 56
/pipen.v
0,0 → 1,43
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
A single 4-phase 1-of-n pipeline stage. |
|
History: |
05/05/2009 Initial version. <wsong83@gmail.com> |
01/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module pipen(/*AUTOARG*/ |
// Outputs |
d_in_a, d_out, |
// Inputs |
d_in, d_out_a |
); |
|
parameter DW = 4; // the wire count, the "n" of the 1-of-n code |
|
input [DW-1:0] d_in; |
output d_in_a; |
output [DW-1:0] d_out; |
input d_out_a; |
|
genvar i; |
|
// the data pipe stage |
generate for (i=0; i<DW; i=i+1) begin:DD |
dc2 DC (.d(d_in[i]), .a(d_out_a), .q(d_out[i])); |
end endgenerate |
|
assign d_in_a = |d_out; |
|
endmodule // pipen |
/comp4.v
0,0 → 1,39
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
1-of-4 data comparator |
|
History: |
11/05/2010 Initial version. <wsong83@gmail.com> |
01/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module comp4 (/*AUTOARG*/ |
// Outputs |
q, |
// Inputs |
a, b |
); |
|
input [3:0] a, b; // the data inputs to be compared |
output [2:0] q; // the comparison result |
|
// a > b |
assign q[0] = (a[3]&(|b[2:0])) | (a[2]&(|b[1:0])) | (a[1]&(|b[0:0])); |
|
// a < b |
assign q[1] = (a[2]&(|b[3:3])) | (a[1]&(|b[3:2])) | (a[0]&(|b[3:1])); |
|
// a = b |
assign q[2] = (a[3]&b[3]) | (a[2]&b[2]) | (a[1]&b[1]) | (a[0]&b[0]); |
|
endmodule // comp4 |
/cell_lib.v
0,0 → 1,163
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
A synthesizable cell library for asynchronous circuis. |
Some cell are directly initialized to one of the Nangate 45nm cell lib. |
|
History: |
05/05/2009 Initial version. <wsong83@gmail.com> |
20/05/2011 Change to general verilog description for opensource. |
The Nangate cell library is used. <wsong83@gmail.com> |
01/06/2011 The bugs in the C2 and C2P1 gates are fixed. <wsong83@gmail.com> |
*/ |
|
// General 2-input C-element |
module c2 (a0, a1, q); |
|
input a0, a1; // two inputs |
output q; // output |
|
wire [2:0] m; // internal wires |
|
nand U1 (m[0], a0, a1); |
nand U2 (m[1], a0, q); |
nand U3 (m[2], a1, q); |
assign q = ~&m; |
|
endmodule |
|
// the 2-input C-element on data paths, different name for easy synthesis scription |
module dc2 (d, a, q); |
|
input d; // data input |
input a; // ack input |
output q; // data output |
|
wire [2:0] m; // internal wires |
|
nand U1 (m[0], a, d); |
nand U2 (m[1], d, q); |
nand U3 (m[2], a, q); |
assign q = ~&m; |
|
endmodule |
|
// 2-input C-element with a minus input |
module c2n (a, b, q); |
|
input a; // the normal input |
input b; // the minus input |
output q; // output |
|
wire m; // internal wire |
|
and U1 (m, b, q); |
or U2 (q, m, a); |
|
endmodule |
|
// 2-input C-element with a plus input |
module c2p (a, b, q); |
|
input a; // the normal input |
input b; // the plus input |
output q; // output |
|
wire m; // internal wire |
|
or U1 (m, b, q); |
and U2 (q, m, a); |
|
endmodule |
|
// 2-input MUTEX cell, Nangate |
module mutex2 ( a, b, qa, qb ); // !!! dont touch !!! |
|
input a, b; // request inputs |
output qa, qb; // grant outputs |
|
wire qan, qbn; // internal wires |
|
NAND2_X2 U1 ( .A1(a), .A2(qbn), .ZN(qan) ); // different driving strength for fast convergence |
NOR3_X2 U2 ( .A1(qbn), .A2(qbn), .A3(qbn), .ZN(qb) ); // pulse filter |
NOR3_X2 U3 ( .A1(qan), .A2(qan), .A3(qan), .ZN(qa) ); // pulse filter |
NAND2_X1 U4 ( .A1(b), .A2(qan), .ZN(qbn) ); |
|
endmodule |
|
// 3-input C-element with a plus input |
module c2p1 (a0, a1, b, q); |
|
input a0, a1; // normal inputs |
input b; // plus input |
output q; // output |
|
wire [2:0] m; // internal wires |
|
nand U1 (m[0], a0, a1, b); |
nand U2 (m[1], a0, q); |
nand U3 (m[2], a1, q); |
assign q = ~&m; |
|
endmodule |
|
// the basic element of a tree arbiter |
module tarb ( ngnt, ntgnt, req, treq ); |
|
input [1:0] req; // request input |
output [1:0] ngnt; // the negative grant output |
output treq; // combined request output |
input ntgnt; // the negative combined grant input |
|
wire n1, n2; // internal wires |
wire [1:0] mgnt; // outputs of the MUTEX |
|
mutex2 ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) ); |
c2n C0 ( .a(ntgnt), .b(n2), .q(ngnt[0]) ); |
c2n C1 ( .a(ntgnt), .b(n1), .q(ngnt[1]) ); |
nand U1 (treq, n1, n2); |
nand U2 (n1, ngnt[0], mgnt[1]); |
nand U3 (n2, ngnt[1], mgnt[0]); |
endmodule |
|
// the tile in a multi-resource arbiter |
module cr_blk ( bo, hs, cbi, rbi, rg, cg ); |
|
input rg, cg; // input requests |
input cbi, rbi; // input blockage |
output bo; // output blockage |
output hs; // match result |
|
wire blk; // internal wire |
|
c2p1 XG ( .a0(rg), .a1(cg), .b(blk), .q(bo) ); |
c2p1 HG ( .a0(cbi), .a1(rbi), .b(bo), .q(hs) ); |
nor U1 (blk, rbi, cbi); |
|
endmodule |
|
// a data latch template, Nangate |
module dlatch ( q, qb, d, g); |
output q, qb; |
input d, g; |
|
DLH_X1 U1 (.Q(q), .D(d), .G(g)); |
endmodule |
|
// a delay line, Nangate |
module delay (q, a); |
input a; |
output q; |
|
BUF_X2 U (.Z(q), .A(a)); |
endmodule |
|
|
/mrma.v
0,0 → 1,112
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Multi-resource match arbiter |
*** SystemVerilog is used *** |
|
References |
Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Multi-resource arbiter decomposition, Tech report NCL-EECE-MSD-TR-2009-143, Microelectronic System Design Group, School of EECE, Newcastle University, 2009. |
Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009. |
|
History: |
05/09/2009 Initial version. <wsong83@gmail.com> |
05/11/2009 Speed up the arbiter. <wsong83@gmail.com> |
27/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module mrma (/*AUTOARG*/ |
// Outputs |
ca, ra, cfg, |
// Inputs |
c, r, rst_n |
); |
|
// parameters |
parameter N = 2; // the number of requests/clients |
parameter M = 2; // the number of resources |
|
input [N-1:0] c; // requests/clients |
output [N-1:0] ca; // requests ack |
|
input [M-1:0] r; // resources |
output [M-1:0] ra; // resource ack |
|
output [M-1:0][N-1:0] cfg; // the generated configuration |
wire [N-1:0][M-1:0] scfg; |
|
wire [M-1:0][N-1:0] hs; // match results |
wire [M-1:0][N-1:0] blk; // blockage |
wire [N-1:0][M-1:0] sblk; // shuffled blockage |
wire [M-1:0] rbi; // resource blockage |
wire [N-1:0] cbi; // client blockage |
wire [N-1:0] cg, cm; // client requests |
wire [M-1:0] rg, rm; // resource requests |
|
input rst_n; // active low reset |
|
// generate variables |
genvar i, j; |
|
|
// input arbiters |
tree_arb #(N) CIArb ( |
.req ( cm ), |
.gnt ( cg ) |
); |
|
tree_arb #(M) RIArb ( |
.req ( rm ), |
.gnt ( rg ) |
); |
|
generate |
// tile matrix |
for (i=0; i<M; i++) begin: Row |
for(j=0; j<N; j++) begin: Clm |
cr_blk E ( |
.bo ( blk[i][j] ), |
.hs ( hs[i][j] ), |
.cbi ( cbi[j] ), |
.rbi ( rbi[i] ), |
.rg ( rg[i] ), |
.cg ( cg[j] ) |
); |
|
// shuffle the blockage |
assign sblk[j][i] = blk[i][j]; |
|
// shuffle the configuration |
assign scfg[j][i] = cfg[i][j]; |
|
// store the match results |
c2p C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j])); |
|
end // block: Clm |
end // block: Row |
|
// combine the row blockage and generate input requests |
for(i=0; i<M; i++) begin: RB |
assign rbi[i] = (|blk[i]) & rst_n; |
and AND_RG (rm[i], r[i], ~ra[i], rst_n); |
assign ra[i] = |cfg[i]; |
end |
|
// combine the column blockage and generate input requests |
for(j=0; j<N; j++) begin: CB |
assign cbi[j] = (|sblk[j]) & rst_n; |
and AND_CG (cm[j], c[j], ~ca[j], rst_n); |
assign ca[j] = |scfg[j]; |
end |
endgenerate |
|
endmodule // mrma |
|
/pipe4.v
0,0 → 1,75
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
General pipeline stage using the 4-phase 1-of-4 QDI protocol. |
*** SystemVerilog is used *** |
|
History: |
05/05/2009 Initial version. <wsong83@gmail.com> |
17/04/2011 Replace the common ack generation. <wsong83@gmail.com> |
26/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module pipe4(/*AUTOARG*/ |
// Outputs |
ia, o0, o1, o2, o3, |
// Inputs |
i0, i1, i2, i3, oa |
`ifdef ENABLE_EOF |
, i4, o4 |
`endif |
); |
|
parameter DW = 32; // the data width of the pipeline stage |
parameter SCN = DW/2; // the number of 1-of-4 sub-stage required |
|
input [SCN-1:0] i0, i1, i2, i3; |
output [SCN-1:0] o0, o1, o2, o3; |
input oa; // input ack |
output ia; // output ack |
|
`ifdef ENABLE_EOF |
output o4; // the eof bit |
input i4; |
`endif |
|
// internal signals |
wire [SCN-1:0] tack; |
|
// generate the ack line |
genvar i; |
|
// the data pipe stage |
generate for (i=0; i<SCN; i++) begin:DD |
dc2 DC0 (.d(i0[i]), .a(oa), .q(o0[i])); |
dc2 DC1 (.d(i1[i]), .a(oa), .q(o1[i])); |
dc2 DC2 (.d(i2[i]), .a(oa), .q(o2[i])); |
dc2 DC3 (.d(i3[i]), .a(oa), .q(o3[i])); |
end endgenerate |
|
// the eof bit |
`ifdef ENABLE_EOF |
dc2 DD_DC4 (.d(i4), .a(oa), .q(o4)); |
`endif |
|
// generate the input ack |
assign tack = o0|o1|o2|o3; |
ctree #(.DW(SCN)) ACKT (.ci(tack), .co(ia)); |
|
endmodule // pipe4 |
|
|
|
|
/tree_arb.v
0,0 → 1,106
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
M-to-1 asynchronous tree arbiter. |
|
History: |
03/09/2009 Initial version. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module tree_arb (/*AUTOARG*/ |
// Outputs |
gnt, |
// Inputs |
req |
) ; |
|
// parameters |
parameter MR = 2; // the number of request inputs |
localparam TrLev = mlog2(MR)-1; // the number of levels of the tree |
input [MR-1:0] req; // the request input |
output [MR-1:0] gnt; // the grant output |
|
// generate variables |
genvar i, j, k; |
|
// internal wires |
wire [MR*2:0] mreq; // the internal request lines |
wire [MR*2:0] mgnt; // the internal gnt lines |
wire [1:0] rgnt; // the positive gnt of the root mutex |
|
// the hardware block |
generate |
if (MR == 1) // special case: only one input |
begin: MA_1 |
assign gnt = req; |
end |
else if(MR == 2) // special case: only two input |
begin: MA_2 |
mutex2 ME0 ( |
.a ( req[0] ), |
.b ( req[1] ), |
.qa ( gnt[0] ), |
.qb ( gnt[1] ) |
); |
end |
else |
begin: MA_N |
|
mutex2 ME0 ( |
.a ( mreq[0] ), |
.b ( mreq[1] ), |
.qa ( rgnt[0] ), |
.qb ( rgnt[1] ) |
); |
|
assign mgnt[1:0] = ~rgnt; |
|
for (i=1; 2**(i+1)<MR; i=i+1) begin: L |
for (j=0; j<2**i; j=j+1) begin: T |
tarb TA ( |
.ngnt ( mgnt[(2**i-1)*2+j*2+1:(2**i-1)*2+j*2] ), |
.ntgnt ( mgnt[(2**(i-1)-1)*2+j] ), |
.req ( mreq[(2**i-1)*2+j*2+1:(2**i-1)*2+j*2] ), |
.treq ( mreq[(2**(i-1)-1)*2+j] ) |
); |
end |
end |
|
for (j=0; j<MR-(2**TrLev); j=j+1) begin: LF |
tarb TA ( |
.ngnt ( mgnt[(2**TrLev-1)*2+j*2+1:(2**TrLev-1)*2+j*2] ), |
.ntgnt ( mgnt[(2**(TrLev-1)-1)*2+j] ), |
.req ( mreq[(2**TrLev-1)*2+j*2+1:(2**TrLev-1)*2+j*2] ), |
.treq ( mreq[(2**(TrLev-1)-1)*2+j] ) |
); |
end |
|
assign gnt = ~(mgnt[2*MR-3:MR-2]); |
assign mreq[2*MR-3:MR-2] = req; |
|
end |
endgenerate |
|
// log_2 function |
function integer mlog2; |
input integer MR; |
begin |
for( mlog2 = 0; 2**mlog2<MR; mlog2=mlog2+1) |
begin |
end |
end |
endfunction // mlog2 |
|
endmodule // tree_arb |
|
|
/mutex_arb.v
0,0 → 1,48
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
M-to-1 asynchronous multi-way MUTEX arbiter. |
|
History: |
24/05/2009 Initial version. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module mutex_arb (/*AUTOARG*/ |
// Outputs |
gnt, |
// Inputs |
req |
); |
|
parameter wd = 4; // the number of request inputs |
|
input [wd-1:0] req; |
output [wd-1:0] gnt; |
|
genvar i,j; |
|
wire [wd-1:0] arb_w [wd-1:0]; |
wire [wd-1:0] gnt; |
|
generate |
for(i=0; i<wd; i=i+1) begin:lv |
for(j=i+1; j<wd; j=j+1) begin:b |
mutex2 ME ( .a(arb_w[i][j-1]), .b(arb_w[j][i]), .qa(arb_w[i][j]), .qb(arb_w[j][i+1])); |
end |
assign arb_w[i][0] = req[i]; |
assign gnt[i] = arb_w[i][wd-1]; |
end |
endgenerate |
|
endmodule // mutex_arb |
|
/rcb.v
0,0 → 1,73
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Request crossbar for wormhole and SDM routers. |
*** SystemVerilog is used *** |
|
History: |
10/12/2009 Initial version. <wsong83@gmail.com> |
23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com> |
27/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module rcb (/*AUTOARG*/ |
// Outputs |
ira, oreq, |
// Inputs |
ireq, ora, cfg |
) ; |
// parameters |
parameter NN = 1; // number of input ports |
parameter MN = 1; // number of output ports |
parameter DW = 1; // datawidth a port |
|
input [NN-1:0][DW-1:0] ireq; // input requests |
output [NN-1:0] ira; // ack for input requests |
output [MN-1:0][DW-1:0] oreq; // output requests |
input [MN-1:0] ora; // ack for output requests |
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration |
|
wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for requests |
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks |
|
// generate variable |
genvar i, j, k; |
|
// request matrix |
generate |
for (i=0; i<MN; i++) begin: EN |
for (j=0; j<DW; j++) begin: SC |
for (k=0; k<NN; k++) begin: IP |
and AC (m[i][j][k], ireq[k][j], cfg[i][k]); |
end |
|
// the OR gates |
assign oreq[i][j] = |m[i][j]; |
end |
end |
endgenerate |
|
// ack matrix |
generate |
for (k=0; k<NN; k++) begin: ENA |
for (i=0; i<MN; i++) begin: OP |
and AC (ma[k][i], ora[i], cfg[i][k]); |
end |
|
// the OR gates |
assign ira[k] = |ma[k]; |
end |
endgenerate |
|
endmodule // rcb |
|
|
/mnma.v
0,0 → 1,96
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
M-N Match allocator |
*** SystemVerilog is used *** |
|
References |
Thomas E. Anderson, Susan S. Owicki, James B. Saxe and Charles P. Thacker, High-speed switch scheduling for local-area networks, ACM Transactions on Computer Systems, 1993(11), 319-352. |
|
For the detail structure, please refer to Section 6.3.1 of the thesis: |
Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011. |
|
History: |
09/06/2010 Initial version. <wsong83@gmail.com> |
08/03/2011 Tree arbiter cannot be used as the requests are not allowed to drop before ack. <wsong83@gmail.com> |
24/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
module mnma(/*AUTOARG*/ |
// Outputs |
ra, cfg, |
// Inputs |
r |
); |
parameter N = 2; // number of input requests |
parameter M = 2; // number of resources |
|
input [N-1:0][M-1:0] r; // input requests |
output [N-1:0] ra; // ack to input requests |
output [M-1:0][N-1:0] cfg; // configuration to the crssbar |
|
wire [M-1:0][N-1:0] OPr; |
wire [M-1:0][N-1:0] OPg; |
wire [M-1:0][N-1:0][M-1:0] OPren; |
wire [N-1:0][M-1:0] IPr; |
wire [N-1:0][M-1:0] IPg; |
|
genvar i,j,k; |
|
//------------------------------------- |
// OP arbiters |
generate |
for(i=0; i<M; i++) begin:OPA |
mutex_arb #(N) |
A ( |
.req ( OPr[i] ), |
.gnt ( OPg[i] ) |
); |
end |
endgenerate |
|
//-------------------------------------- |
// IP arbiters |
generate |
for(i=0; i<N; i++) begin:IPA |
mutex_arb #(M) |
A ( |
.req ( IPr[i] ), |
.gnt ( IPg[i] ) |
); |
|
// the input ack |
assign ra[i] = |IPg[i]; |
end |
endgenerate |
|
//-------------------------------------- |
// connections |
generate |
for(i=0; i<M; i++) begin:CO |
for(j=0; j<N; j++) begin:CI |
for(k=0; k<M; k++) begin:EN |
if(i==k) |
assign OPren[i][j][k] = 1'b0; |
else |
assign OPren[i][j][k] = IPg[j][k]; // connection j->k is settle |
end |
and AND_OPRen (OPr[i][j], r[j][i] ,(~|OPren[i][j])); |
assign cfg[i][j] = IPg[j][i]; |
assign IPr[j][i] = OPg[i][j]; |
end // block: CI |
end // block: CO |
endgenerate |
|
endmodule // mnma |
|
|
/dclos.v
0,0 → 1,345
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Data Clos network. |
*** SystemVerilog is used *** |
|
History: |
17/07/2010 Initial version. <wsong83@gmail.com> |
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module dclos (/*AUTOARG*/ |
// Outputs |
so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, |
eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia, |
wia, nia, eia, lia, |
// Inputs |
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, |
ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa, |
woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg |
); |
|
parameter MN = 2; // number of CMs |
parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits |
parameter DW = 8; // datawidth of a single virtual circuit/port |
parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port |
|
input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1 |
input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1 |
input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1 |
input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1 |
input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input |
output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output |
output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output |
output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output |
output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output |
output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output |
|
// eof bits and ack lines |
`ifdef ENABLE_CHANNEL_SLICING |
input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4; |
output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4; |
output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia; |
input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa; |
`else |
input [NN-1:0] si4, wi4, ni4, ei4, li4; |
output [NN-1:0] so4, wo4, no4, eo4, lo4; |
output [NN-1:0] sia, wia, nia, eia, lia; |
input [NN-1:0] soa, woa, noa, eoa, loa; |
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs |
// configuration for CMs |
input [MN-1:0][1:0] scfg, ncfg; |
input [MN-1:0][3:0] wcfg, ecfg, lcfg; |
// no OMs |
|
// output of IMs |
wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3; |
wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3; |
wire [MN-1:0][SCN-1:0] imon0, imon1, imon2, imon3; |
wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3; |
wire [MN-1:0][SCN-1:0] imol0, imol1, imol2, imol3; |
`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4; |
wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola; |
`else |
wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4; |
wire [MN-1:0] imosa, imowa, imona, imoea, imola; |
`endif |
|
// input of CMs |
wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3; |
`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia; |
`else |
wire [MN-1:0][4:0] cmi4, cmia; |
`endif |
|
// output of CMs |
wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3; |
`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa; |
`else |
wire [MN-1:0][4:0] cmo4, cmoa; |
`endif |
|
genvar i,j,k; |
|
dcb #(.NN(NN), .MN(MN), .DW(DW)) |
SIM ( |
.o0 ( imos0 ), |
.o1 ( imos1 ), |
.o2 ( imos2 ), |
.o3 ( imos3 ), |
.o4 ( imos4 ), |
.ia ( sia ), |
.i0 ( si0 ), |
.i1 ( si1 ), |
.i2 ( si2 ), |
.i3 ( si3 ), |
.i4 ( si4 ), |
.oa ( imosa ), |
.cfg ( imcfg[0] ) |
); |
|
dcb #(.NN(NN), .MN(MN), .DW(DW)) |
WIM ( |
.o0 ( imow0 ), |
.o1 ( imow1 ), |
.o2 ( imow2 ), |
.o3 ( imow3 ), |
.o4 ( imow4 ), |
.ia ( wia ), |
.i0 ( wi0 ), |
.i1 ( wi1 ), |
.i2 ( wi2 ), |
.i3 ( wi3 ), |
.i4 ( wi4 ), |
.oa ( imowa ), |
.cfg ( imcfg[1] ) |
); |
|
dcb #(.NN(NN), .MN(MN), .DW(DW)) |
NIM ( |
.o0 ( imon0 ), |
.o1 ( imon1 ), |
.o2 ( imon2 ), |
.o3 ( imon3 ), |
.o4 ( imon4 ), |
.ia ( nia ), |
.i0 ( ni0 ), |
.i1 ( ni1 ), |
.i2 ( ni2 ), |
.i3 ( ni3 ), |
.i4 ( ni4 ), |
.oa ( imona ), |
.cfg ( imcfg[2] ) |
); |
|
dcb #(.NN(NN), .MN(MN), .DW(DW)) |
EIM ( |
.o0 ( imoe0 ), |
.o1 ( imoe1 ), |
.o2 ( imoe2 ), |
.o3 ( imoe3 ), |
.o4 ( imoe4 ), |
.ia ( eia ), |
.i0 ( ei0 ), |
.i1 ( ei1 ), |
.i2 ( ei2 ), |
.i3 ( ei3 ), |
.i4 ( ei4 ), |
.oa ( imoea ), |
.cfg ( imcfg[3] ) |
); |
|
dcb #(.NN(NN), .MN(MN), .DW(DW)) |
LIM ( |
.o0 ( imol0 ), |
.o1 ( imol1 ), |
.o2 ( imol2 ), |
.o3 ( imol3 ), |
.o4 ( imol4 ), |
.ia ( lia ), |
.i0 ( li0 ), |
.i1 ( li1 ), |
.i2 ( li2 ), |
.i3 ( li3 ), |
.i4 ( li4 ), |
.oa ( imola ), |
.cfg ( imcfg[4] ) |
); |
|
generate for(i=0; i<MN; i++) begin: IMSHF |
// shuffle the interconnects between IMs and CMs |
assign cmi0[i][0] = imos0[i]; |
assign cmi1[i][0] = imos1[i]; |
assign cmi2[i][0] = imos2[i]; |
assign cmi3[i][0] = imos3[i]; |
assign cmi4[i][0] = imos4[i]; |
assign imosa[i] = cmia[i][0]; |
|
assign cmi0[i][1] = imow0[i]; |
assign cmi1[i][1] = imow1[i]; |
assign cmi2[i][1] = imow2[i]; |
assign cmi3[i][1] = imow3[i]; |
assign cmi4[i][1] = imow4[i]; |
assign imowa[i] = cmia[i][1]; |
|
assign cmi0[i][2] = imon0[i]; |
assign cmi1[i][2] = imon1[i]; |
assign cmi2[i][2] = imon2[i]; |
assign cmi3[i][2] = imon3[i]; |
assign cmi4[i][2] = imon4[i]; |
assign imona[i] = cmia[i][2]; |
|
assign cmi0[i][3] = imoe0[i]; |
assign cmi1[i][3] = imoe1[i]; |
assign cmi2[i][3] = imoe2[i]; |
assign cmi3[i][3] = imoe3[i]; |
assign cmi4[i][3] = imoe4[i]; |
assign imoea[i] = cmia[i][3]; |
|
assign cmi0[i][4] = imol0[i]; |
assign cmi1[i][4] = imol1[i]; |
assign cmi2[i][4] = imol2[i]; |
assign cmi3[i][4] = imol3[i]; |
assign cmi4[i][4] = imol4[i]; |
assign imola[i] = cmia[i][4]; |
|
// CM modules |
dcb_xy #(.VCN(1), .VCW(DW)) |
CM ( |
.sia ( cmia[i][0] ), |
.wia ( cmia[i][1] ), |
.nia ( cmia[i][2] ), |
.eia ( cmia[i][3] ), |
.lia ( cmia[i][4] ), |
.so0 ( cmo0[i][0] ), |
.so1 ( cmo1[i][0] ), |
.so2 ( cmo2[i][0] ), |
.so3 ( cmo3[i][0] ), |
.so4 ( cmo4[i][0] ), |
.wo0 ( cmo0[i][1] ), |
.wo1 ( cmo1[i][1] ), |
.wo2 ( cmo2[i][1] ), |
.wo3 ( cmo3[i][1] ), |
.wo4 ( cmo4[i][1] ) , |
.no0 ( cmo0[i][2] ), |
.no1 ( cmo1[i][2] ), |
.no2 ( cmo2[i][2] ), |
.no3 ( cmo3[i][2] ), |
.no4 ( cmo4[i][2] ), |
.eo0 ( cmo0[i][3] ), |
.eo1 ( cmo1[i][3] ), |
.eo2 ( cmo2[i][3] ), |
.eo3 ( cmo3[i][3] ), |
.eo4 ( cmo4[i][3] ), |
.lo0 ( cmo0[i][4] ), |
.lo1 ( cmo1[i][4] ), |
.lo2 ( cmo2[i][4] ), |
.lo3 ( cmo3[i][4] ), |
.lo4 ( cmo4[i][4] ), |
.si0 ( cmi0[i][0] ), |
.si1 ( cmi1[i][0] ), |
.si2 ( cmi2[i][0] ), |
.si3 ( cmi3[i][0] ), |
.si4 ( cmi4[i][0] ), |
.wi0 ( cmi0[i][1] ), |
.wi1 ( cmi1[i][1] ), |
.wi2 ( cmi2[i][1] ), |
.wi3 ( cmi3[i][1] ), |
.wi4 ( cmi4[i][1] ), |
.ni0 ( cmi0[i][2] ), |
.ni1 ( cmi1[i][2] ), |
.ni2 ( cmi2[i][2] ), |
.ni3 ( cmi3[i][2] ), |
.ni4 ( cmi4[i][2] ), |
.ei0 ( cmi0[i][3] ), |
.ei1 ( cmi1[i][3] ), |
.ei2 ( cmi2[i][3] ), |
.ei3 ( cmi3[i][3] ), |
.ei4 ( cmi4[i][3] ), |
.li0 ( cmi0[i][4] ), |
.li1 ( cmi1[i][4] ), |
.li2 ( cmi2[i][4] ), |
.li3 ( cmi3[i][4] ), |
.li4 ( cmi4[i][4] ), |
.soa ( cmoa[i][0] ), |
.woa ( cmoa[i][1] ), |
.noa ( cmoa[i][2] ), |
.eoa ( cmoa[i][3] ), |
.loa ( cmoa[i][4] ), |
.wcfg ( wcfg[i] ), |
.ecfg ( ecfg[i] ), |
.lcfg ( lcfg[i] ), |
.scfg ( scfg[i] ), |
.ncfg ( ncfg[i] ) |
); |
|
// shuffle between CMs and OMs(OPs) |
assign so0[i] = cmo0[i][0]; |
assign so1[i] = cmo1[i][0]; |
assign so2[i] = cmo2[i][0]; |
assign so3[i] = cmo3[i][0]; |
assign so4[i] = cmo4[i][0]; |
assign cmoa[i][0] = soa[i]; |
|
assign wo0[i] = cmo0[i][1]; |
assign wo1[i] = cmo1[i][1]; |
assign wo2[i] = cmo2[i][1]; |
assign wo3[i] = cmo3[i][1]; |
assign wo4[i] = cmo4[i][1]; |
assign cmoa[i][1] = woa[i]; |
|
assign no0[i] = cmo0[i][2]; |
assign no1[i] = cmo1[i][2]; |
assign no2[i] = cmo2[i][2]; |
assign no3[i] = cmo3[i][2]; |
assign no4[i] = cmo4[i][2]; |
assign cmoa[i][2] = noa[i]; |
|
assign eo0[i] = cmo0[i][3]; |
assign eo1[i] = cmo1[i][3]; |
assign eo2[i] = cmo2[i][3]; |
assign eo3[i] = cmo3[i][3]; |
assign eo4[i] = cmo4[i][3]; |
assign cmoa[i][3] = eoa[i]; |
|
assign lo0[i] = cmo0[i][4]; |
assign lo1[i] = cmo1[i][4]; |
assign lo2[i] = cmo2[i][4]; |
assign lo3[i] = cmo3[i][4]; |
assign lo4[i] = cmo4[i][4]; |
assign cmoa[i][4] = loa[i]; |
end // block: IMSHF |
|
endgenerate |
|
|
endmodule // dclos |
|
|
|
|
|
|
|
|
|
|
/dcb.v
0,0 → 1,113
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Data crossbar for wormhole and SDM routers. |
*** SystemVerilog is used *** |
|
History: |
17/07/2010 Initial version. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module dcb (/*AUTOARG*/ |
// Outputs |
o0, o1, o2, o3, ia, o4, |
// Inputs |
i0, i1, i2, i3, oa, i4, cfg |
); |
|
parameter NN = 2; // number of input ports |
parameter MN = 3; // number of output ports |
parameter DW = 8; // data-width of a port |
parameter SCN = DW/2; // number of 1-of-4 sub-channels for one port |
|
input [NN-1:0][SCN-1:0] i0, i1, i2, i3; // input ports |
output [MN-1:0][SCN-1:0] o0, o1, o2, o3; // output ports |
|
`ifdef ENABLE_CHANNEL_SLICING |
output [NN-1:0][SCN-1:0] ia, o4; // eof and ack |
input [MN-1:0][SCN-1:0] oa, i4; |
`else |
output [NN-1:0] ia, o4; // eof and ack |
input [MN-1:0] oa, i4; |
`endif |
|
input [MN-1:0][NN-1:0] cfg; // crossbar configuration |
|
wire [MN-1:0][SCN-1:0][NN-1:0] dm0, dm1, dm2, dm3; |
|
`ifdef ENABLE_CHANNEL_SLICING |
wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4; |
`else |
wire [NN-1:0][MN-1:0] am, dm4; |
`endif |
|
genvar i, j, k; |
|
generate |
for(i=0; i<MN; i++) begin: EN |
for(j=0; j<NN; j++) begin: IP |
for(k=0; k<SCN; k++) begin: SC |
and A0 (dm0[i][k][j], i0[j][k], cfg[i][j]); |
and A1 (dm1[i][k][j], i1[j][k], cfg[i][j]); |
and A2 (dm2[i][k][j], i2[j][k], cfg[i][j]); |
and A3 (dm3[i][k][j], i3[j][k], cfg[i][j]); |
`ifdef ENABLE_CHANNEL_SLICING |
and A4 (dm4[i][k][j], i4[j][k], cfg[i][j]); |
and Aa (am[j][k][i], oa[i][k], cfg[i][j]); |
`endif |
end |
|
`ifndef ENABLE_CHANNEL_SLICING |
and A4 (dm4[i][j], i4[j], cfg[i][j]); |
and Aa (am[j][i], oa[i], cfg[i][j]); |
`endif |
end // block: IP |
end // block: EN |
endgenerate |
|
generate |
for(i=0; i<MN; i++) begin: ORTD |
for(j=0; j<SCN; j++) begin: OP |
assign o0[i][j] = |dm0[i][j]; |
assign o1[i][j] = |dm1[i][j]; |
assign o2[i][j] = |dm2[i][j]; |
assign o3[i][j] = |dm3[i][j]; |
`ifdef ENABLE_CHANNEL_SLICING |
assign o4[i][j] = |dm4[i][j]; |
`endif |
end |
|
`ifndef ENABLE_CHANNEL_SLICING |
assign o4[i] = |dm4[i]; |
`endif |
|
end // block: ORTD |
endgenerate |
|
generate |
for(i=0; i<NN; i++) begin: ORTA |
`ifdef ENABLE_CHANNEL_SLICING |
for(j=0; j<SCN; j++) begin: IP |
assign ia[i][j] = |am[i][j]; |
end |
`else |
assign ia[i] = |am[i]; |
`endif |
end |
endgenerate |
|
endmodule // dcb |
|
/dcb_xy.v
0,0 → 1,443
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Data crossbar for wormhole and SDM routers. |
Optimized by removing disabled turn models according to the XY routing algorithm. |
*** SystemVerilog is used *** |
|
History: |
21/08/2009 Initial version. <wsong83@gmail.com> |
20/09/2010 Supporting channel slicing and SDM using macro difinitions. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module dcb_xy (/*AUTOARG*/ |
// Outputs |
so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, |
eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, sia, wo4, wia, no4, nia, |
eo4, eia, lo4, lia, |
// Inputs |
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, |
ei1, ei2, ei3, li0, li1, li2, li3, si4, soa, wi4, woa, ni4, noa, |
ei4, eoa, li4, loa, scfg, ncfg, wcfg, ecfg, lcfg |
) ; |
|
parameter VCN = 1; // number of virtual circuits per port |
parameter VCW = 8; // the datawidth of a single virtual circuit |
parameter SCN = VCW/2; // number of 1-of-4 sub-channels in one virtual circuit |
|
input [VCN-1:0][SCN-1:0] si0, si1, si2, si3; // south input, X+1 |
output [VCN-1:0][SCN-1:0] so0, so1, so2, so3; // south output |
input [VCN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input, Y-1 |
output [VCN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output |
input [VCN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input, X-1 |
output [VCN-1:0][SCN-1:0] no0, no1, no2, no3; // north output |
input [VCN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input, Y+1 |
output [VCN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output |
input [VCN-1:0][SCN-1:0] li0, li1, li2, li3; // local input |
output [VCN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output |
|
// ack and eof bits |
`ifdef ENABLE_CHANNEL_SLICING |
input [VCN-1:0][SCN-1:0] si4, soa; |
output [VCN-1:0][SCN-1:0] so4, sia; |
input [VCN-1:0][SCN-1:0] wi4, woa; |
output [VCN-1:0][SCN-1:0] wo4, wia; |
input [VCN-1:0][SCN-1:0] ni4, noa; |
output [VCN-1:0][SCN-1:0] no4, nia; |
input [VCN-1:0][SCN-1:0] ei4, eoa; |
output [VCN-1:0][SCN-1:0] eo4, eia; |
input [VCN-1:0][SCN-1:0] li4, loa; |
output [VCN-1:0][SCN-1:0] lo4, lia; |
`else // !`ifdef ENABLE_CHANNEL_SLICING |
input [VCN-1:0] si4, soa; |
output [VCN-1:0] so4, sia; |
input [VCN-1:0] wi4, woa; |
output [VCN-1:0] wo4, wia; |
input [VCN-1:0] ni4, noa; |
output [VCN-1:0] no4, nia; |
input [VCN-1:0] ei4, eoa; |
output [VCN-1:0] eo4, eia; |
input [VCN-1:0] li4, loa; |
output [VCN-1:0] lo4, lia; |
`endif |
|
// configurations |
input [VCN-1:0][1:0][VCN-1:0] scfg, ncfg; |
input [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; |
|
|
// ANDed wires |
wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos0, tos1, tos2, tos3; // the wires to the south output port |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow0, tow1, tow2, tow3; // the wires to the west output port |
wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton0, ton1, ton2, ton3; // the wires to the north output port |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe0, toe1, toe2, toe3; // the wires to the east output port |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol0, tol1, tol2, tol3; // the wires to the local output port |
|
`ifdef ENABLE_CHANNEL_SLICING |
wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos4, tosa; // the wires to the south output port |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow4, towa; // the wires to the west output port |
wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton4, tona; // the wires to the north output port |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe4, toea; // the wires to the east output port |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol4, tola; // the wires to the local output port |
|
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] isa; // ack back to south |
wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iwa; // ack back to west |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ina; // ack back to north |
wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iea; // ack back to east |
wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ila; // ack back to local |
|
`else // !`ifdef ENABLE_CHANNEL_SLICING |
wire [VCN-1:0][1:0][VCN-1:0] tos4, tosa; // the wires to the south output port |
wire [VCN-1:0][3:0][VCN-1:0] tow4, towa; // the wires to the west output port |
wire [VCN-1:0][1:0][VCN-1:0] ton4, tona; // the wires to the north output port |
wire [VCN-1:0][3:0][VCN-1:0] toe4, toea; // the wires to the east output port |
wire [VCN-1:0][3:0][VCN-1:0] tol4, tola; // the wires to the local output port |
|
wire [VCN-1:0][3:0][VCN-1:0] isa; // ack back to south |
wire [VCN-1:0][1:0][VCN-1:0] iwa; // ack back to west |
wire [VCN-1:0][3:0][VCN-1:0] ina; // ack back to north |
wire [VCN-1:0][1:0][VCN-1:0] iea; // ack back to east |
wire [VCN-1:0][3:0][VCN-1:0] ila; // ack back to local |
|
`endif // !`ifdef ENABLE_CHANNEL_SLICING |
|
// generate |
genvar i, j, k; |
|
|
/*---------------------------- SOUTH OUPUT -------------------------------------*/ |
generate for (i=0; i<VCN; i=i+1) |
begin:SOP |
for(j=0; j<VCN; j++) begin: V |
for(k=0; k<SCN; k++) begin: SC |
and AN0 (tos0[i][k][0][j], ni0[j][k], scfg[i][0][j]); |
and AN1 (tos1[i][k][0][j], ni1[j][k], scfg[i][0][j]); |
and AN2 (tos2[i][k][0][j], ni2[j][k], scfg[i][0][j]); |
and AN3 (tos3[i][k][0][j], ni3[j][k], scfg[i][0][j]); |
and AL0 (tos0[i][k][1][j], li0[j][k], scfg[i][1][j]); |
and AL1 (tos1[i][k][1][j], li1[j][k], scfg[i][1][j]); |
and AL2 (tos2[i][k][1][j], li2[j][k], scfg[i][1][j]); |
and AL3 (tos3[i][k][1][j], li3[j][k], scfg[i][1][j]); |
`ifdef ENABLE_CHANNEL_SLICING |
and AN4 (tos4[i][k][0][j], ni4[j][k], scfg[i][0][j]); |
and ANA (tosa[i][k][0][j], soa[i][k], scfg[i][0][j]); |
and AL4 (tos4[i][k][1][j], li4[j][k], scfg[i][1][j]); |
and ALA (tosa[i][k][1][j], soa[i][k], scfg[i][1][j]); |
`endif |
end // block: SC |
`ifndef ENABLE_CHANNEL_SLICING |
and AN4 (tos4[i][0][j], ni4[j], scfg[i][0][j]); |
and ANA (tosa[i][0][j], soa[i], scfg[i][0][j]); |
and AL4 (tos4[i][1][j], li4[j], scfg[i][1][j]); |
and ALA (tosa[i][1][j], soa[i], scfg[i][1][j]); |
`endif |
end // block: V |
|
for(k=0; k<SCN; k++) begin: SCOR |
assign so0[i][k] = |(tos0[i][k][0]|tos0[i][k][1]); |
assign so1[i][k] = |(tos1[i][k][0]|tos1[i][k][1]); |
assign so2[i][k] = |(tos2[i][k][0]|tos2[i][k][1]); |
assign so3[i][k] = |(tos3[i][k][0]|tos3[i][k][1]); |
`ifdef ENABLE_CHANNEL_SLICING |
assign so4[i][k] = |(tos4[i][k][0]|tos4[i][k][1]); |
`endif |
end |
`ifndef ENABLE_CHANNEL_SLICING |
assign so4[i] = |(tos4[i][0]|tos4[i][1]); |
`endif |
end |
endgenerate |
|
/*---------------------------- WEST OUPUT -------------------------------------*/ |
generate for (i=0; i<VCN; i=i+1) |
begin:WOP |
for(j=0; j<VCN; j++) begin: V |
for(k=0; k<SCN; k++) begin: SC |
and AS0 (tow0[i][k][0][j], si0[j][k], wcfg[i][0][j]); |
and AS1 (tow1[i][k][0][j], si1[j][k], wcfg[i][0][j]); |
and AS2 (tow2[i][k][0][j], si2[j][k], wcfg[i][0][j]); |
and AS3 (tow3[i][k][0][j], si3[j][k], wcfg[i][0][j]); |
and AN0 (tow0[i][k][1][j], ni0[j][k], wcfg[i][1][j]); |
and AN1 (tow1[i][k][1][j], ni1[j][k], wcfg[i][1][j]); |
and AN2 (tow2[i][k][1][j], ni2[j][k], wcfg[i][1][j]); |
and AN3 (tow3[i][k][1][j], ni3[j][k], wcfg[i][1][j]); |
and AE0 (tow0[i][k][2][j], ei0[j][k], wcfg[i][2][j]); |
and AE1 (tow1[i][k][2][j], ei1[j][k], wcfg[i][2][j]); |
and AE2 (tow2[i][k][2][j], ei2[j][k], wcfg[i][2][j]); |
and AE3 (tow3[i][k][2][j], ei3[j][k], wcfg[i][2][j]); |
and AL0 (tow0[i][k][3][j], li0[j][k], wcfg[i][3][j]); |
and AL1 (tow1[i][k][3][j], li1[j][k], wcfg[i][3][j]); |
and AL2 (tow2[i][k][3][j], li2[j][k], wcfg[i][3][j]); |
and AL3 (tow3[i][k][3][j], li3[j][k], wcfg[i][3][j]); |
`ifdef ENABLE_CHANNEL_SLICING |
and AS4 (tow4[i][k][0][j], si4[j][k], wcfg[i][0][j]); |
and ASA (towa[i][k][0][j], woa[i][k], wcfg[i][0][j]); |
and AN4 (tow4[i][k][1][j], ni4[j][k], wcfg[i][1][j]); |
and ANA (towa[i][k][1][j], woa[i][k], wcfg[i][1][j]); |
and AE4 (tow4[i][k][2][j], ei4[j][k], wcfg[i][2][j]); |
and AEA (towa[i][k][2][j], woa[i][k], wcfg[i][2][j]); |
and AL4 (tow4[i][k][3][j], li4[j][k], wcfg[i][3][j]); |
and ALA (towa[i][k][3][j], woa[i][k], wcfg[i][3][j]); |
`endif |
end // block: SC |
`ifndef ENABLE_CHANNEL_SLICING |
and AS4 (tow4[i][0][j], si4[j], wcfg[i][0][j]); |
and ASA (towa[i][0][j], woa[i], wcfg[i][0][j]); |
and AN4 (tow4[i][1][j], ni4[j], wcfg[i][1][j]); |
and ANA (towa[i][1][j], woa[i], wcfg[i][1][j]); |
and AE4 (tow4[i][2][j], ei4[j], wcfg[i][2][j]); |
and AEA (towa[i][2][j], woa[i], wcfg[i][2][j]); |
and AL4 (tow4[i][3][j], li4[j], wcfg[i][3][j]); |
and ALA (towa[i][3][j], woa[i], wcfg[i][3][j]); |
`endif |
end // block: V |
|
for(k=0; k<SCN; k++) begin: SCOR |
assign wo0[i][k] = |(tow0[i][k][0]|tow0[i][k][1]|tow0[i][k][2]|tow0[i][k][3]); |
assign wo1[i][k] = |(tow1[i][k][0]|tow1[i][k][1]|tow1[i][k][2]|tow1[i][k][3]); |
assign wo2[i][k] = |(tow2[i][k][0]|tow2[i][k][1]|tow2[i][k][2]|tow2[i][k][3]); |
assign wo3[i][k] = |(tow3[i][k][0]|tow3[i][k][1]|tow3[i][k][2]|tow3[i][k][3]); |
`ifdef ENABLE_CHANNEL_SLICING |
assign wo4[i][k] = |(tow4[i][k][0]|tow4[i][k][1]|tow4[i][k][2]|tow4[i][k][3]); |
`endif |
end |
`ifndef ENABLE_CHANNEL_SLICING |
assign wo4[i] = |(tow4[i][0]|tow4[i][1]|tow4[i][2]|tow4[i][3]); |
`endif |
end |
endgenerate |
|
/*---------------------------- NORTH OUPUT -------------------------------------*/ |
generate for (i=0; i<VCN; i=i+1) |
begin:NOP |
for(j=0; j<VCN; j++) begin: V |
for(k=0; k<SCN; k++) begin: SC |
and AS0 (ton0[i][k][0][j], si0[j][k], ncfg[i][0][j]); |
and AS1 (ton1[i][k][0][j], si1[j][k], ncfg[i][0][j]); |
and AS2 (ton2[i][k][0][j], si2[j][k], ncfg[i][0][j]); |
and AS3 (ton3[i][k][0][j], si3[j][k], ncfg[i][0][j]); |
and AL0 (ton0[i][k][1][j], li0[j][k], ncfg[i][1][j]); |
and AL1 (ton1[i][k][1][j], li1[j][k], ncfg[i][1][j]); |
and AL2 (ton2[i][k][1][j], li2[j][k], ncfg[i][1][j]); |
and AL3 (ton3[i][k][1][j], li3[j][k], ncfg[i][1][j]); |
`ifdef ENABLE_CHANNEL_SLICING |
and AS4 (ton4[i][k][0][j], si4[j][k], ncfg[i][0][j]); |
and ASA (tona[i][k][0][j], noa[i][k], ncfg[i][0][j]); |
and AL4 (ton4[i][k][1][j], li4[j][k], ncfg[i][1][j]); |
and ALA (tona[i][k][1][j], noa[i][k], ncfg[i][1][j]); |
`endif |
end // block: SC |
`ifndef ENABLE_CHANNEL_SLICING |
and AS4 (ton4[i][0][j], si4[j], ncfg[i][0][j]); |
and ASA (tona[i][0][j], noa[i], ncfg[i][0][j]); |
and AL4 (ton4[i][1][j], li4[j], ncfg[i][1][j]); |
and ALA (tona[i][1][j], noa[i], ncfg[i][1][j]); |
`endif |
end // block: V |
|
for(k=0; k<SCN; k++) begin: SCOR |
assign no0[i][k] = |(ton0[i][k][0]|ton0[i][k][1]); |
assign no1[i][k] = |(ton1[i][k][0]|ton1[i][k][1]); |
assign no2[i][k] = |(ton2[i][k][0]|ton2[i][k][1]); |
assign no3[i][k] = |(ton3[i][k][0]|ton3[i][k][1]); |
`ifdef ENABLE_CHANNEL_SLICING |
assign no4[i][k] = |(ton4[i][k][0]|ton4[i][k][1]); |
`endif |
end |
`ifndef ENABLE_CHANNEL_SLICING |
assign no4[i] = |(ton4[i][0]|ton4[i][1]); |
`endif |
end |
endgenerate |
|
/*---------------------------- EAST OUPUT -------------------------------------*/ |
generate for (i=0; i<VCN; i=i+1) |
begin:EOP |
for(j=0; j<VCN; j++) begin: V |
for(k=0; k<SCN; k++) begin: SC |
and AS0 (toe0[i][k][0][j], si0[j][k], ecfg[i][0][j]); |
and AS1 (toe1[i][k][0][j], si1[j][k], ecfg[i][0][j]); |
and AS2 (toe2[i][k][0][j], si2[j][k], ecfg[i][0][j]); |
and AS3 (toe3[i][k][0][j], si3[j][k], ecfg[i][0][j]); |
and AW0 (toe0[i][k][1][j], wi0[j][k], ecfg[i][1][j]); |
and AW1 (toe1[i][k][1][j], wi1[j][k], ecfg[i][1][j]); |
and AW2 (toe2[i][k][1][j], wi2[j][k], ecfg[i][1][j]); |
and AW3 (toe3[i][k][1][j], wi3[j][k], ecfg[i][1][j]); |
and AN0 (toe0[i][k][2][j], ni0[j][k], ecfg[i][2][j]); |
and AN1 (toe1[i][k][2][j], ni1[j][k], ecfg[i][2][j]); |
and AN2 (toe2[i][k][2][j], ni2[j][k], ecfg[i][2][j]); |
and AN3 (toe3[i][k][2][j], ni3[j][k], ecfg[i][2][j]); |
and AL0 (toe0[i][k][3][j], li0[j][k], ecfg[i][3][j]); |
and AL1 (toe1[i][k][3][j], li1[j][k], ecfg[i][3][j]); |
and AL2 (toe2[i][k][3][j], li2[j][k], ecfg[i][3][j]); |
and AL3 (toe3[i][k][3][j], li3[j][k], ecfg[i][3][j]); |
`ifdef ENABLE_CHANNEL_SLICING |
and AS4 (toe4[i][k][0][j], si4[j][k], ecfg[i][0][j]); |
and ASA (toea[i][k][0][j], eoa[i][k], ecfg[i][0][j]); |
and AW4 (toe4[i][k][1][j], wi4[j][k], ecfg[i][1][j]); |
and AWA (toea[i][k][1][j], eoa[i][k], ecfg[i][1][j]); |
and AN4 (toe4[i][k][2][j], ni4[j][k], ecfg[i][2][j]); |
and ANA (toea[i][k][2][j], eoa[i][k], ecfg[i][2][j]); |
and AL4 (toe4[i][k][3][j], li4[j][k], ecfg[i][3][j]); |
and ALA (toea[i][k][3][j], eoa[i][k], ecfg[i][3][j]); |
`endif |
end // block: SC |
`ifndef ENABLE_CHANNEL_SLICING |
and AS4 (toe4[i][0][j], si4[j], ecfg[i][0][j]); |
and ASA (toea[i][0][j], eoa[i], ecfg[i][0][j]); |
and AW4 (toe4[i][1][j], wi4[j], ecfg[i][1][j]); |
and AWA (toea[i][1][j], eoa[i], ecfg[i][1][j]); |
and AN4 (toe4[i][2][j], ni4[j], ecfg[i][2][j]); |
and ANA (toea[i][2][j], eoa[i], ecfg[i][2][j]); |
and AL4 (toe4[i][3][j], li4[j], ecfg[i][3][j]); |
and ALA (toea[i][3][j], eoa[i], ecfg[i][3][j]); |
`endif |
end // block: V |
|
for(k=0; k<SCN; k++) begin: SCOR |
assign eo0[i][k] = |(toe0[i][k][0]|toe0[i][k][1]|toe0[i][k][2]|toe0[i][k][3]); |
assign eo1[i][k] = |(toe1[i][k][0]|toe1[i][k][1]|toe1[i][k][2]|toe1[i][k][3]); |
assign eo2[i][k] = |(toe2[i][k][0]|toe2[i][k][1]|toe2[i][k][2]|toe2[i][k][3]); |
assign eo3[i][k] = |(toe3[i][k][0]|toe3[i][k][1]|toe3[i][k][2]|toe3[i][k][3]); |
`ifdef ENABLE_CHANNEL_SLICING |
assign eo4[i][k] = |(toe4[i][k][0]|toe4[i][k][1]|toe4[i][k][2]|toe4[i][k][3]); |
`endif |
end |
`ifndef ENABLE_CHANNEL_SLICING |
assign eo4[i] = |(toe4[i][0]|toe4[i][1]|toe4[i][2]|toe4[i][3]); |
`endif |
end |
endgenerate |
|
|
/*---------------------------- LOCAL OUPUT -------------------------------------*/ |
generate for (i=0; i<VCN; i=i+1) |
begin:LOP |
for(j=0; j<VCN; j++) begin: V |
for(k=0; k<SCN; k++) begin: SC |
and AS0 (tol0[i][k][0][j], si0[j][k], lcfg[i][0][j]); |
and AS1 (tol1[i][k][0][j], si1[j][k], lcfg[i][0][j]); |
and AS2 (tol2[i][k][0][j], si2[j][k], lcfg[i][0][j]); |
and AS3 (tol3[i][k][0][j], si3[j][k], lcfg[i][0][j]); |
and AW0 (tol0[i][k][1][j], wi0[j][k], lcfg[i][1][j]); |
and AW1 (tol1[i][k][1][j], wi1[j][k], lcfg[i][1][j]); |
and AW2 (tol2[i][k][1][j], wi2[j][k], lcfg[i][1][j]); |
and AW3 (tol3[i][k][1][j], wi3[j][k], lcfg[i][1][j]); |
and AN0 (tol0[i][k][2][j], ni0[j][k], lcfg[i][2][j]); |
and AN1 (tol1[i][k][2][j], ni1[j][k], lcfg[i][2][j]); |
and AN2 (tol2[i][k][2][j], ni2[j][k], lcfg[i][2][j]); |
and AN3 (tol3[i][k][2][j], ni3[j][k], lcfg[i][2][j]); |
and AE0 (tol0[i][k][3][j], ei0[j][k], lcfg[i][3][j]); |
and AE1 (tol1[i][k][3][j], ei1[j][k], lcfg[i][3][j]); |
and AE2 (tol2[i][k][3][j], ei2[j][k], lcfg[i][3][j]); |
and AE3 (tol3[i][k][3][j], ei3[j][k], lcfg[i][3][j]); |
`ifdef ENABLE_CHANNEL_SLICING |
and AS4 (tol4[i][k][0][j], si4[j][k], lcfg[i][0][j]); |
and ASA (tola[i][k][0][j], loa[i][k], lcfg[i][0][j]); |
and AW4 (tol4[i][k][1][j], wi4[j][k], lcfg[i][1][j]); |
and AWA (tola[i][k][1][j], loa[i][k], lcfg[i][1][j]); |
and AN4 (tol4[i][k][2][j], ni4[j][k], lcfg[i][2][j]); |
and ANA (tola[i][k][2][j], loa[i][k], lcfg[i][2][j]); |
and AE4 (tol4[i][k][3][j], ei4[j][k], lcfg[i][3][j]); |
and AEA (tola[i][k][3][j], loa[i][k], lcfg[i][3][j]); |
`endif |
end // block: SC |
`ifndef ENABLE_CHANNEL_SLICING |
and AS4 (tol4[i][0][j], si4[j], lcfg[i][0][j]); |
and ASA (tola[i][0][j], loa[i], lcfg[i][0][j]); |
and AW4 (tol4[i][1][j], wi4[j], lcfg[i][1][j]); |
and AWA (tola[i][1][j], loa[i], lcfg[i][1][j]); |
and AN4 (tol4[i][2][j], ni4[j], lcfg[i][2][j]); |
and ANA (tola[i][2][j], loa[i], lcfg[i][2][j]); |
and AE4 (tol4[i][3][j], ei4[j], lcfg[i][3][j]); |
and AEA (tola[i][3][j], loa[i], lcfg[i][3][j]); |
`endif |
end // block: V |
|
for(k=0; k<SCN; k++) begin: SCOR |
assign lo0[i][k] = |(tol0[i][k][0]|tol0[i][k][1]|tol0[i][k][2]|tol0[i][k][3]); |
assign lo1[i][k] = |(tol1[i][k][0]|tol1[i][k][1]|tol1[i][k][2]|tol1[i][k][3]); |
assign lo2[i][k] = |(tol2[i][k][0]|tol2[i][k][1]|tol2[i][k][2]|tol2[i][k][3]); |
assign lo3[i][k] = |(tol3[i][k][0]|tol3[i][k][1]|tol3[i][k][2]|tol3[i][k][3]); |
`ifdef ENABLE_CHANNEL_SLICING |
assign lo4[i][k] = |(tol4[i][k][0]|tol4[i][k][1]|tol4[i][k][2]|tol4[i][k][3]); |
`endif |
end |
`ifndef ENABLE_CHANNEL_SLICING |
assign lo4[i] = |(tol4[i][0]|tol4[i][1]|tol4[i][2]|tol4[i][3]); |
`endif |
end |
endgenerate |
|
generate for(i=0; i<VCN; i++) begin: IACK |
`ifdef ENABLE_CHANNEL_SLICING |
for(k=0; k<SCN; k++) begin: SC |
for(j=0; j<VCN; j++) begin: SHUFFLE |
assign isa[i][k][0][j] = towa[j][k][0][i]; |
assign isa[i][k][1][j] = tona[j][k][0][i]; |
assign isa[i][k][2][j] = toea[j][k][0][i]; |
assign isa[i][k][3][j] = tola[j][k][0][i]; |
assign iwa[i][k][0][j] = toea[j][k][1][i]; |
assign iwa[i][k][1][j] = tola[j][k][1][i]; |
assign ina[i][k][0][j] = tosa[j][k][0][i]; |
assign ina[i][k][1][j] = towa[j][k][1][i]; |
assign ina[i][k][2][j] = toea[j][k][2][i]; |
assign ina[i][k][3][j] = tola[j][k][2][i]; |
assign iea[i][k][0][j] = towa[j][k][2][i]; |
assign iea[i][k][1][j] = tola[j][k][3][i]; |
assign ila[i][k][0][j] = tosa[j][k][1][i]; |
assign ila[i][k][1][j] = towa[j][k][3][i]; |
assign ila[i][k][2][j] = tona[j][k][1][i]; |
assign ila[i][k][3][j] = toea[j][k][3][i]; |
end // block: SHUFFLE |
assign sia[i][k] = |{isa[i][k][0]|isa[i][k][1]|isa[i][k][2]|isa[i][k][3]}; |
assign wia[i][k] = |{iwa[i][k][0]|iwa[i][k][1]}; |
assign nia[i][k] = |{ina[i][k][0]|ina[i][k][1]|ina[i][k][2]|ina[i][k][3]}; |
assign eia[i][k] = |{iea[i][k][0]|iea[i][k][1]}; |
assign lia[i][k] = |{ila[i][k][0]|ila[i][k][1]|ila[i][k][2]|ila[i][k][3]}; |
end // block: SC |
`else // !`ifdef ENABLE_CHANNEL_SLICING |
for(j=0; j<VCN; j++) begin: SHUFFLE |
assign isa[i][0][j] = towa[j][0][i]; |
assign isa[i][1][j] = tona[j][0][i]; |
assign isa[i][2][j] = toea[j][0][i]; |
assign isa[i][3][j] = tola[j][0][i]; |
assign iwa[i][0][j] = toea[j][1][i]; |
assign iwa[i][1][j] = tola[j][1][i]; |
assign ina[i][0][j] = tosa[j][0][i]; |
assign ina[i][1][j] = towa[j][1][i]; |
assign ina[i][2][j] = toea[j][2][i]; |
assign ina[i][3][j] = tola[j][2][i]; |
assign iea[i][0][j] = towa[j][2][i]; |
assign iea[i][1][j] = tola[j][3][i]; |
assign ila[i][0][j] = tosa[j][1][i]; |
assign ila[i][1][j] = towa[j][3][i]; |
assign ila[i][2][j] = tona[j][1][i]; |
assign ila[i][3][j] = toea[j][3][i]; |
end // block: SHUFFLE |
assign sia[i] = |{isa[i][0]|isa[i][1]|isa[i][2]|isa[i][3]}; |
assign wia[i] = |{iwa[i][0]|iwa[i][1]}; |
assign nia[i] = |{ina[i][0]|ina[i][1]|ina[i][2]|ina[i][3]}; |
assign eia[i] = |{iea[i][0]|iea[i][1]}; |
assign lia[i] = |{ila[i][0]|ila[i][1]|ila[i][2]|ila[i][3]}; |
`endif |
end // block: IACK |
endgenerate |
|
endmodule // dcb_xy |
|
|
|
dcb_xy.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ctree.v
===================================================================
--- ctree.v (nonexistent)
+++ ctree.v (revision 56)
@@ -0,0 +1,45 @@
+/*
+ Asynchronous SDM NoC
+ (C)2011 Wei Song
+ Advanced Processor Technologies Group
+ Computer Science, the Univ. of Manchester, UK
+
+ Authors:
+ Wei Song wsong83@gmail.com
+
+ License: LGPL 3.0 or later
+
+ C-element tree, usually for common ack generation.
+ *** SystemVerilog is used ***
+
+ History:
+ 17/04/2011 Initial version.
+ 23/05/2011 Clean up for opensource.
+
+*/
+
+module ctree (/*AUTOARG*/
+ // Outputs
+ co,
+ // Inputs
+ ci
+ );
+
+ parameter DW = 2; // the total number of leaves of the C-element tree
+
+ input [DW-1:0] ci; // all input leaves
+ output co; // the combined output
+
+ wire [2*DW-2:0] dat;
+ genvar i;
+
+ assign dat[DW-1:0] = ci;
+
+ generate for (i=0; i