URL
https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
Compare Revisions
- This comparison shows the changes necessary to convert path
/async_sdm_noc/trunk/common
- from Rev 22 to Rev 28
- ↔ Reverse comparison
Rev 22 → Rev 28
/script/cell_constraint.tcl
13,10 → 13,11
# |
# History: |
# 03/07/2009 Initial version. <wsong83@gmail.com> |
# 21/05/2011 Change to the Nangate cell library. <wsong83@gmail.com> |
# 27/05/2011 Change to the Nangate cell library. <wsong83@gmail.com> |
|
set_dont_touch mutex |
set_dont_touch mutex2 |
set_dont_touch delay |
# It is not a problem if there is no delay cells in the design. |
|
uniquify -force |
|
38,14 → 39,16
foreach_in_collection celln [get_references -hierarchical c2n_*] { |
set_disable_timing [get_object_name $celln]/U1 -from B -to Z |
} |
# It is not a problem if there is no c2n cells in the design. |
|
# c2p gates |
foreach_in_collection celln [get_references -hierarchical c2p_*] { |
set_disable_timing [get_object_name $celln]/U1 -from B -to O |
set_disable_timing [get_object_name $celln]/U1 -from B -to Z |
} |
# It is not a problem if there is no c2p cells in the design. |
|
# mutex gates |
foreach_in_collection celln [get_references -hierarchical mutex_*] { |
foreach_in_collection celln [get_references -hierarchical mutex2_*] { |
set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN |
set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN |
set_dont_touch [get_object_name $celln]/U2 |
57,6 → 60,7
set_disable_timing [get_object_name $celln]/U2 -from B -to Z |
set_disable_timing [get_object_name $celln]/U3 -from B -to Z |
} |
# It is not a problem if MRMA is not used in the design. |
|
# tarb |
foreach_in_collection celln [get_references -hierarchical tarb_*] { |
63,9 → 67,34
set_disable_timing [get_object_name $celln]/U2 -from A -to Z |
set_disable_timing [get_object_name $celln]/U3 -from A -to Z |
} |
# It is not a problem if tree arbiter is not used in the design. |
|
# cr_blk |
foreach_in_collection celln [get_references -hierarchical cr_blk_*] { |
set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z |
} |
# It is not a problem if MRMA is not used in the design. |
|
# mrma multi-resource match arbiter |
foreach_in_collection celln [get_references -hierarchical mrma_*] { |
set_disable_timing [get_object_name $celln]/*.AND_*G* -from B -to Z |
set_disable_timing [get_object_name $celln]/*.AND_RG* -from A -to Z |
} |
# It is not a problem if MRMA is not used in the design. |
|
# dcb data crossbar |
foreach_in_collection celln [get_references -hierarchical dcb_*] { |
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z |
} |
|
# dcb data crossbar |
foreach_in_collection celln [get_references -hierarchical rcb_*] { |
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z |
} |
#It is not a problem if there is no rcb modules in the design. |
|
# mnmr m-n match allocator |
foreach_in_collection celln [get_references -hierarchical mnma_*] { |
set_disable_timing [get_object_name $celln]/*.AND_OPRen* -from B -to Z |
} |
#It is not a problem if MNMA is not used in the design. |
/script/tech.tcl
19,7 → 19,7
|
set rm_library "Nangate_typ.db" |
|
set search_path [concat ${search_path} "${rm_lib_dirs}/"] |
set search_path [concat ${search_path} "${rm_lib_dirs}/" ".."] |
|
set synthetic_library dw_foundation.sldb |
set link_library [list *] |
/src/mrma.v
19,7 → 19,7
History: |
05/09/2009 Initial version. <wsong83@gmail.com> |
05/11/2009 Speed up the arbiter. <wsong83@gmail.com> |
24/05/2011 Clean up for opensource. <wsong83@gmail.com> |
27/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
45,9 → 45,9
|
wire [M-1:0][N-1:0] hs; // match results |
wire [M-1:0][N-1:0] blk; // blockage |
wire [N-1:0][M-1:0] cblk; // shuffled blockage |
wire [M-1:0] rblk; // resource blockage |
wire [N-1:0] cblk; // client blockage |
wire [N-1:0][M-1:0] sblk; // shuffled blockage |
wire [M-1:0] rbi; // resource blockage |
wire [N-1:0] cbi; // client blockage |
wire [N-1:0] cg, cm; // client requests |
wire [M-1:0] rg, rm; // resource requests |
|
82,13 → 82,13
); |
|
// shuffle the blockage |
assign cblk[j][i] = blk[i][j]; |
assign sblk[j][i] = blk[i][j]; |
|
// shuffle the configuration |
assign scfg[j][i] = cfg[i][j]; |
|
// store the match results |
c2p C (.q(cfg[i][j]), .a0(c[j]), .a1(hs[i][j])); |
c2p C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j])); |
|
end // block: Clm |
end // block: Row |
97,15 → 97,16
for(i=0; i<M; i++) begin: RB |
assign rbi[i] = (|blk[i]) & rst_n; |
and AND_RG (rm[i], r[i], ~ra[i], rst_n); |
ra[i] = |cfg[i]; |
assign ra[i] = |cfg[i]; |
end |
|
// combine the column blockage and generate input requests |
for(j=0; j<N; j++) begin: CB |
assign cbi[j] = (|cblk[j]) & rst_n; |
assign cbi[j] = (|sblk[j]) & rst_n; |
and AND_CG (cm[j], c[j], ~ca[j], rst_n); |
assign ca[j] = |scfg[j]; |
end |
endgenerate |
|
endmodule // im_arb |
endmodule // mrma |
|
/src/pipe4.v
15,7 → 15,7
History: |
05/05/2009 Initial version. <wsong83@gmail.com> |
17/04/2011 Replace the common ack generation. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
26/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
41,12 → 41,12
output ia; // output ack |
|
`ifdef ENABLE_EOF |
input o4; // the eof bit |
output i4; |
output o4; // the eof bit |
input i4; |
`endif |
|
// internal signals |
wire [2*SCN-2:0] tack; |
wire [SCN-1:0] tack; |
|
// generate the ack line |
genvar i; |
61,7 → 61,7
|
// the eof bit |
`ifdef ENABLE_EOF |
dc2 DD_DC4 (.d(i4), .a(oa[SCN-1]), .q(o4)); |
dc2 DD_DC4 (.d(i4), .a(oa), .q(o4)); |
`endif |
|
// generate the input ack |
/src/tree_arb.v
46,7 → 46,7
end |
else if(MR == 2) // special case: only two input |
begin: MA_2 |
mutex ME0 ( |
mutex2 ME0 ( |
.a ( req[0] ), |
.b ( req[1] ), |
.qa ( gnt[0] ), |
56,7 → 56,7
else |
begin: MA_N |
|
mutex ME0 ( |
mutex2 ME0 ( |
.a ( mreq[0] ), |
.b ( mreq[1] ), |
.qa ( rgnt[0] ), |
/src/cell_lib.v
79,7 → 79,7
endmodule |
|
// 2-input MUTEX cell, Nangate |
module mutex ( a, b, qa, qb ); // !!! dont touch !!! |
module mutex2 ( a, b, qa, qb ); // !!! dont touch !!! |
|
input a, b; // request inputs |
output qa, qb; // grant outputs |
120,7 → 120,7
wire n1, n2; // internal wires |
wire [1:0] mgnt; // outputs of the MUTEX |
|
mutex ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) ); |
mutex2 ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) ); |
c2n C0 ( .a(ntgnt), .b(n2), .q(ngnt[0]) ); |
c2n C1 ( .a(ntgnt), .b(n1), .q(ngnt[1]) ); |
nand U1 (treq, n1, n2); |
/src/mutex_arb.v
37,7 → 37,7
generate |
for(i=0; i<wd; i=i+1) begin:lv |
for(j=i+1; j<wd; j=j+1) begin:b |
mutex ME ( .a(arb_w[i][j-1]), .b(arb_w[j][i]), .qa(arb_w[i][j]), .qb(arb_w[j][i+1])); |
mutex2 ME ( .a(arb_w[i][j-1]), .b(arb_w[j][i]), .qa(arb_w[i][j]), .qb(arb_w[j][i+1])); |
end |
assign arb_w[i][0] = req[i]; |
assign gnt[i] = arb_w[i][wd-1]; |
/src/rcb.v
15,7 → 15,7
History: |
10/12/2009 Initial version. <wsong83@gmail.com> |
23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com> |
23/05/2011 Clean up for opensource. <wsong83@gmail.com> |
27/05/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
33,11 → 33,11
input [NN-1:0][DW-1:0] ireq; // input requests |
output [NN-1:0] ira; // ack for input requests |
output [MN-1:0][DW-1:0] oreq; // output requests |
input [DW-1:0] ora; // ack for output requests |
input [MN-1:0] ora; // ack for output requests |
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration |
|
wire [MN-1:0][DW-1:0][NN-1-1:0] m; // the internal wires for requests |
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks |
wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for requests |
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks |
|
// generate variable |
genvar i, j, k; |
45,8 → 45,8
// request matrix |
generate |
for (i=0; i<MN; i++) begin: EN |
for (j=0; j<DW; j=j+1) begin: SC |
for (k=0; k<NN; k=k+1) begin: IP |
for (j=0; j<DW; j++) begin: SC |
for (k=0; k<NN; k++) begin: IP |
and AC (m[i][j][k], ireq[k][j], cfg[i][k]); |
end |
|
58,8 → 58,8
|
// ack matrix |
generate |
for (k=0; k<NN; k=k+1) begin: ENA |
for (i=0; i<MN; i=i+1) begin: OP |
for (k=0; k<NN; k++) begin: ENA |
for (i=0; i<MN; i++) begin: OP |
and AC (ma[k][i], ora[i], cfg[i][k]); |
end |
|
/src/mnma.v
27,7 → 27,7
|
module mnma(/*AUTOARG*/ |
// Outputs |
cfg, |
ra, cfg, |
// Inputs |
r |
); |
35,6 → 35,7
parameter M = 2; // number of resources |
|
input [N-1:0][M-1:0] r; // input requests |
output [N-1:0] ra; // ack to input requests |
output [M-1:0][N-1:0] cfg; // configuration to the crssbar |
|
wire [M-1:0][N-1:0] OPr; |
66,6 → 67,9
.req ( IPr[i] ), |
.gnt ( IPg[i] ) |
); |
|
// the input ack |
assign ra[i] = |IPg[i]; |
end |
endgenerate |
|