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https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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Rev 22 → Rev 47
/netnode.v
0,0 → 1,68
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The SystemC module of network node including the processing element and the network interface. |
Currently the transmission FIFO is 500 frame deep. |
|
History: |
27/02/2011 Initial version. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
`include "define.v" |
|
module NetNode ( |
doa, doc, do0, do1, do2, do3, doft, dovc, doca, |
dia, dic, di0, di1, di2, di3, dift, divc, dica, |
rst_n) |
// |
// The foreign attribute string value must be a SystemC value. |
// |
(* integer foreign = "SystemC"; |
*); |
// |
// Verilog port names must match port names exactly as they appear in the |
// sc_module class in SystemC; they must also match in order, mode, and type. |
// |
parameter DW = 32; |
parameter VCN = 1; |
parameter FT = 3; |
parameter x = 2; |
parameter y = 2; |
parameter SCN = DW/2; |
|
output doa ; |
output [VCN-1:0] doc ; |
input [SCN-1:0] do0 ; |
input [SCN-1:0] do1 ; |
input [SCN-1:0] do2 ; |
input [SCN-1:0] do3 ; |
input [FT-1:0] doft; |
input [VCN-1:0] dovc; |
input [VCN-1:0] doca; |
input dia; |
input [VCN-1:0] dic; |
output [SCN-1:0] di0; |
output [SCN-1:0] di1; |
output [SCN-1:0] di2; |
output [SCN-1:0] di3; |
output [FT-1:0] dift; |
output [VCN-1:0] divc; |
output [VCN-1:0] dica; |
|
|
input rst_n; |
|
|
endmodule // NetNode |
|
|
/netnode.h
0,0 → 1,148
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The SystemC module of network node including the processing element and the network interface. |
Currently the transmission FIFO is 500 frame deep. |
|
History: |
26/02/2011 Initial version. <wsong83@gmail.com> |
04/03/2011 Support VC router. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
#ifndef NETNODE_H_ |
#define NETNODE_H_ |
|
#include "define.h" |
#include <systemc.h> |
#include "ni.h" |
#include "procelem.h" |
#include "rtdriver.h" |
|
class NetNode : public sc_module { |
public: |
RTDriver * LIOD; /* driving and convert I/O to/from router local port */ |
Network_Adapter * NI; /* network interface */ |
ProcElem * PE; /* processor element */ |
|
// signals for router |
sc_out< sc_logic > doa ; |
sc_out< sc_lv<SubChN > > doc ; |
sc_in< sc_lv<ChBW*4 > > do0 ; |
sc_in< sc_lv<ChBW*4 > > do1 ; |
sc_in< sc_lv<ChBW*4 > > do2 ; |
sc_in< sc_lv<ChBW*4 > > do3 ; |
sc_in< sc_lv<3> > doft; |
sc_in< sc_lv<SubChN > > dovc; |
sc_in< sc_lv<SubChN > > doca; |
sc_in< sc_logic > dia; |
sc_in< sc_lv<SubChN > > dic; |
sc_out< sc_lv<ChBW*4 > > di0; |
sc_out< sc_lv<ChBW*4 > > di1; |
sc_out< sc_lv<ChBW*4 > > di2; |
sc_out< sc_lv<ChBW*4 > > di3; |
sc_out< sc_lv<3> > dift; |
sc_out< sc_lv<SubChN > > divc; |
sc_out< sc_lv<SubChN > > dica; |
|
sc_in<sc_logic > rst_n; /* global active-low reset */ |
|
// signals between IOD and NI |
sc_fifo<pdu_flit<ChBW> > * NI2P ; /* flit fifo, from NI to IO driver */ |
sc_fifo<pdu_flit<ChBW> > * P2NI ; /* flit fifo, from IO driver to NI */ |
sc_signal<bool> CP [SubChN]; /* credit input */ |
sc_signal<bool> CPa [SubChN]; /* credit ack */ |
|
// signals between NI and FG/FS |
sc_fifo<pdu_frame<ChBW> > * FIQ; /* the frame fifo, from PE to NI */ |
sc_fifo<pdu_frame<ChBW> > * FOQ; /* the frame fifo, from NI to PE */ |
sc_signal<bool> brst_n; /* the reset in the SystemC modules */ |
|
int x, y; /* private local address */ |
|
SC_CTOR(NetNode) |
: doa("doa"), doc("doc"), |
do0("do0"), do1("do1"), do2("do2"), do3("do3"), |
doft("doft"), dovc("dovc"), doca("doca"), |
dia("dia"), dic("dic"), |
di0("di0"), di1("di1"), di2("di2"), di3("di3"), |
dift("dift"), divc("divc"), dica("dica"), |
rst_n("rst_n") |
{ |
// dynamically get the parameters from Verilog test bench |
ncsc_get_param("x", x); |
ncsc_get_param("y", y); |
|
// initialization |
LIOD = new RTDriver("LIOD"); |
NI = new Network_Adapter("NI", x, y); |
PE = new ProcElem("PE", x, y); |
NI2P = new sc_fifo<pdu_flit<ChBW> >(1); |
P2NI = new sc_fifo<pdu_flit<ChBW> >(1); |
FIQ = new sc_fifo<pdu_frame<ChBW> >(500);/* currently the fifo from PE is 500 frame deep */ |
FOQ = new sc_fifo<pdu_frame<ChBW> >(1); |
|
// connections |
LIOD->NI2P(*NI2P); |
LIOD->P2NI(*P2NI); |
LIOD->rtid[0](di0); |
LIOD->rtod[0](do0); |
LIOD->rtid[1](di1); |
LIOD->rtod[1](do1); |
LIOD->rtid[2](di2); |
LIOD->rtod[2](do2); |
LIOD->rtid[3](di3); |
LIOD->rtod[3](do3); |
LIOD->rtift(dift); |
LIOD->rtivc(divc); |
LIOD->rtia(dia); |
LIOD->rtic(dic); |
LIOD->rtica(dica); |
LIOD->rtoft(doft); |
LIOD->rtovc(dovc); |
LIOD->rtoa(doa); |
LIOD->rtoc(doc); |
LIOD->rtoca(doca); |
for(unsigned int j=0; j<SubChN; j++) { |
LIOD->CP[j](CP[j]); |
LIOD->CPa[j](CPa[j]); |
} |
|
NI->frame_in(*FIQ); |
NI->frame_out(*FOQ); |
NI->IP(*P2NI); |
NI->OP(*NI2P); |
for(unsigned int j=0; j<SubChN; j++) { |
NI->CP[j](CP[j]); |
NI->CPa[j](CPa[j]); |
} |
|
PE->rst_n(brst_n); |
PE->Fout(*FIQ); |
PE->Fin(*FOQ); |
|
brst_n.write(false); |
|
SC_METHOD(rst_proc); |
sensitive << rst_n; |
} |
|
|
void rst_proc() { |
bool mrst_n; |
mrst_n = rst_n.read().is_01() ? rst_n.read().to_bool() : false; |
brst_n.write(mrst_n); |
} |
}; |
|
|
#endif |
/rtdriver.cpp
0,0 → 1,306
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The port driver between NI and router. |
|
History: |
02/05/2010 Initial version. <wsong83@gmail.com> |
03/06/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com> |
|
*/ |
|
#include "rtdriver.h" |
|
RTDriver::RTDriver(sc_module_name mname) |
: sc_module(mname), |
NI2P("NI2P"), |
P2NI("P2NI"), |
rtia("rtia"), |
rtic("rtic"), |
rtica("rtica"), |
rtoa("rtoa"), |
rtoc("rtoc"), |
rtoca("rtoca") |
{ |
SC_METHOD(IPdetect); |
sensitive << rtia; |
|
SC_METHOD(OPdetect); |
sensitive << rtod[0] << rtod[1] << rtod[2] << rtod[3] << rtovc << rtoft; |
|
SC_METHOD(Creditdetect); |
for(unsigned int i = 0; i<SubChN; i++) { |
sensitive << CPa[i]; |
sensitive << out_cred[i]; |
} |
sensitive << rtic << rtoca; |
|
SC_THREAD(send); |
SC_THREAD(recv); |
|
rtinp_sig = false; |
rtoutp_sig = false; |
} |
|
void RTDriver::IPdetect() { |
sc_logic ack_lv_high, ack_lv_low; // the sc_logic ack |
|
ack_lv_high = rtia.read(); |
ack_lv_low = rtia.read(); |
|
if(ack_lv_high.is_01() && ack_lv_high.to_bool()) |
rtinp_sig = true; |
|
if(ack_lv_low.is_01() && (!ack_lv_low.to_bool())) |
rtinp_sig = false; |
} |
|
void RTDriver::OPdetect() { |
sc_lv<ChBW*4> data_lv; // the ORed data |
sc_logic data_lv_high, data_lv_low; |
sc_lv<SubChN> vc_lv; // the local copy of vc number |
sc_lv<3> ft_lv; // the local copy of flit type |
|
data_lv = rtod[0].read() | rtod[1].read() | rtod[2].read() | rtod[3].read(); |
vc_lv = rtovc.read(); |
ft_lv = rtoft.read(); |
data_lv_high = (sc_logic)(data_lv.and_reduce()) & (sc_logic)(vc_lv.or_reduce()) & (sc_logic)(ft_lv.or_reduce()); |
data_lv_low = (sc_logic)(data_lv.or_reduce()) | (sc_logic)(vc_lv.or_reduce()) | (sc_logic)(ft_lv.or_reduce()); |
|
if(data_lv_high.is_01() && data_lv_high.to_bool()) |
rtoutp_sig = true; |
|
if(data_lv_high.is_01() && (!data_lv_low.to_bool())) |
rtoutp_sig = false; |
} |
|
void RTDriver::Creditdetect() { |
sc_lv<SubChN> mic; // the local input credit |
sc_lv<SubChN> mica; // the local input credit ack |
sc_lv<SubChN> moc; // the local output credit; |
sc_lv<SubChN> moca; // the local output credit ack; |
|
mic = rtic.read(); |
moca = rtoca.read(); |
|
for(unsigned int i=0; i<SubChN; i++) { |
CP[i].write(mic[i].is_01()? mic[i].to_bool():false); |
out_cred_ack[i] = moca[i].is_01()? moca[i].to_bool():false; |
mica[i] = CPa[i].read(); |
moc[i] = out_cred[i]; |
} |
|
rtica.write(mica); |
rtoc.write(moc); |
} |
|
void RTDriver::send() { |
FLIT mflit; // the local flit buffer |
unsigned int i, j; // local loop index |
sc_lv<ChBW*4> mdata[4]; // local data copy |
sc_lv<SubChN> mvc; // local vcn |
sc_lv<3> mft; // local flit type |
|
// initialize the output ports |
mdata[0] = 0; |
mdata[1] = 0; |
mdata[2] = 0; |
mdata[3] = 0; |
mvc = 0; |
mft = 0; |
|
|
rtid[0].write(mdata[0]); |
rtid[1].write(mdata[1]); |
rtid[2].write(mdata[2]); |
rtid[3].write(mdata[3]); |
rtivc.write(mvc); |
rtift.write(mft); |
|
while(true) { |
mflit = NI2P->read(); // read in the flit |
|
// write the flit |
if(mflit.ftype == F_HD) { |
// the target address |
mdata[mflit.addrx&0x3][0] = SC_LOGIC_1; |
mdata[(mflit.addrx&0xc)>>2][1] = SC_LOGIC_1; |
mdata[mflit.addry&0x3][2] = SC_LOGIC_1; |
mdata[(mflit.addry&0xc)>>2][3] = SC_LOGIC_1; |
|
for(i=0,j=4; i<(ChBW-1)*4; i++, j++) { |
switch((mflit[i/4] >> ((i%4)*2)) & 0x3) { |
case 0: mdata[0][j] = SC_LOGIC_1; break; |
case 1: mdata[1][j] = SC_LOGIC_1; break; |
case 2: mdata[2][j] = SC_LOGIC_1; break; |
case 3: mdata[3][j] = SC_LOGIC_1; break; |
} |
} |
} else { |
for(i=0; i<ChBW*4; i++) { |
switch((mflit[i/4] >> ((i%4)*2)) & 0x3) { |
case 0: mdata[0][i] = SC_LOGIC_1; break; |
case 1: mdata[1][i] = SC_LOGIC_1; break; |
case 2: mdata[2][i] = SC_LOGIC_1; break; |
case 3: mdata[3][i] = SC_LOGIC_1; break; |
} |
} |
} |
|
// flit type |
switch(mflit.ftype) { |
case F_HD: mft[0] = SC_LOGIC_1; break; |
case F_DAT: mft[1] = SC_LOGIC_1; break; |
case F_TL: mft[2] = SC_LOGIC_1; break; |
default: break; |
} |
|
// VC number |
mvc[mflit.vcn] = SC_LOGIC_1; |
|
// write to the port |
rtid[0].write(mdata[0]); |
rtid[1].write(mdata[1]); |
rtid[2].write(mdata[2]); |
rtid[3].write(mdata[3]); |
rtivc.write(mvc); |
rtift.write(mft); |
|
// wait for the router to capture the data |
wait(rtinp_sig.posedge_event()); |
wait(0.2, SC_NS); // a delay to avoid data override |
|
// clear the data |
mdata[0] = 0; |
mdata[1] = 0; |
mdata[2] = 0; |
mdata[3] = 0; |
mvc = 0; |
mft = 0; |
|
rtid[0].write(mdata[0]); |
rtid[1].write(mdata[1]); |
rtid[2].write(mdata[2]); |
rtid[3].write(mdata[3]); |
rtivc.write(mvc); |
rtift.write(mft); |
|
// wait for the input port be ready again |
wait(rtinp_sig.negedge_event()); |
wait(0.2, SC_NS); // a delay to avoid data override |
} |
} |
|
void RTDriver::recv() { |
FLIT mflit; // the local flit buffer |
sc_lv<ChBW*4> mdata[4]; // local data copy |
sc_lv<SubChN> mvc; // local vc number |
sc_lv<3> mft; // local flit type |
sc_logic mack = SC_LOGIC_0; // local copy of ack |
sc_lv<4> dd; // the current 1-of-4 data under process |
unsigned int i, j; // local loop index |
|
// initialize the ack signal |
rtoa.write(mack); |
|
while(true) { |
// wait for an incoming flit |
wait(rtoutp_sig.posedge_event()); |
if(out_cred_ack[mflit.vcn].read()) |
wait(out_cred_ack[mflit.vcn].negedge_event()); |
|
// clear the flit |
mflit.clear(); |
|
// analyse the flit |
mdata[0] = rtod[0].read(); |
mdata[1] = rtod[1].read(); |
mdata[2] = rtod[2].read(); |
mdata[3] = rtod[3].read(); |
mft = rtoft.read(); |
mvc = rtovc.read(); |
|
switch(mft.to_uint()) { |
case 1: mflit.ftype = F_HD; break; |
case 2: mflit.ftype = F_DAT; break; |
case 4: mflit.ftype = F_TL; break; |
default: mflit.ftype = F_IDLE; // shoudle not happen |
} |
|
if(mflit.ftype == F_HD) { |
// fetch the address |
dd[0] = mdata[0][0]; dd[1] = mdata[1][0]; dd[2] = mdata[2][0]; dd[3] = mdata[3][0]; |
mflit.addrx |= (c1o42b(dd.to_uint()) << 0); |
dd[0] = mdata[0][1]; dd[1] = mdata[1][1]; dd[2] = mdata[2][1]; dd[3] = mdata[3][1]; |
mflit.addrx |= (c1o42b(dd.to_uint()) << 2); |
dd[0] = mdata[0][2]; dd[1] = mdata[1][2]; dd[2] = mdata[2][2]; dd[3] = mdata[3][2]; |
mflit.addry |= (c1o42b(dd.to_uint()) << 0); |
dd[0] = mdata[0][3]; dd[1] = mdata[1][3]; dd[2] = mdata[2][3]; dd[3] = mdata[3][3]; |
mflit.addry |= (c1o42b(dd.to_uint()) << 2); |
|
// fill in data |
for(i=1; i<ChBW; i++) { |
for(j=0; j<4; j++) { |
dd[0] = mdata[0][i*4+j]; |
dd[1] = mdata[1][i*4+j]; |
dd[2] = mdata[2][i*4+j]; |
dd[3] = mdata[3][i*4+j]; |
mflit[i-1] |= c1o42b(dd.to_uint()) << j*2; |
} |
} |
} else{ |
for(i=0; i<ChBW; i++) { |
for(j=0; j<4; j++) { |
dd[0] = mdata[0][i*4+j]; |
dd[1] = mdata[1][i*4+j]; |
dd[2] = mdata[2][i*4+j]; |
dd[3] = mdata[3][i*4+j]; |
mflit[i] |= c1o42b(dd.to_uint()) << j*2; |
} |
} |
} |
|
// get the binary vc number |
unsigned int fvcn = mvc.to_uint(); |
while(fvcn != 1) { |
mflit.vcn += 1; |
fvcn >>= 1; |
} |
|
// send the flit to the NI |
P2NI->write(mflit); |
|
// send back a credit |
out_cred[mflit.vcn] = true; |
|
wait(0.2, SC_NS); // a delay to avoid data override |
rtoa.write(~mack); // notify that data is captured |
|
// wait for the data withdrawal |
wait(rtoutp_sig.negedge_event()); |
if(!out_cred_ack[mflit.vcn].read()) |
wait(out_cred_ack[mflit.vcn].posedge_event()); |
|
wait(0.2, SC_NS); // a delay to avoid data override |
rtoa.write(mack); // notify that data is captured |
out_cred[mflit.vcn] = false; |
} |
} |
|
unsigned int RTDriver::c1o42b(unsigned int dd) { |
switch(dd) { |
case 1: return 0; |
case 2: return 1; |
case 4: return 2; |
case 8: return 3; |
default: return 0xff; |
} |
} |
/noc_top.v
0,0 → 1,160
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The mesh network for simulation. |
|
History: |
03/03/2011 Initial version. <wsong83@gmail.com> |
04/03/2011 Support VC. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module noc_top(/*AUTOARG*/ |
// Inputs |
rst_n |
); |
input rst_n; |
|
|
parameter DW = 32; |
parameter VCN = 1; |
parameter FT = 3; |
parameter DIMX = 8; |
parameter DIMY = 8; |
parameter SCN = DW/2; |
|
wire [DIMX-1:0][DIMY-1:0][3:0][SCN-1:0] di0, di1, di2, di3; |
wire [DIMX-1:0][DIMY-1:0][3:0][SCN-1:0] do0, do1, do2, do3; |
wire [DIMX-1:0][DIMY-1:0][3:0] dia, doa; |
wire [DIMX-1:0][DIMY-1:0][3:0][FT-1:0] dift, doft; |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] divc, dovc; |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] dic, doc; |
wire [DIMX-1:0][DIMY-1:0][3:0][VCN-1:0] dica, doca; |
|
genvar x, y; |
|
generate for(x=0; x<DIMX; x++) begin: DX |
for(y=0; y<DIMY; y++) begin: DY |
|
node_top #(.DW(DW), .VCN(VCN), .FT(FT), .x(x), .y(y)) |
NN ( |
.si0 (di0[x][y][0]), .si1 (di1[x][y][0]), .si2 (di2[x][y][0]), .si3 (di3[x][y][0]), .sia (dia[x][y][0]), .sift(dift[x][y][0]), .sivc(divc[x][y][0]), .sic(dic[x][y][0]), .sica(dica[x][y][0]), |
.wi0 (di0[x][y][1]), .wi1 (di1[x][y][1]), .wi2 (di2[x][y][1]), .wi3 (di3[x][y][1]), .wia (dia[x][y][1]), .wift(dift[x][y][1]), .wivc(divc[x][y][1]), .wic(dic[x][y][1]), .wica(dica[x][y][1]), |
.ni0 (di0[x][y][2]), .ni1 (di1[x][y][2]), .ni2 (di2[x][y][2]), .ni3 (di3[x][y][2]), .nia (dia[x][y][2]), .nift(dift[x][y][2]), .nivc(divc[x][y][2]), .nic(dic[x][y][2]), .nica(dica[x][y][2]), |
.ei0 (di0[x][y][3]), .ei1 (di1[x][y][3]), .ei2 (di2[x][y][3]), .ei3 (di3[x][y][3]), .eia (dia[x][y][3]), .eift(dift[x][y][3]), .eivc(divc[x][y][3]), .eic(dic[x][y][3]), .eica(dica[x][y][3]), |
.so0 (do0[x][y][0]), .so1 (do1[x][y][0]), .so2 (do2[x][y][0]), .so3 (do3[x][y][0]), .soa (doa[x][y][0]), .soft(doft[x][y][0]), .sovc(dovc[x][y][0]), .soc(doc[x][y][0]), .soca(doca[x][y][0]), |
.wo0 (do0[x][y][1]), .wo1 (do1[x][y][1]), .wo2 (do2[x][y][1]), .wo3 (do3[x][y][1]), .woa (doa[x][y][1]), .woft(doft[x][y][1]), .wovc(dovc[x][y][1]), .woc(doc[x][y][1]), .woca(doca[x][y][1]), |
.no0 (do0[x][y][2]), .no1 (do1[x][y][2]), .no2 (do2[x][y][2]), .no3 (do3[x][y][2]), .noa (doa[x][y][2]), .noft(doft[x][y][2]), .novc(dovc[x][y][2]), .noc(doc[x][y][2]), .noca(doca[x][y][2]), |
.eo0 (do0[x][y][3]), .eo1 (do1[x][y][3]), .eo2 (do2[x][y][3]), .eo3 (do3[x][y][3]), .eoa (doa[x][y][3]), .eoft(doft[x][y][3]), .eovc(dovc[x][y][3]), .eoc(doc[x][y][3]), .eoca(doca[x][y][3]), |
.rst_n(rst_n) |
); |
|
// north link |
if(x==0) begin |
assign di0[x][y][2] = do0[x][y][2]; |
assign di1[x][y][2] = do1[x][y][2]; |
assign di2[x][y][2] = do2[x][y][2]; |
assign di3[x][y][2] = do3[x][y][2]; |
assign doa[x][y][2] = dia[x][y][2]; |
assign dift[x][y][2] = doft[x][y][2]; |
assign divc[x][y][2] = dovc[x][y][2]; |
assign doc[x][y][2] = dic[x][y][2]; |
assign dica[x][y][2] = doca[x][y][2]; |
end else begin |
assign di0[x][y][2] = do0[x-1][y][0]; |
assign di1[x][y][2] = do1[x-1][y][0]; |
assign di2[x][y][2] = do2[x-1][y][0]; |
assign di3[x][y][2] = do3[x-1][y][0]; |
assign doa[x-1][y][0] = dia[x][y][2]; |
assign dift[x][y][2] = doft[x-1][y][0]; |
assign divc[x][y][2] = dovc[x-1][y][0]; |
assign doc[x-1][y][0] = dic[x][y][2]; |
assign dica[x][y][2] = doca[x-1][y][0]; |
end |
|
// south link |
if(x==DIMX-1) begin |
assign di0[x][y][0] = do0[x][y][0]; |
assign di1[x][y][0] = do1[x][y][0]; |
assign di2[x][y][0] = do2[x][y][0]; |
assign di3[x][y][0] = do3[x][y][0]; |
assign doa[x][y][0] = dia[x][y][0]; |
assign dift[x][y][0] = doft[x][y][0]; |
assign divc[x][y][0] = dovc[x][y][0]; |
assign doc[x][y][0] = dic[x][y][0]; |
assign dica[x][y][0] = doca[x][y][0]; |
end else begin |
assign di0[x][y][0] = do0[x+1][y][2]; |
assign di1[x][y][0] = do1[x+1][y][2]; |
assign di2[x][y][0] = do2[x+1][y][2]; |
assign di3[x][y][0] = do3[x+1][y][2]; |
assign doa[x+1][y][2] = dia[x][y][0]; |
assign dift[x][y][0] = doft[x+1][y][2]; |
assign divc[x][y][0] = dovc[x+1][y][2]; |
assign doc[x+1][y][2] = dic[x][y][0]; |
assign dica[x][y][0] = doca[x+1][y][2]; |
end |
|
// west link |
if(y==0) begin |
assign di0[x][y][1] = do0[x][y][1]; |
assign di1[x][y][1] = do1[x][y][1]; |
assign di2[x][y][1] = do2[x][y][1]; |
assign di3[x][y][1] = do3[x][y][1]; |
assign doa[x][y][1] = dia[x][y][1]; |
assign dift[x][y][1] = doft[x][y][1]; |
assign divc[x][y][1] = dovc[x][y][1]; |
assign doc[x][y][1] = dic[x][y][1]; |
assign dica[x][y][1] = doca[x][y][1]; |
end else begin |
assign di0[x][y][1] = do0[x][y-1][3]; |
assign di1[x][y][1] = do1[x][y-1][3]; |
assign di2[x][y][1] = do2[x][y-1][3]; |
assign di3[x][y][1] = do3[x][y-1][3]; |
assign doa[x][y-1][3] = dia[x][y][1]; |
assign dift[x][y][1] = doft[x][y-1][3]; |
assign divc[x][y][1] = dovc[x][y-1][3]; |
assign doc[x][y-1][3] = dic[x][y][1]; |
assign dica[x][y][1] = doca[x][y-1][3]; |
end // else: !if(y==0) |
|
// east link |
if(y==DIMY-1) begin |
assign di0[x][y][3] = do0[x][y][3]; |
assign di1[x][y][3] = do1[x][y][3]; |
assign di2[x][y][3] = do2[x][y][3]; |
assign di3[x][y][3] = do3[x][y][3]; |
assign doa[x][y][3] = dia[x][y][3]; |
assign dift[x][y][3] = doft[x][y][3]; |
assign divc[x][y][3] = dovc[x][y][3]; |
assign doc[x][y][3] = dic[x][y][3]; |
assign dica[x][y][3] = doca[x][y][3]; |
end else begin |
assign di0[x][y][3] = do0[x][y+1][1]; |
assign di1[x][y][3] = do1[x][y+1][1]; |
assign di2[x][y][3] = do2[x][y+1][1]; |
assign di3[x][y][3] = do3[x][y+1][1]; |
assign doa[x][y+1][1] = dia[x][y][3]; |
assign dift[x][y][3] = doft[x][y+1][1]; |
assign divc[x][y][3] = dovc[x][y+1][1]; |
assign doc[x][y+1][1] = dic[x][y][3]; |
assign dica[x][y][3] = doca[x][y+1][1]; |
end // else: !if(y==DIMY-1) |
|
end // block: DY |
end // block: DX |
endgenerate |
|
endmodule // noc_top |
/ni.cpp
0,0 → 1,147
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
A SystemC network adapter/interface for NoC simulation. |
|
History: |
23/12/2008 Initial version. <wsong83@gmail.com> |
30/09/2010 Use template style packet definition. <wsong83@gmail.com> |
16/10/2010 Support SDM. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
#include "ni.h" |
|
Network_Adapter::Network_Adapter( |
sc_module_name name // module name |
,unsigned int x // location x |
,unsigned int y // location y |
): |
sc_module(name), |
frame_in("FrmIn"), |
frame_out("FrmOut"), |
IP("IP"), |
OP("OP"), |
loc_x(x), |
loc_y(y), |
oflit(1) |
{ |
sc_spawn_options opt; |
|
for(unsigned int i=0; i<SubChN; i++) { |
token[i] = BufDepth/2; |
} |
|
for(unsigned int i=0; i<SubChN; i++) { |
sc_spawn(sc_bind(&Network_Adapter::ibuffer_thread, this, i), NULL, &opt); |
sc_spawn(sc_bind(&Network_Adapter::obuffer_thread, this, i), NULL, &opt); |
sc_spawn(sc_bind(&Network_Adapter::credit_update, this, i), NULL, &opt); |
} |
|
SC_THREAD(oport); |
SC_THREAD(iport); |
|
} |
|
Network_Adapter::~Network_Adapter() |
{ |
} |
|
// read in the incoming frame |
void Network_Adapter::ibuffer_thread(unsigned int ii){ |
FRAME mframe; |
FLIT mflit; |
|
while(1){ |
mframe.clear(); |
|
while(1) { |
mflit = iflit[ii].read(); |
mframe << mflit; |
|
if(mflit.ftype == F_TL) break; |
} |
|
frame_out->write(mframe); |
} |
} |
|
// send out a frame |
void Network_Adapter::obuffer_thread(unsigned int ii){ |
|
FRAME mframe; |
FLIT mflit; |
|
while(1){ |
mframe = frame_in->read(); |
|
while(1) { |
mframe >> mflit; |
mflit.vcn = ii; |
|
//fetch a token |
if(token[ii] == 0) |
wait(token_arrive[ii]); |
|
token[ii]--; |
|
oflit.write(mflit); |
|
if(mflit.ftype == F_TL) break; |
} |
} |
} |
|
|
void Network_Adapter::oport() { |
FLIT mflit; |
|
while(1) { |
mflit = oflit.read(); |
OP->write(mflit); |
} |
} |
|
void Network_Adapter::iport() { |
FLIT mflit; |
|
while(1) { |
mflit = IP->read(); |
iflit[mflit.vcn].write(mflit); |
} |
} |
|
void Network_Adapter::credit_update(unsigned int ii) { |
|
CPa[ii].write(false); |
while(1) { |
if(!CP[ii].read()) |
wait(CP[ii].posedge_event()); |
|
token[ii]++; |
token_arrive[ii].notify(); |
CPa[ii].write(true); |
|
wait(CP[ii].negedge_event()); |
CPa[ii].write(false); |
} |
} |
|
bool Network_Adapter::check_frame(const FRAME& frame) |
{ |
// TODO: check the integerity, dummy right noe |
return true; |
} |
|
|
|
|
/rtdriver.h
0,0 → 1,72
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The port driver between NI and router. |
|
History: |
27/04/2010 Initial version. <wsong83@gmail.com> |
03/06/2011 Remove the sc_unit datatype to support data width larger than 64. <wsong83@gmail.com> |
|
*/ |
|
#ifndef RT_DRIVER_H_ |
#define RT_DRIVER_H_ |
|
#include "define.h" |
#include <systemc.h> |
#include "pdu_def.h" |
|
SC_MODULE(RTDriver) { |
|
public: |
// port with network interface |
sc_port<sc_fifo_in_if<FLIT> > NI2P; |
sc_port<sc_fifo_out_if<FLIT> > P2NI; |
sc_out<bool> CP [SubChN]; |
sc_in<bool > CPa [SubChN]; |
|
// signals from interface to router |
sc_out<sc_lv<ChBW*4> > rtid [4]; |
sc_out<sc_lv<3> > rtift; |
sc_out<sc_lv<SubChN> > rtivc; |
sc_in<sc_logic> rtia; |
sc_in<sc_lv<SubChN> > rtic; |
sc_out<sc_lv<SubChN> > rtica; |
|
sc_in<sc_lv<ChBW*4> > rtod [4]; |
sc_in<sc_lv<3> > rtoft; |
sc_in<sc_lv<SubChN> > rtovc; |
sc_out<sc_logic> rtoa; |
sc_out<sc_lv<SubChN> > rtoc; |
sc_in<sc_lv<SubChN> > rtoca; |
|
// local variable |
sc_signal<bool> out_cred[SubChN]; /* the input credit */ |
sc_signal<bool> out_cred_ack[SubChN]; /* the input credit ack */ |
|
|
SC_HAS_PROCESS(RTDriver); |
RTDriver(sc_module_name name); |
|
void IPdetect(); // Method to detect the router input port |
void OPdetect(); // Method to detect the router output port |
void Creditdetect(); // Method to detect the credit ports |
void send(); // thread of sending a flit |
void recv(); // thread to recveive a flit |
|
sc_signal<bool> rtinp_sig; // fire when the router input port is ready for a new flit |
sc_signal<bool> rtoutp_sig; // fire when the router output port has a new flit |
|
unsigned int c1o42b(unsigned int); // convert 1-of-4 to binary |
}; |
|
|
#endif |
/noctb.v
0,0 → 1,48
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Test bench. |
|
History: |
03/03/2011 Initial version. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
`timescale 1ns/1ps |
|
module noctb; |
parameter DW = 8; // the data width of a single virtual circuit |
parameter VCN = 2; // the number of VCs per direction |
parameter DIMX = 4; // the X dimension |
parameter DIMY = 4; // the Y dimension |
|
reg rst_n; |
|
noc_top #(.DW(DW), .VCN(VCN), .DIMX(DIMX), .DIMY(DIMY)) |
NoC (.rst_n(rst_n)); // the mesh network |
|
AnaProc ANAM(); // the global performance analyser |
|
initial begin |
rst_n = 0; |
|
# 133; |
|
rst_n = 1; |
|
end |
|
endmodule // noctb |
|
|
|
|
/rtwrapper.v
0,0 → 1,283
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The wrapper for the synthesized router. |
|
History: |
28/05/2009 Initial version. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module router_hdl(/*AUTOARG*/ |
// Outputs |
sia, wia, nia, eia, lia, sic, wic, nic, eic, lic, so0, so1, so2, |
so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3, |
lo0, lo1, lo2, lo3, soft, woft, noft, eoft, loft, sovc, wovc, novc, |
eovc, lovc, soca, woca, noca, eoca, loca, |
// Inputs |
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, |
ei1, ei2, ei3, li0, li1, li2, li3, sift, wift, nift, eift, lift, |
sivc, wivc, nivc, eivc, livc, sica, wica, nica, eica, lica, soa, |
woa, noa, eoa, loa, soc, woc, noc, eoc, loc, addrx, addry, rst_n |
); |
|
parameter VCN = 1; // number of virtual circuits in each direction. When VCN == 1, it is a wormhole router |
parameter DW = 32; // the datawidth of a single virtual circuit, the total data width of the router is DW*VCN |
parameter FT = 3;// the number of types of flits |
parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit |
|
input [SCN-1:0] si0, si1, si2, si3; |
input [SCN-1:0] wi0, wi1, wi2, wi3; |
input [SCN-1:0] ni0, ni1, ni2, ni3; |
input [SCN-1:0] ei0, ei1, ei2, ei3; |
input [SCN-1:0] li0, li1, li2, li3; |
input [FT-1:0] sift, wift, nift, eift, lift; |
input [VCN-1:0] sivc, wivc, nivc, eivc, livc; |
output sia, wia, nia, eia, lia; |
output [VCN-1:0] sic, wic, nic, eic, lic; |
input [VCN-1:0] sica, wica, nica, eica, lica; |
|
output [SCN-1:0] so0, so1, so2, so3; |
output [SCN-1:0] wo0, wo1, wo2, wo3; |
output [SCN-1:0] no0, no1, no2, no3; |
output [SCN-1:0] eo0, eo1, eo2, eo3; |
output [SCN-1:0] lo0, lo1, lo2, lo3; |
output [FT-1:0] soft, woft, noft, eoft, loft; |
output [VCN-1:0] sovc, wovc, novc, eovc, lovc; |
input soa, woa, noa, eoa, loa; |
input [VCN-1:0] soc, woc, noc, eoc, loc; |
output [VCN-1:0] soca, woca, noca, eoca, loca; |
|
input [7:0] addrx, addry; |
input rst_n; |
|
wire [SCN-1:0] psi0, psi1, psi2, psi3; |
wire [SCN-1:0] pwi0, pwi1, pwi2, pwi3; |
wire [SCN-1:0] pni0, pni1, pni2, pni3; |
wire [SCN-1:0] pei0, pei1, pei2, pei3; |
wire [SCN-1:0] pli0, pli1, pli2, pli3; |
wire [FT-1:0] psift, pwift, pnift, peift, plift; |
wire [VCN-1:0] psivc, pwivc, pnivc, peivc, plivc; |
wire psia, pwia, pnia, peia, plia; |
wire [VCN-1:0] psic, pwic, pnic, peic, plic; |
wire [VCN-1:0] psica, pwica, pnica, peica, plica; |
|
wire [SCN-1:0] pso0, pso1, pso2, pso3; |
wire [SCN-1:0] pwo0, pwo1, pwo2, pwo3; |
wire [SCN-1:0] pno0, pno1, pno2, pno3; |
wire [SCN-1:0] peo0, peo1, peo2, peo3; |
wire [SCN-1:0] plo0, plo1, plo2, plo3; |
wire [FT-1:0] psoft, pwoft, pnoft, peoft, ploft; |
wire [VCN-1:0] psovc, pwovc, pnovc, peovc, plovc; |
wire psoa, pwoa, pnoa, peoa, ploa; |
wire [VCN-1:0] psoc, pwoc, pnoc, peoc, ploc; |
wire [VCN-1:0] psoca, pwoca, pnoca, peoca, ploca; |
|
wire [7:0] paddrx, paddry; |
wire prst_n; |
|
router RT ( |
.sia ( psia ), |
.wia ( pwia ), |
.nia ( pnia ), |
.eia ( peia ), |
.lia ( plia ), |
.sic ( psic ), |
.wic ( pwic ), |
.nic ( pnic ), |
.eic ( peic ), |
.lic ( plic ), |
.so0 ( pso0 ), |
.so1 ( pso1 ), |
.so2 ( pso2 ), |
.so3 ( pso3 ), |
.wo0 ( pwo0 ), |
.wo1 ( pwo1 ), |
.wo2 ( pwo2 ), |
.wo3 ( pwo3 ), |
.no0 ( pno0 ), |
.no1 ( pno1 ), |
.no2 ( pno2 ), |
.no3 ( pno3 ), |
.eo0 ( peo0 ), |
.eo1 ( peo1 ), |
.eo2 ( peo2 ), |
.eo3 ( peo3 ), |
.lo0 ( plo0 ), |
.lo1 ( plo1 ), |
.lo2 ( plo2 ), |
.lo3 ( plo3 ), |
.soft ( psoft ), |
.woft ( pwoft ), |
.noft ( pnoft ), |
.eoft ( peoft ), |
.loft ( ploft ), |
.sovc ( psovc ), |
.wovc ( pwovc ), |
.novc ( pnovc ), |
.eovc ( peovc ), |
.lovc ( plovc ), |
.soca ( psoca ), |
.woca ( pwoca ), |
.noca ( pnoca ), |
.eoca ( peoca ), |
.loca ( ploca ), |
.si0 ( psi0 ), |
.si1 ( psi1 ), |
.si2 ( psi2 ), |
.si3 ( psi3 ), |
.wi0 ( pwi0 ), |
.wi1 ( pwi1 ), |
.wi2 ( pwi2 ), |
.wi3 ( pwi3 ), |
.ni0 ( pni0 ), |
.ni1 ( pni1 ), |
.ni2 ( pni2 ), |
.ni3 ( pni3 ), |
.ei0 ( pei0 ), |
.ei1 ( pei1 ), |
.ei2 ( pei2 ), |
.ei3 ( pei3 ), |
.li0 ( pli0 ), |
.li1 ( pli1 ), |
.li2 ( pli2 ), |
.li3 ( pli3 ), |
.sift ( psift ), |
.wift ( pwift ), |
.nift ( pnift ), |
.eift ( peift ), |
.lift ( plift ), |
.sivc ( psivc ), |
.wivc ( pwivc ), |
.nivc ( pnivc ), |
.eivc ( peivc ), |
.livc ( plivc ), |
.sica ( psica ), |
.wica ( pwica ), |
.nica ( pnica ), |
.eica ( peica ), |
.lica ( plica ), |
.soa ( psoa ), |
.woa ( pwoa ), |
.noa ( pnoa ), |
.eoa ( peoa ), |
.loa ( ploa ), |
.soc ( psoc ), |
.woc ( pwoc ), |
.noc ( pnoc ), |
.eoc ( peoc ), |
.loc ( ploc ), |
.addrx ( paddrx ), |
.addry ( paddry ), |
.rst_n ( prst_n ) |
); |
|
assign sia = psia ; |
assign wia = pwia ; |
assign nia = pnia ; |
assign eia = peia ; |
assign lia = plia ; |
assign sic = psic ; |
assign wic = pwic ; |
assign nic = pnic ; |
assign eic = peic ; |
assign lic = plic ; |
assign so0 = pso0 ; |
assign so1 = pso1 ; |
assign so2 = pso2 ; |
assign so3 = pso3 ; |
assign wo0 = pwo0 ; |
assign wo1 = pwo1 ; |
assign wo2 = pwo2 ; |
assign wo3 = pwo3 ; |
assign no0 = pno0 ; |
assign no1 = pno1 ; |
assign no2 = pno2 ; |
assign no3 = pno3 ; |
assign eo0 = peo0 ; |
assign eo1 = peo1 ; |
assign eo2 = peo2 ; |
assign eo3 = peo3 ; |
assign lo0 = plo0 ; |
assign lo1 = plo1 ; |
assign lo2 = plo2 ; |
assign lo3 = plo3 ; |
assign soft = psoft ; |
assign woft = pwoft ; |
assign noft = pnoft ; |
assign eoft = peoft ; |
assign loft = ploft ; |
assign sovc = psovc ; |
assign wovc = pwovc ; |
assign novc = pnovc ; |
assign eovc = peovc ; |
assign lovc = plovc ; |
assign soca = psoca ; |
assign woca = pwoca ; |
assign noca = pnoca ; |
assign eoca = peoca ; |
assign loca = ploca ; |
assign psi0 = si0 ; |
assign psi1 = si1 ; |
assign psi2 = si2 ; |
assign psi3 = si3 ; |
assign pwi0 = wi0 ; |
assign pwi1 = wi1 ; |
assign pwi2 = wi2 ; |
assign pwi3 = wi3 ; |
assign pni0 = ni0 ; |
assign pni1 = ni1 ; |
assign pni2 = ni2 ; |
assign pni3 = ni3 ; |
assign pei0 = ei0 ; |
assign pei1 = ei1 ; |
assign pei2 = ei2 ; |
assign pei3 = ei3 ; |
assign pli0 = li0 ; |
assign pli1 = li1 ; |
assign pli2 = li2 ; |
assign pli3 = li3 ; |
assign psift = sift ; |
assign pwift = wift ; |
assign pnift = nift ; |
assign peift = eift ; |
assign plift = lift ; |
assign psivc = sivc ; |
assign pwivc = wivc ; |
assign pnivc = nivc ; |
assign peivc = eivc ; |
assign plivc = livc ; |
assign psica = sica ; |
assign pwica = wica ; |
assign pnica = nica ; |
assign peica = eica ; |
assign plica = lica ; |
assign psoa = soa ; |
assign pwoa = woa ; |
assign pnoa = noa ; |
assign peoa = eoa ; |
assign ploa = loa ; |
assign psoc = soc ; |
assign pwoc = woc ; |
assign pnoc = noc ; |
assign peoc = eoc ; |
assign ploc = loc ; |
assign paddrx = addrx ; |
assign paddry = addry ; |
assign prst_n = rst_n ; |
|
initial $sdf_annotate("../syn/file/router.sdf", RT); |
|
endmodule |
/node_top.v
0,0 → 1,125
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
A network node including a router, a NI and a processing element. |
|
History: |
03/03/2011 Initial version. <wsong83@gmail.com> |
04/03/2011 Support VC. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
// the router structure definitions |
`include "define.v" |
|
module node_top(/*AUTOARG*/ |
// Outputs |
sia, wia, nia, eia, sic, wic, nic, eic, so0, so1, so2, so3, wo0, |
wo1, wo2, wo3, no0, no1, no2, no3, eo0, eo1, eo2, eo3, soft, woft, |
noft, eoft, sovc, wovc, novc, eovc, soca, woca, noca, eoca, |
// Inputs |
si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, |
ei1, ei2, ei3, sift, wift, nift, eift, sivc, wivc, nivc, eivc, |
sica, wica, nica, eica, soa, woa, noa, eoa, soc, woc, noc, eoc, |
rst_n |
); |
parameter DW = 32; |
parameter VCN = 1; |
parameter FT = 3; |
parameter x = 0; |
parameter y = 0; |
parameter SCN = DW/2; |
|
input [SCN-1:0] si0, si1, si2, si3; |
input [SCN-1:0] wi0, wi1, wi2, wi3; |
input [SCN-1:0] ni0, ni1, ni2, ni3; |
input [SCN-1:0] ei0, ei1, ei2, ei3; |
input [FT-1:0] sift, wift, nift, eift; |
input [VCN-1:0] sivc, wivc, nivc, eivc; |
output sia, wia, nia, eia; |
output [VCN-1:0] sic, wic, nic, eic; |
input [VCN-1:0] sica, wica, nica, eica; |
|
output [SCN-1:0] so0, so1, so2, so3; |
output [SCN-1:0] wo0, wo1, wo2, wo3; |
output [SCN-1:0] no0, no1, no2, no3; |
output [SCN-1:0] eo0, eo1, eo2, eo3; |
output [FT-1:0] soft, woft, noft, eoft; |
output [VCN-1:0] sovc, wovc, novc, eovc; |
input soa, woa, noa, eoa; |
input [VCN-1:0] soc, woc, noc, eoc; |
output [VCN-1:0] soca, woca, noca, eoca; |
|
wire [SCN-1:0] li0, li1, li2, li3; |
wire [SCN-1:0] lo0, lo1, lo2, lo3; |
wire [FT-1:0] lift; |
wire [VCN-1:0] livc; |
wire lia; |
wire [VCN-1:0] lic; |
wire [VCN-1:0] lica; |
wire [FT-1:0] loft; |
wire [VCN-1:0] lovc; |
wire loa; |
wire [VCN-1:0] loc; |
wire [VCN-1:0] loca; |
|
input rst_n; |
|
|
// the network node |
NetNode #(.DW(DW), .VCN(VCN), .FT(FT), .x(x), .y(y)) |
Node ( |
.doa(loa), .doc(loc), |
.do0(lo0), .do1(lo1), .do2(lo2), .do3(lo3), |
.doft(loft), .dovc(lovc), .doca(loca), |
.dia(lia), .dic(lic), |
.di0(li0), .di1(li1), .di2(li2), .di3(li3), |
.dift(lift), .divc(livc), .dica(lica), |
.rst_n(rst_n) |
); |
|
|
// router wrapper |
router_hdl #(.DW(DW), .VCN(VCN)) |
RTN ( |
.so0(so0), .so1(so1), .so2(so2), .so3(so3), .soa(soa), .soft(soft), .sovc(sovc), .soc(soc), .soca(soca), |
.wo0(wo0), .wo1(wo1), .wo2(wo2), .wo3(wo3), .woa(woa), .woft(woft), .wovc(wovc), .woc(woc), .woca(woca), |
.no0(no0), .no1(no1), .no2(no2), .no3(no3), .noa(noa), .noft(noft), .novc(novc), .noc(noc), .noca(noca), |
.eo0(eo0), .eo1(eo1), .eo2(eo2), .eo3(eo3), .eoa(eoa), .eoft(eoft), .eovc(eovc), .eoc(eoc), .eoca(eoca), |
.lo0(lo0), .lo1(lo1), .lo2(lo2), .lo3(lo3), .loa(loa), .loft(loft), .lovc(lovc), .loc(loc), .loca(loca), |
.si0(si0), .si1(si1), .si2(si2), .si3(si3), .sia(sia), .sift(sift), .sivc(sivc), .sic(sic), .sica(sica), |
.wi0(wi0), .wi1(wi1), .wi2(wi2), .wi3(wi3), .wia(wia), .wift(wift), .wivc(wivc), .wic(wic), .wica(wica), |
.ni0(ni0), .ni1(ni1), .ni2(ni2), .ni3(ni3), .nia(nia), .nift(nift), .nivc(nivc), .nic(nic), .nica(nica), |
.ei0(ei0), .ei1(ei1), .ei2(ei2), .ei3(ei3), .eia(eia), .eift(eift), .eivc(eivc), .eic(eic), .eica(eica), |
.li0(li0), .li1(li1), .li2(li2), .li3(li3), .lia(lia), .lift(lift), .livc(livc), .lic(lic), .lica(lica), |
.addrx (b2chain(x)), |
.addry (b2chain(y)), |
.rst_n (rst_n) |
); |
|
|
// binary to 1-of-4 (Chain) converter |
function [7:0] b2chain; |
input [3:0] data; |
begin |
b2chain[0] = (data[1:0] == 2'b00); |
b2chain[1] = (data[1:0] == 2'b01); |
b2chain[2] = (data[1:0] == 2'b10); |
b2chain[3] = (data[1:0] == 2'b11); |
b2chain[4] = (data[3:2] == 2'b00); |
b2chain[5] = (data[3:2] == 2'b01); |
b2chain[6] = (data[3:2] == 2'b10); |
b2chain[7] = (data[3:2] == 2'b11); |
end |
endfunction |
|
endmodule // node_top |
/ni.h
0,0 → 1,69
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
Network interface for the VC router. |
|
History: |
20/08/2008 Initial version. <wsong83@gmail.com> |
30/09/2010 Use template style packet definition. <wsong83@gmail.com> |
05/06/2011 Clean up for opensource. <wsong83@gmail.com> |
|
*/ |
|
#ifndef NETWORK_ADAPTER_H_ |
#define NETWORK_ADAPTER_H_ |
|
#include "define.h" |
#include <systemc.h> |
|
SC_MODULE(Network_Adapter) |
{ |
|
public: |
SC_HAS_PROCESS(Network_Adapter); |
Network_Adapter( |
sc_module_name name // module name |
,unsigned int x // location x |
,unsigned int y // location y |
); |
~Network_Adapter(); |
|
// interface with processor |
sc_port<sc_fifo_in_if<FRAME> > frame_in; // frame for transmission |
sc_port<sc_fifo_out_if<FRAME> > frame_out; // frame for receiving |
|
// interface with router |
sc_port<sc_fifo_in_if<FLIT> > IP; // input port from IO driver |
sc_port<sc_fifo_out_if<FLIT> > OP; // output port to IO driver |
sc_in<bool> CP [SubChN]; // the credit input from the router input buffer |
sc_out<bool> CPa [SubChN]; // ack to the credit |
|
private: |
unsigned int loc_x,loc_y; // location information |
|
sc_fifo<FLIT> oflit; // the current flit under transmission |
sc_fifo<FLIT> iflit [SubChN]; // the current flits under receiving from all input VCs |
unsigned int token [SubChN]; // the token ready for each output VC |
sc_event token_arrive [SubChN]; // the token ready event |
|
// functional thread |
void ibuffer_thread(unsigned int); // input buffer respond thread |
void obuffer_thread(unsigned int); // output buffer respond thread |
void oport(); // the thread transmitting flit |
void iport(); // the thread receiving flits |
void credit_update(unsigned int); // receive credits and update the available tokens |
|
// other functions |
bool check_frame(const FRAME& frame); // check the correctness of frame received |
}; |
|
#endif |
|
/netnode.cpp
0,0 → 1,23
/* |
Asynchronous SDM NoC |
(C)2011 Wei Song |
Advanced Processor Technologies Group |
Computer Science, the Univ. of Manchester, UK |
|
Authors: |
Wei Song wsong83@gmail.com |
|
License: LGPL 3.0 or later |
|
The SystemC module of network node including the processing element and the network interface. |
Currently the transmission FIFO is 500 frame deep. |
|
History: |
26/02/2011 Initial version. <wsong83@gmail.com> |
|
*/ |
|
#include "netnode.h" |
|
NCSC_MODULE_EXPORT(NetNode) |
|