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/sdm/src/clos_sch.v

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/sdm/src/im_alloc.v

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/sdm/src/router.v

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sdm/src/router.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdm/src/sdm_sch.v =================================================================== --- sdm/src/sdm_sch.v (nonexistent) +++ sdm/src/sdm_sch.v (revision 22) @@ -0,0 +1,242 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Crossbar based SDM switch allocator + *** SystemVerilog is used *** + + References + For the detail structure, please refer to Section 6.3.1 of the thesis: + Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011. + + History: + 28/09/2009 Initial version. + 25/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module sdm_sch (/*AUTOARG*/ + // Outputs + sack, wack, nack, eack, lack, scfg, ncfg, wcfg, ecfg, lcfg, + // Inputs + sreq, nreq, lreq, wreq, ereq + ); + + parameter VCN = 2; // the number of virtual circuits per port + + // income requests + input [VCN-1:0][3:0] sreq, nreq, lreq; + input [VCN-1:0][1:0] wreq, ereq; + + // ack to input buffers + output [VCN-1:0] sack, wack, nack, eack, lack; + + // configuration to the crossbar + output [VCN-1:0][1:0][VCN-1:0] scfg, ncfg; + output [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; + + input rst_n; // active low global reset + + // requests to arbiters +`ifndef ENABLE_MRMA + wire [1:0][VCN-1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals + wire [3:0][VCN-1:0][VCN-1:0] r2w, r2e, r2l; +`else + wire [1:0][VCN-1:0] r2s, r2n; // shuffle the incoming request signals + wire [3:0][VCN-1:0] r2w, r2e, r2l; +`endif + + // ack from arbiters + wire [VCN-1:0][3:0] a2s, a2n, a2l; + wire [VCN-1:0][1:0] a2w, a2e; + + // ack of the arbiters + wire [1:0][VCN-1:0] r2sa, r2na; + wire [3:0][VCN-1:0] r2wa, r2ea, r2la; + +`ifdef ENABLE_MRMA + wire [VCN:0] OPrst_n; // the buffered resets to avoid metastability + wire [VCN-1:0] SOPrdy, SOPblk; // OP ready and blocked status + wire [VCN-1:0] WOPrdy, WOPblk; // OP ready and blocked status + wire [VCN-1:0] NOPrdy, NOPblk; // OP ready and blocked status + wire [VCN-1:0] EOPrdy, EOPblk; // OP ready and blocked status + wire [VCN-1:0] LOPrdy, LOPblk; // OP ready and blocked status +`endif + + genvar i,j; + + // wire shuffle + generate for(i=0; i + 20/09/2010 Modified for the Clos SDM router + 25/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module cm_alloc (/*AUTOARG*/ +`ifndef ENABLE_CRRD + s, +`endif + // Outputs + sra, wra, nra, era, lra, scfg, ncfg, wcfg, ecfg, lcfg, + // Inputs + wr, er, sr, nr, lr + ) ; + + //requests from all IMs + input [1:0] wr, er; + input [3:0] sr, nr, lr; + + // ack to IMs + output sra, wra, nra, era, lra; + + // the configuration to the local CM + output [1:0] scfg, ncfg; + output [3:0] wcfg, ecfg, lcfg; + + // when using the asynchronous dispatching algorithm, status is sent back to IMs +`ifndef ENABLE_CRRD + output [4:0] s; +`endif + + // arbiters + mutex_arb #(2) + SA ( .req ( {lr[0], nr[0]} ), + .gnt ( scfg ) + ); + + mutex_arb #(4) + WA ( .req ( {lr[1], er[0], nr[1], sr[0]} ), + .gnt ( wcfg ) + ); + + mutex_arb #(2) + NA ( .req ( {lr[2], sr[1]} ), + .gnt ( ncfg ) + ); + + mutex_arb #(4) + EA ( .req ( {lr[3], nr[2], wr[0], sr[2]} ), + .gnt ( ecfg ) + ); + + mutex_arb #(4) + LA ( .req ( {er[1], nr[3], wr[1], sr[3]} ), + .gnt ( lcfg ) + ); + + // generating the ack + assign sra = |{wcfg[0], ncfg[0], ecfg[0], lcfg[0]}; + assign wra = |{ecfg[1], lcfg[1]}; + assign nra = |{scfg[0], wcfg[1], ecfg[2], lcfg[2]}; + assign era = |{wcfg[2], lcfg[3]}; + assign lra = |{scfg[1], wcfg[3], ncfg[1], ecfg[3]}; + + // generating the status +`ifndef ENABLE_CRRD + assign s = {|lcfg, |ecfg, |ncfg, |wcfg, |scfg}; +`endif + +endmodule // cm_alloc + +

sdm/src/cm_alloc.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdm/src/input_buf.v =================================================================== --- sdm/src/input_buf.v (nonexistent) +++ sdm/src/input_buf.v (revision 22) @@ -0,0 +1,288 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Input buffer for Wormhole/SDM routers. + *** SystemVerilog is used *** + + References + * Lookahead pipelines + Montek Singh and Steven M. Nowick, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205 + * Channel slicing + Wei Song and Doug Edwards, A low latency wormhole router for asynchronous on-chip networks, Asia and South Pacific Design Automation Conference, 2010, 437-443. + * SDM + Wei Song and Doug Edwards, Asynchronous spatial division multiplexing router, Microprocessors and Microsystems, 2011(35), 85-97. + + History: + 05/05/2009 Initial version. + 20/09/2010 Supporting channel slicing and SDM using macro difinitions. + 24/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module inp_buf (/*AUTOARG*/ + // Outputs + o0, o1, o2, o3, o4, ia, arb_r, + // Inputs + rst_n, i0, i1, i2, i3, i4, oa, addrx, addry, arb_ra + ); + + //-------------------------- parameters ---------------------------------------// + parameter DIR = 0; // the port direction: south, west, north, east, and local + parameter RN = 4; // the number of request outputs, must match the direction + parameter DW = 16; // the data-width of the data-path + parameter PD = 2; // the depth of the input buffer + parameter SCN = DW/2; + + //-------------------------- I/O ports ---------------------------------------// + input rst_n; // global reset, active low + input [SCN-1:0] i0, i1, i2, i3; // data input + output [SCN-1:0] o0, o1, o2, o3; // data output +`ifdef ENABLE_CHANNEL_SLICING + input [SCN-1:0] i4, oa; + output [SCN-1:0] o4, ia; +`else + input i4, oa; + output o4, ia; +`endif + input [7:0] addrx, addry; + output [RN-1:0] arb_r; + input arb_ra; + + //-------------------------- control signals ---------------------------------------// + wire rten; // routing enable + wire frame_end; // identify the end of a frame + wire [7:0] pipe_xd, pipe_yd; // the target address from the incoming frame + wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges + wire [5:0] raw_dec; // the routing decision from the comparator + wire [4:0] dec_reg; // the routing decision kept by C-gates + wire x_equal; // addr x = target x + wire rt_err; // route decoder error + wire rt_ack; // route build ack + +`ifdef ENABLE_CHANNEL_SLICING + wire [SCN-1:0] rtrst; // rt decoder reset for each sub-channel + wire [PD:0][SCN-1:0] pd4, pda, pdan; // data wires for the internal pipeline stages + +`else + wire rtrst; // rt decode reset + wire [PD:0] pd4, pda, pdan; // data wires for the internal pipeline satges +`endif // !`ifdef ENABLE_CHANNEL_SLICING + + genvar i, j; + + //------------------------- pipelines ------------------------------------- // + generate for(i=0; i addr x + assign decision[1] = x_cmp[1][1] | (x_cmp[1][2]&x_cmp[0][1]); // frame x < addr x + assign decision[2] = x_cmp[1][2] & x_cmp[0][2]; // frame x = addr x + assign decision[3] = y_cmp[1][0] | (y_cmp[1][2]&y_cmp[0][0]); // frame y > addr y + assign decision[4] = y_cmp[1][1] | (y_cmp[1][2]&y_cmp[0][1]); // frame y < addr y + assign decision[5] = y_cmp[1][2] & y_cmp[0][2]; // frame y = addr y + +endmodule // routing_decision + + +// the 1-of-4 comparator +module chain_comparator ( + a + ,b + ,q + ); + + input [3:0] a; + input [3:0] b; + output [2:0] q; + + // a > b + assign q[0] = (a[3]&(|b[2:0])) | (a[2]&(|b[1:0])) | (a[1]&(|b[0:0])); + + // a < b + assign q[1] = (a[2]&(|b[3:3])) | (a[1]&(|b[3:2])) | (a[0]&(|b[3:1])); + + // a = b + assign q[2] = (a[3]&b[3]) | (a[2]&b[2]) | (a[1]&b[1]) | (a[0]&b[0]); + +endmodule // chain_comparator Index: sdm/src/subc_ctl.v =================================================================== --- sdm/src/subc_ctl.v (nonexistent) +++ sdm/src/subc_ctl.v (revision 22) @@ -0,0 +1,68 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Sub-channel controller + + References + * Lookahead pipelines + Montek Singh and Steven M. Nowick, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205 + * Channel slicing + Wei Song and Doug Edwards, A low latency wormhole router for asynchronous on-chip networks, Asia and South Pacific Design Automation Conference, 2010, 437-443. + + For the detail structure, please refer to Section 7.1.1 of the thesis: + Wei Song, Spatial parallelism in the routers of asynchronous on-chip networks, PhD thesis, the University of Manchester, 2011. + + History: + 05/05/2009 Initial version. + 22/10/2010 Make it more timing robust. + 24/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module subc_ctl (/*AUTOARG*/ + // Outputs + nack, rt_rst, + // Inputs + ai2cb, ack, eof, rt_ra, rt_err, rst_n + ); + + input ai2cb; // the ack from output ports + input ack; // the ack from the last stage of the input buffer + input eof; // the eof bit from the last stage of the input buffer + input rt_ra; // ack from the switch allocator + input rt_err; // invalid router decision + input rst_n; // the global active low reset signal + output nack; // the ack to the last stage of the input buffer + output rt_rst; // the router reset signal + + wire csc; // internal wires to handle the CSC of the STG + wire acko; // the ack signal after the C2N gate + wire fend; // the end of frame indicator + wire acken; // active low ack enable + +`ifdef ENABLE_LOOKAHEAD + c2n CD (.q(acko), .a0(ai2cb), .a1(ack)); // the C2N gate to avoid early withdrawal +`else + assign acko = ai2cb; +`endif + + c2p CEN (.a1(eof), .a0(acko), .q(fend)); + c2 C (.a0(rt_ra), .a1(fend), .q(csc)); + nand U1 ( acken, rt_ra, ~csc); + nor U2 ( rt_rst, fend, ~csc); + nor AG ( nack, acko&(~eof), acken|(rt_err&ack), ~rst_n); + +endmodule // subc_ctl + + \ No newline at end of file Index: sdm/src/output_buf.v =================================================================== --- sdm/src/output_buf.v (nonexistent) +++ sdm/src/output_buf.v (revision 22) @@ -0,0 +1,143 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Output buffer for Wormhole/SDM routers. + *** SystemVerilog is used *** + + References + * Lookahead pipelines + Montek Singh and Steven M. Nowick}, The design of high-performance dynamic asynchronous pipelines: lookahead style, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007(15), 1256-1269. doi:10.1109/TVLSI.2007.902205 + + History: + 26/05/2009 Initial version. + 20/09/2010 Supporting channel slicing and SDM using macro difinitions. + 22/10/2010 Parameterize the number of pipelines in output buffers. + 23/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +// the out buffer +module outp_buf (/*AUTOARG*/ + // Outputs + o0, o1, o2, o3, o4, ia, + // Inputs + rst_n, i0, i1, i2, i3, i4, oa + ); + + parameter DW = 16; // the datawidth of a single virtual circuit + parameter PD = 2; // buffer depth + parameter SCN = DW/2; // the number of 1-of-4 sub-channel in each virtual circuit + + input rst_n; // global reset, active low + input [SCN-1:0] i0, i1, i2, i3; // data input + output [SCN-1:0] o0, o1, o2, o3; // data output + wire [PD:0][SCN-1:0] pd0, pd1, pd2, pd3; // data wires for the internal pipeline satges +`ifdef ENABLE_CHANNEL_SLICING + input [SCN-1:0] i4, oa; // eof and ack + output [SCN-1:0] o4, ia; + wire [SCN-1:0] ian_dly; + wire [PD:0][SCN-1:0] pd4, pda, pdan; // internal eof and ack +`else + input i4, oa; // eof and ack + output o4, ia; + wire ian_dly; + wire [PD:0] pd4, pda, pdan; // internal eof and ack +`endif + + +//-------------------------- pipeline ---------------------------------------// + genvar i,j; + generate for(i=0; i

sdm/src/output_buf.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: sdm/define.v =================================================================== --- sdm/define.v (nonexistent) +++ sdm/define.v (revision 22) @@ -0,0 +1,30 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Router configuration header file for SDM routers. + + History: + 20/09/2009 Initial version. + 23/05/2011 Clean up for opensource. + +*/ + +// if VCN > 1, set ENABLE_CLOS to use the 2-stage Clos switch for less switching area +`define ENABLE_CLOS + +// set to enable channel slicing for fast data paths +`define ENABLE_CHANNEL_SLICING + +// set to use the early acknowledge of lokkahead pipelines in the critical cycle +`define ENABLE_LOOKAHEAD + +// always set in wormhole and SDM routers to enable the eof bit in data pipeline stages +`define ENABLE_EOF Index: AUTHORS =================================================================== --- AUTHORS (nonexistent) +++ AUTHORS (revision 22) @@ -0,0 +1,3 @@ +Wei Song wsong83@gmail.com Computer Science, the University of Manchester, Manchester M13 9PL, United Kingdom +Doug Edwards doug@cs.man.ac.uk Computer Science, the University of Manchester, Manchester M13 9PL, United Kingdom + Index: lib/NangateOpenCellLibrary_typical_conditional.v =================================================================== --- lib/NangateOpenCellLibrary_typical_conditional.v (nonexistent) +++ lib/NangateOpenCellLibrary_typical_conditional.v (revision 22) @@ -0,0 +1,3936 @@ +// +// ****************************************************************************** +// * * +// * Copyright (C) 2004-2009, Nangate Inc. * +// * All rights reserved. * +// * * +// * Nangate and the Nangate logo are trademarks of Nangate Inc. * +// * * +// * All trademarks, logos, software marks, and trade names (collectively the * +// * "Marks") in this program are proprietary to Nangate or other respective * +// * owners that have granted Nangate the right and license to use such Marks. * +// * You are not permitted to use the Marks without the prior written consent * +// * of Nangate or such third party that may own the Marks. * +// * * +// * This file has been provided pursuant to a License Agreement containing * +// * restrictions on its use. This file contains valuable trade secrets and * +// * proprietary information of Nangate Inc., and is protected by U.S. and * +// * international laws and/or treaties. * +// * * +// * The copyright notice(s) in this file does not indicate actual or intended * +// * publication of this file. * +// * * +// * NGLibraryCharacterizer, v2009.07-HR28-2009-07-08 - build 200907162109 * +// * * +// ****************************************************************************** + +module AND2_X1 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + and(ZN, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND2_X2 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + and(ZN, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND2_X4 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + and(ZN, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND3_X1 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + and(ZN, i_66, A3); + and(i_66, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND3_X2 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + and(ZN, i_66, A3); + and(i_66, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND3_X4 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + and(ZN, i_46, A3); + and(i_46, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND4_X1 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + and(ZN, i_12, A4); + and(i_12, i_13, A3); + and(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND4_X2 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + and(ZN, i_12, A4); + and(i_12, i_13, A3); + and(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AND4_X4 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + and(ZN, i_12, A4); + and(i_12, i_13, A3); + and(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module ANTENNA_X1 (A); + + input A; + +endmodule + +module AOI211_X1 (A, B, C1, C2, ZN); + + input A; + input B; + input C1; + input C2; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, A); + or(i_19, i_20, B); + and(i_20, C1, C2); + + specify + if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI211_X2 (A, B, C1, C2, ZN); + + input A; + input B; + input C1; + input C2; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, A); + or(i_19, i_20, B); + and(i_20, C1, C2); + + specify + if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI211_X4 (A, B, C1, C2, ZN); + + input A; + input B; + input C1; + input C2; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, A); + or(i_19, i_20, B); + and(i_20, C1, C2); + + specify + if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI21_X1 (A, B1, B2, ZN); + + input A; + input B1; + input B2; + output ZN; + + not(ZN, i_12); + or(i_12, A, i_13); + and(i_13, B1, B2); + + specify + if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI21_X2 (A, B1, B2, ZN); + + input A; + input B1; + input B2; + output ZN; + + not(ZN, i_52); + or(i_52, A, i_53); + and(i_53, B1, B2); + + specify + if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI21_X4 (A, B1, B2, ZN); + + input A; + input B1; + input B2; + output ZN; + + not(ZN, i_52); + or(i_52, A, i_53); + and(i_53, B1, B2); + + specify + if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI221_X1 (A, B1, B2, C1, C2, ZN); + + input A; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_24); + or(i_24, i_25, i_27); + or(i_25, i_26, A); + and(i_26, C1, C2); + and(i_27, B1, B2); + + specify + (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) || (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI221_X2 (A, B1, B2, C1, C2, ZN); + + input A; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_24); + or(i_24, i_25, i_27); + or(i_25, i_26, A); + and(i_26, C1, C2); + and(i_27, B1, B2); + + specify + (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) || (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI221_X4 (A, B1, B2, C1, C2, ZN); + + input A; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_24); + or(i_24, i_25, i_27); + or(i_25, i_26, A); + and(i_26, C1, C2); + and(i_27, B1, B2); + + specify + (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI222_X1 (A1, A2, B1, B2, C1, C2, ZN); + + input A1; + input A2; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_30); + or(i_30, i_31, i_34); + or(i_31, i_32, i_33); + and(i_32, A1, A2); + and(i_33, B1, B2); + and(i_34, C1, C2); + + specify + (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI222_X2 (A1, A2, B1, B2, C1, C2, ZN); + + input A1; + input A2; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_30); + or(i_30, i_31, i_34); + or(i_31, i_32, i_33); + and(i_32, A1, A2); + and(i_33, B1, B2); + and(i_34, C1, C2); + + specify + (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI222_X4 (A1, A2, B1, B2, C1, C2, ZN); + + input A1; + input A2; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_30); + or(i_30, i_31, i_34); + or(i_31, i_32, i_33); + and(i_32, A1, A2); + and(i_33, B1, B2); + and(i_34, C1, C2); + + specify + (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI22_X1 (A1, A2, B1, B2, ZN); + + input A1; + input A2; + input B1; + input B2; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, i_20); + and(i_19, A1, A2); + and(i_20, B1, B2); + + specify + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI22_X2 (A1, A2, B1, B2, ZN); + + input A1; + input A2; + input B1; + input B2; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, i_20); + and(i_19, A1, A2); + and(i_20, B1, B2); + + specify + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module AOI22_X4 (A1, A2, B1, B2, ZN); + + input A1; + input A2; + input B1; + input B2; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, i_20); + and(i_19, A1, A2); + and(i_20, B1, B2); + + specify + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module BUF_X1 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module BUF_X16 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module BUF_X2 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module BUF_X32 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module BUF_X4 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module BUF_X8 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module CLKBUF_X1 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module CLKBUF_X2 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +module CLKBUF_X3 (A, Z); + + input A; + output Z; + + buf(Z, A); + + specify + (A => Z) = (0.1, 0.1); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATETST_X1 (CK, E, SE, GCK); + + input CK; + input E; + input SE; + output GCK; + reg NOTIFIER; + + and(GCK, IQ, CK); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + or(nextstate, E, SE); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATETST_X2 (CK, E, SE, GCK); + + input CK; + input E; + input SE; + output GCK; + reg NOTIFIER; + + and(GCK, IQ, CK); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + or(nextstate, E, SE); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATETST_X4 (CK, E, SE, GCK); + + input CK; + input E; + input SE; + output GCK; + reg NOTIFIER; + + and(GCK, IQ, CK); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + or(nextstate, E, SE); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATETST_X8 (CK, E, SE, GCK); + + input CK; + input E; + input SE; + output GCK; + reg NOTIFIER; + + and(GCK, IQ, CK); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + or(nextstate, E, SE); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATE_X1 (CK, E, GCK); + + input CK; + input E; + output GCK; + reg NOTIFIER; + + and(GCK, CK, IQ); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + buf(nextstate, E); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATE_X2 (CK, E, GCK); + + input CK; + input E; + output GCK; + reg NOTIFIER; + + and(GCK, CK, IQ); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + buf(nextstate, E); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATE_X4 (CK, E, GCK); + + input CK; + input E; + output GCK; + reg NOTIFIER; + + and(GCK, CK, IQ); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + buf(nextstate, E); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module CLKGATE_X8 (CK, E, GCK); + + input CK; + input E; + output GCK; + reg NOTIFIER; + + and(GCK, CK, IQ); + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQn, IQ); + buf(nextstate, E); + + + specify + (CK => GCK) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge E, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge E, 0.1, 0.1, NOTIFIER); + $width(negedge E, 0.1, 0, NOTIFIER); + $width(posedge E, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN RN nextstate CK NOTIFIER : @IQ : IQ + 1 ? 0 r ? : ? : 0; + ? 1 1 r ? : ? : 1; + 1 ? 0 * ? : 0 : 0; // reduce pessimism + ? 1 1 * ? : 1 : 1; // reduce pessimism + 1 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 1 ? ? ? : ? : 1; // SN activated + * 1 ? ? ? : 1 : 1; // Cover all transitions on SN + ? 0 ? ? ? : ? : 0; // RN activated + 1 * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFFRS_X1 (CK, D, RN, SN, Q, QN); + + input CK; + input D; + input RN; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, RN, nextstate, CK, NOTIFIER); + and(IQN, i_15, i_16); + not(i_15, IQ); + not(i_16, i_17); + and(i_17, i_18, i_19); + not(i_18, SN); + not(i_19, RN); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + and(id_3, SN, RN); + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& id_3, 0.1, 0, NOTIFIER); + $width(posedge CK &&& id_3, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN RN nextstate CK NOTIFIER : @IQ : IQ + 1 ? 0 r ? : ? : 0; + ? 1 1 r ? : ? : 1; + 1 ? 0 * ? : 0 : 0; // reduce pessimism + ? 1 1 * ? : 1 : 1; // reduce pessimism + 1 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 1 ? ? ? : ? : 1; // SN activated + * 1 ? ? ? : 1 : 1; // Cover all transitions on SN + ? 0 ? ? ? : ? : 0; // RN activated + 1 * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFFRS_X2 (CK, D, RN, SN, Q, QN); + + input CK; + input D; + input RN; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, RN, nextstate, CK, NOTIFIER); + and(IQN, i_15, i_16); + not(i_15, IQ); + not(i_16, i_17); + and(i_17, i_18, i_19); + not(i_18, SN); + not(i_19, RN); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + and(id_3, SN, RN); + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& id_3, 0.1, 0, NOTIFIER); + $width(posedge CK &&& id_3, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER); + output IQ; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // RN nextstate CK NOTIFIER : @IQ : IQ + ? 0 r ? : ? : 0; + 1 1 r ? : ? : 1; + ? 0 * ? : 0 : 0; // reduce pessimism + 1 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 0; // RN activated + * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFFR_X1 (CK, D, RN, Q, QN); + + input CK; + input D; + input RN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, RN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + + $width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER); + output IQ; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // RN nextstate CK NOTIFIER : @IQ : IQ + ? 0 r ? : ? : 0; + 1 1 r ? : ? : 1; + ? 0 * ? : 0 : 0; // reduce pessimism + 1 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 0; // RN activated + * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFFR_X2 (CK, D, RN, Q, QN); + + input CK; + input D; + input RN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, RN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + + $width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN nextstate CK NOTIFIER : @IQ : IQ + 1 0 r ? : ? : 0; + ? 1 r ? : ? : 1; + 1 0 * ? : 0 : 0; // reduce pessimism + ? 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 1; // SN activated + * ? ? ? : 1 : 1; // Cover all transitions on SN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFFS_X1 (CK, D, SN, Q, QN); + + input CK; + input D; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN nextstate CK NOTIFIER : @IQ : IQ + 1 0 r ? : ? : 0; + ? 1 r ? : ? : 1; + 1 0 * ? : 0 : 0; // reduce pessimism + ? 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 1; // SN activated + * ? ? ? : 1 : 1; // Cover all transitions on SN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFFS_X2 (CK, D, SN, Q, QN); + + input CK; + input D; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 r ? : ? : 0; + 1 r ? : ? : 1; + 0 * ? : 0 : 0; // reduce pessimism + 1 * ? : 1 : 1; // reduce pessimism + * ? ? : ? : -; // Ignore all edges on nextstate + ? f ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFF_X1 (CK, D, Q, QN); + + input CK; + input D; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 r ? : ? : 0; + 1 r ? : ? : 1; + 0 * ? : 0 : 0; // reduce pessimism + 1 * ? : 1 : 1; // reduce pessimism + * ? ? : ? : -; // Ignore all edges on nextstate + ? f ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DFF_X2 (CK, D, Q, QN); + + input CK; + input D; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + buf(nextstate, D); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, G, NOTIFIER); + output IQ; + input nextstate; + input G; + input NOTIFIER; + reg IQ; + + table +// nextstate G NOTIFIER : @IQ : IQ + 0 1 ? : ? : 0; + 1 1 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 0 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DLH_X1 (D, G, Q); + + input D; + input G; + output Q; + reg NOTIFIER; + + seq3(IQ, nextstate, G, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(nextstate, D); + + + specify + (D => Q) = (0.1, 0.1); + (posedge G => (Q +: D)) = (0.1, 0.1); + + $setuphold(negedge G, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(negedge G, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $width(negedge G, 0.1, 0, NOTIFIER); + $width(posedge G, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, G, NOTIFIER); + output IQ; + input nextstate; + input G; + input NOTIFIER; + reg IQ; + + table +// nextstate G NOTIFIER : @IQ : IQ + 0 1 ? : ? : 0; + 1 1 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 0 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DLH_X2 (D, G, Q); + + input D; + input G; + output Q; + reg NOTIFIER; + + seq3(IQ, nextstate, G, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(nextstate, D); + + + specify + (D => Q) = (0.1, 0.1); + (posedge G => (Q +: D)) = (0.1, 0.1); + + $setuphold(negedge G, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(negedge G, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $width(negedge G, 0.1, 0, NOTIFIER); + $width(posedge G, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, GN, NOTIFIER); + output IQ; + input nextstate; + input GN; + input NOTIFIER; + reg IQ; + + table +// nextstate GN NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DLL_X1 (D, GN, Q); + + input D; + input GN; + output Q; + reg NOTIFIER; + + seq3(IQ, nextstate, GN, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(nextstate, D); + + + specify + (D => Q) = (0.1, 0.1); + (negedge GN => (Q +: D)) = (0.1, 0.1); + + $setuphold(posedge GN, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge GN, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $width(negedge GN, 0.1, 0, NOTIFIER); + $width(posedge GN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, GN, NOTIFIER); + output IQ; + input nextstate; + input GN; + input NOTIFIER; + reg IQ; + + table +// nextstate GN NOTIFIER : @IQ : IQ + 0 0 ? : ? : 0; + 1 0 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 1 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module DLL_X2 (D, GN, Q); + + input D; + input GN; + output Q; + reg NOTIFIER; + + seq3(IQ, nextstate, GN, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(nextstate, D); + + + specify + (D => Q) = (0.1, 0.1); + (negedge GN => (Q +: D)) = (0.1, 0.1); + + $setuphold(posedge GN, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge GN, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $width(negedge GN, 0.1, 0, NOTIFIER); + $width(posedge GN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +module FA_X1 (A, B, CI, CO, S); + + input A; + input B; + input CI; + output CO; + output S; + + or(CO, i_24, i_25); + and(i_24, A, B); + and(i_25, CI, i_26); + or(i_26, A, B); + xor(S, CI, i_30); + xor(i_30, A, B); + + specify + if((B == 1'b0) && (CI == 1'b1)) (A => CO) = (0.1, 0.1); + if((B == 1'b1) && (CI == 1'b0)) (A => CO) = (0.1, 0.1); + if((A == 1'b1) && (CI == 1'b0)) (B => CO) = (0.1, 0.1); + if((A == 1'b0) && (CI == 1'b1)) (B => CO) = (0.1, 0.1); + if((A == 1'b1) && (B == 1'b0)) (CI => CO) = (0.1, 0.1); + if((A == 1'b0) && (B == 1'b1)) (CI => CO) = (0.1, 0.1); + if((B == 1'b0) && (CI == 1'b1)) (A => S) = (0.1, 0.1); + if((B == 1'b0) && (CI == 1'b0)) (A => S) = (0.1, 0.1); + if((B == 1'b1) && (CI == 1'b1)) (A => S) = (0.1, 0.1); + if((B == 1'b1) && (CI == 1'b0)) (A => S) = (0.1, 0.1); + if((A == 1'b0) && (CI == 1'b0)) (B => S) = (0.1, 0.1); + if((A == 1'b1) && (CI == 1'b0)) (B => S) = (0.1, 0.1); + if((A == 1'b1) && (CI == 1'b1)) (B => S) = (0.1, 0.1); + if((A == 1'b0) && (CI == 1'b1)) (B => S) = (0.1, 0.1); + if((A == 1'b1) && (B == 1'b1)) (CI => S) = (0.1, 0.1); + if((A == 1'b1) && (B == 1'b0)) (CI => S) = (0.1, 0.1); + if((A == 1'b0) && (B == 1'b1)) (CI => S) = (0.1, 0.1); + if((A == 1'b0) && (B == 1'b0)) (CI => S) = (0.1, 0.1); + endspecify + +endmodule + +module FILLCELL_X1 (); + + +endmodule + +module FILLCELL_X16 (); + + +endmodule + +module FILLCELL_X2 (); + + +endmodule + +module FILLCELL_X32 (); + + +endmodule + +module FILLCELL_X4 (); + + +endmodule + +module FILLCELL_X8 (); + + +endmodule + +module HA_X1 (A, B, CO, S); + + input A; + input B; + output CO; + output S; + + and(CO, A, B); + xor(S, A, B); + + specify + (A => CO) = (0.1, 0.1); + (B => CO) = (0.1, 0.1); + if((B == 1'b0)) (A => S) = (0.1, 0.1); + if((B == 1'b1)) (A => S) = (0.1, 0.1); + if((A == 1'b1)) (B => S) = (0.1, 0.1); + if((A == 1'b0)) (B => S) = (0.1, 0.1); + endspecify + +endmodule + +module INV_X1 (A, ZN); + + input A; + output ZN; + + not(ZN, A); + + specify + (A => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module INV_X16 (A, ZN); + + input A; + output ZN; + + not(ZN, A); + + specify + (A => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module INV_X2 (A, ZN); + + input A; + output ZN; + + not(ZN, A); + + specify + (A => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module INV_X32 (A, ZN); + + input A; + output ZN; + + not(ZN, A); + + specify + (A => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module INV_X4 (A, ZN); + + input A; + output ZN; + + not(ZN, A); + + specify + (A => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module INV_X8 (A, ZN); + + input A; + output ZN; + + not(ZN, A); + + specify + (A => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module LOGIC0_X1 (Z); + + output Z; + + buf(Z, 0); +endmodule + +module LOGIC1_X1 (Z); + + output Z; + + buf(Z, 1); +endmodule + +module MUX2_X1 (A, B, S, Z); + + input A; + input B; + input S; + output Z; + + or(Z, i_38, i_39); + and(i_38, S, B); + and(i_39, A, i_40); + not(i_40, S); + + specify + if((B == 1'b1) && (S == 1'b0)) (A => Z) = (0.1, 0.1); + if((B == 1'b0) && (S == 1'b0)) (A => Z) = (0.1, 0.1); + if((A == 1'b1) && (S == 1'b1)) (B => Z) = (0.1, 0.1); + if((A == 1'b0) && (S == 1'b1)) (B => Z) = (0.1, 0.1); + if((A == 1'b1) && (B == 1'b0)) (S => Z) = (0.1, 0.1); + if((A == 1'b0) && (B == 1'b1)) (S => Z) = (0.1, 0.1); + endspecify + +endmodule + +module MUX2_X2 (A, B, S, Z); + + input A; + input B; + input S; + output Z; + + or(Z, i_58, i_59); + and(i_58, S, B); + and(i_59, A, i_60); + not(i_60, S); + + specify + if((B == 1'b1) && (S == 1'b0)) (A => Z) = (0.1, 0.1); + if((B == 1'b0) && (S == 1'b0)) (A => Z) = (0.1, 0.1); + if((A == 1'b1) && (S == 1'b1)) (B => Z) = (0.1, 0.1); + if((A == 1'b0) && (S == 1'b1)) (B => Z) = (0.1, 0.1); + if((A == 1'b1) && (B == 1'b0)) (S => Z) = (0.1, 0.1); + if((A == 1'b0) && (B == 1'b1)) (S => Z) = (0.1, 0.1); + endspecify + +endmodule + +module NAND2_X1 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + not(ZN, i_6); + and(i_6, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND2_X2 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + not(ZN, i_6); + and(i_6, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND2_X4 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + not(ZN, i_6); + and(i_6, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND3_X1 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + not(ZN, i_32); + and(i_32, i_33, A3); + and(i_33, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND3_X2 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + not(ZN, i_32); + and(i_32, i_33, A3); + and(i_33, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND3_X4 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + not(ZN, i_12); + and(i_12, i_13, A3); + and(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND4_X1 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, A4); + and(i_19, i_20, A3); + and(i_20, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND4_X2 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, A4); + and(i_19, i_20, A3); + and(i_20, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NAND4_X4 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, A4); + and(i_19, i_20, A3); + and(i_20, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR2_X1 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + not(ZN, i_66); + or(i_66, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR2_X2 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + not(ZN, i_46); + or(i_46, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR2_X4 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + not(ZN, i_66); + or(i_66, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR3_X1 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + not(ZN, i_12); + or(i_12, i_13, A3); + or(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR3_X2 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + not(ZN, i_12); + or(i_12, i_13, A3); + or(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR3_X4 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + not(ZN, i_12); + or(i_12, i_13, A3); + or(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR4_X1 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, A4); + or(i_19, i_20, A3); + or(i_20, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR4_X2 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, A4); + or(i_19, i_20, A3); + or(i_20, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module NOR4_X4 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + not(ZN, i_18); + or(i_18, i_19, A4); + or(i_19, i_20, A3); + or(i_20, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI211_X1 (A, B, C1, C2, ZN); + + input A; + input B; + input C1; + input C2; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, B); + and(i_19, i_20, A); + or(i_20, C1, C2); + + specify + if((B == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI211_X2 (A, B, C1, C2, ZN); + + input A; + input B; + input C1; + input C2; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, B); + and(i_19, i_20, A); + or(i_20, C1, C2); + + specify + if((B == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI211_X4 (A, B, C1, C2, ZN); + + input A; + input B; + input C1; + input C2; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, B); + and(i_19, i_20, A); + or(i_20, C1, C2); + + specify + if((B == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0)) (B => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + if((A == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (B => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI21_X1 (A, B1, B2, ZN); + + input A; + input B1; + input B2; + output ZN; + + not(ZN, i_12); + and(i_12, A, i_13); + or(i_13, B1, B2); + + specify + if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b1) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI21_X2 (A, B1, B2, ZN); + + input A; + input B1; + input B2; + output ZN; + + not(ZN, i_12); + and(i_12, A, i_13); + or(i_13, B1, B2); + + specify + if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b1) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI21_X4 (A, B1, B2, ZN); + + input A; + input B1; + input B2; + output ZN; + + not(ZN, i_12); + and(i_12, A, i_13); + or(i_13, B1, B2); + + specify + if((B1 == 1'b1) && (B2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b1) && (B2 == 1'b1)) (A => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI221_X1 (A, B1, B2, C1, C2, ZN); + + input A; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_24); + and(i_24, i_25, i_27); + and(i_25, i_26, A); + or(i_26, C1, C2); + or(i_27, B1, B2); + + specify + (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI221_X2 (A, B1, B2, C1, C2, ZN); + + input A; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_24); + and(i_24, i_25, i_27); + and(i_25, i_26, A); + or(i_26, C1, C2); + or(i_27, B1, B2); + + specify + (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI221_X4 (A, B1, B2, C1, C2, ZN); + + input A; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_24); + and(i_24, i_25, i_27); + and(i_25, i_26, A); + or(i_26, C1, C2); + or(i_27, B1, B2); + + specify + (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI222_X1 (A1, A2, B1, B2, C1, C2, ZN); + + input A1; + input A2; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_30); + and(i_30, i_31, i_34); + and(i_31, i_32, i_33); + or(i_32, A1, A2); + or(i_33, B1, B2); + or(i_34, C1, C2); + + specify + (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI222_X2 (A1, A2, B1, B2, C1, C2, ZN); + + input A1; + input A2; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_30); + and(i_30, i_31, i_34); + and(i_31, i_32, i_33); + or(i_32, A1, A2); + or(i_33, B1, B2); + or(i_34, C1, C2); + + specify + (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI222_X4 (A1, A2, B1, B2, C1, C2, ZN); + + input A1; + input A2; + input B1; + input B2; + input C1; + input C2; + output ZN; + + not(ZN, i_30); + and(i_30, i_31, i_34); + and(i_31, i_32, i_33); + or(i_32, A1, A2); + or(i_33, B1, B2); + or(i_34, C1, C2); + + specify + (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b1) || (A1 == 1'b0) && (B1 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1) || (A1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b1) && (C2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + if((A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b0) && (C2 == 1'b1) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) || (A1 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1) || (A2 == 1'b1) && (B1 == 1'b0) && (C1 == 1'b1) && (C2 == 1'b1)) (B2 => ZN) = (0.1, 0.1); + (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C2 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C2 == 1'b0)) (C1 => ZN) = (0.1, 0.1); + (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b1) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (C1 == 1'b0) || (A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (C1 == 1'b0)) (C2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI22_X1 (A1, A2, B1, B2, ZN); + + input A1; + input A2; + input B1; + input B2; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, i_20); + or(i_19, A1, A2); + or(i_20, B1, B2); + + specify + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI22_X2 (A1, A2, B1, B2, ZN); + + input A1; + input A2; + input B1; + input B2; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, i_20); + or(i_19, A1, A2); + or(i_20, B1, B2); + + specify + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI22_X4 (A1, A2, B1, B2, ZN); + + input A1; + input A2; + input B1; + input B2; + output ZN; + + not(ZN, i_18); + and(i_18, i_19, i_20); + or(i_19, A1, A2); + or(i_20, B1, B2); + + specify + if((A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B2 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b0) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (B1 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OAI33_X1 (A1, A2, A3, B1, B2, B3, ZN); + + input A1; + input A2; + input A3; + input B1; + input B2; + input B3; + output ZN; + + not(ZN, i_30); + and(i_30, i_31, i_33); + or(i_31, i_32, A3); + or(i_32, A1, A2); + or(i_33, i_34, B3); + or(i_34, B1, B2); + + specify + (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b0) || (A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + if((A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) || (A2 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B3 == 1'b1)) (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b0) || (A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) || (A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b1) && (B3 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b1)) (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b1)) (A3 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b1) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (B3 == 1'b1)) (A3 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (A3 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b1) && (B3 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b1)) (A3 => ZN) = (0.1, 0.1); + (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b0) && (B2 == 1'b0) && (B3 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (A3 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B2 == 1'b0) && (B3 == 1'b0)) (B1 => ZN) = (0.1, 0.1); + (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b1) && (B1 == 1'b0) && (B3 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B3 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b0) && (B1 == 1'b0) && (B3 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (A3 == 1'b1) && (B1 == 1'b0) && (B3 == 1'b0)) (B2 => ZN) = (0.1, 0.1); + (B3 => ZN) = (0.1, 0.1); + if((A1 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (B3 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b0) && (B1 == 1'b0) && (B2 == 1'b0) || (A1 == 1'b0) && (A2 == 1'b0) && (A3 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (B3 => ZN) = (0.1, 0.1); + if((A1 == 1'b0) && (A2 == 1'b1) && (A3 == 1'b1) && (B1 == 1'b0) && (B2 == 1'b0)) (B3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR2_X1 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + or(ZN, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR2_X2 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + or(ZN, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR2_X4 (A1, A2, ZN); + + input A1; + input A2; + output ZN; + + or(ZN, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR3_X1 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + or(ZN, i_6, A3); + or(i_6, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR3_X2 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + or(ZN, i_6, A3); + or(i_6, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR3_X4 (A1, A2, A3, ZN); + + input A1; + input A2; + input A3; + output ZN; + + or(ZN, i_6, A3); + or(i_6, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR4_X1 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + or(ZN, i_12, A4); + or(i_12, i_13, A3); + or(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR4_X2 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + or(ZN, i_12, A4); + or(i_12, i_13, A3); + or(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module OR4_X4 (A1, A2, A3, A4, ZN); + + input A1; + input A2; + input A3; + input A4; + output ZN; + + or(ZN, i_12, A4); + or(i_12, i_13, A3); + or(i_13, A1, A2); + + specify + (A1 => ZN) = (0.1, 0.1); + (A2 => ZN) = (0.1, 0.1); + (A3 => ZN) = (0.1, 0.1); + (A4 => ZN) = (0.1, 0.1); + endspecify + +endmodule + +primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN RN nextstate CK NOTIFIER : @IQ : IQ + 1 ? 0 r ? : ? : 0; + ? 1 1 r ? : ? : 1; + 1 ? 0 * ? : 0 : 0; // reduce pessimism + ? 1 1 * ? : 1 : 1; // reduce pessimism + 1 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 1 ? ? ? : ? : 1; // SN activated + * 1 ? ? ? : 1 : 1; // Cover all transitions on SN + ? 0 ? ? ? : ? : 0; // RN activated + 1 * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFFRS_X1 (CK, D, RN, SE, SI, SN, Q, QN); + + input CK; + input D; + input RN; + input SE; + input SI; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, RN, nextstate, CK, NOTIFIER); + and(IQN, i_33, i_34); + not(i_33, IQ); + not(i_34, i_35); + and(i_35, i_36, i_37); + not(i_36, SN); + not(i_37, RN); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_38, i_39); + and(i_38, SE, SI); + and(i_39, D, i_40); + not(i_40, SE); + + and(id_3, SN, RN); + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& id_3, 0.1, 0, NOTIFIER); + $width(posedge CK &&& id_3, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, SN, RN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN RN nextstate CK NOTIFIER : @IQ : IQ + 1 ? 0 r ? : ? : 0; + ? 1 1 r ? : ? : 1; + 1 ? 0 * ? : 0 : 0; // reduce pessimism + ? 1 1 * ? : 1 : 1; // reduce pessimism + 1 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 1 ? ? ? : ? : 1; // SN activated + * 1 ? ? ? : 1 : 1; // Cover all transitions on SN + ? 0 ? ? ? : ? : 0; // RN activated + 1 * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFFRS_X2 (CK, D, RN, SE, SI, SN, Q, QN); + + input CK; + input D; + input RN; + input SE; + input SI; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, RN, nextstate, CK, NOTIFIER); + and(IQN, i_33, i_34); + not(i_33, IQ); + not(i_34, i_35); + and(i_35, i_36, i_37); + not(i_36, SN); + not(i_37, RN); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_38, i_39); + and(i_38, SE, SI); + and(i_39, D, i_40); + not(i_40, SE); + + and(id_3, SN, RN); + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b0)) (RN => Q) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0) && (SN == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b1) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b0)) (SN => QN) = (0.1, 0.1); + if((CK == 1'b0) && (RN == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& id_3, 0.1, 0, NOTIFIER); + $width(posedge CK &&& id_3, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER); + output IQ; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // RN nextstate CK NOTIFIER : @IQ : IQ + ? 0 r ? : ? : 0; + 1 1 r ? : ? : 1; + ? 0 * ? : 0 : 0; // reduce pessimism + 1 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 0; // RN activated + * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFFR_X1 (CK, D, RN, SE, SI, Q, QN); + + input CK; + input D; + input RN; + input SE; + input SI; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, RN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_18, i_19); + and(i_18, SE, SI); + and(i_19, D, i_20); + not(i_20, SE); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + + $width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, RN, nextstate, CK, NOTIFIER); + output IQ; + input RN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // RN nextstate CK NOTIFIER : @IQ : IQ + ? 0 r ? : ? : 0; + 1 1 r ? : ? : 1; + ? 0 * ? : 0 : 0; // reduce pessimism + 1 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 0; // RN activated + * ? ? ? : 0 : 0; // Cover all transitions on RN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFFR_X2 (CK, D, RN, SE, SI, Q, QN); + + input CK; + input D; + input RN; + input SE; + input SI; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, RN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_18, i_19); + and(i_18, SE, SI); + and(i_19, D, i_20); + not(i_20, SE); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (Q +: 1'b0)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge RN => (QN +: 1'b1)) = (0.1, 0.1); + + $width(negedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((RN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $recovery(posedge RN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge RN, 0.1, NOTIFIER); + $width(negedge RN, 0.1, 0, NOTIFIER); + $width(posedge RN, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN nextstate CK NOTIFIER : @IQ : IQ + 1 0 r ? : ? : 0; + ? 1 r ? : ? : 1; + 1 0 * ? : 0 : 0; // reduce pessimism + ? 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 1; // SN activated + * ? ? ? : 1 : 1; // Cover all transitions on SN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFFS_X1 (CK, D, SE, SI, SN, Q, QN); + + input CK; + input D; + input SE; + input SI; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_18, i_19); + and(i_18, SE, SI); + and(i_19, D, i_20); + not(i_20, SE); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, SN, nextstate, CK, NOTIFIER); + output IQ; + input SN; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table + // SN nextstate CK NOTIFIER : @IQ : IQ + 1 0 r ? : ? : 0; + ? 1 r ? : ? : 1; + 1 0 * ? : 0 : 0; // reduce pessimism + ? 1 * ? : 1 : 1; // reduce pessimism + 1 * ? ? : ? : -; // Ignore all edges on nextstate + 1 ? f ? : ? : -; // Ignore non-triggering clock edge + 0 ? ? ? : ? : 1; // SN activated + * ? ? ? : 1 : 1; // Cover all transitions on SN + ? ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFFS_X2 (CK, D, SE, SI, SN, Q, QN); + + input CK; + input D; + input SE; + input SI; + input SN; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, SN, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_18, i_19); + and(i_18, SE, SI); + and(i_19, D, i_20); + not(i_20, SE); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (Q +: 1'b1)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + if((CK == 1'b1)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + if((CK == 1'b0)) (negedge SN => (QN +: 1'b0)) = (0.1, 0.1); + + $width(negedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $width(posedge CK &&& ((SN)), 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + $recovery(posedge SN, posedge CK, 0.1, NOTIFIER); + $hold(posedge CK, posedge SN, 0.1, NOTIFIER); + $width(negedge SN, 0.1, 0, NOTIFIER); + $width(posedge SN, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 r ? : ? : 0; + 1 r ? : ? : 1; + 0 * ? : 0 : 0; // reduce pessimism + 1 * ? : 1 : 1; // reduce pessimism + * ? ? : ? : -; // Ignore all edges on nextstate + ? f ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFF_X1 (CK, D, SE, SI, Q, QN); + + input CK; + input D; + input SE; + input SI; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_18, i_19); + and(i_18, SE, SI); + and(i_19, D, i_20); + not(i_20, SE); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, CK, NOTIFIER); + output IQ; + input nextstate; + input CK; + input NOTIFIER; + reg IQ; + + table +// nextstate CK NOTIFIER : @IQ : IQ + 0 r ? : ? : 0; + 1 r ? : ? : 1; + 0 * ? : 0 : 0; // reduce pessimism + 1 * ? : 1 : 1; // reduce pessimism + * ? ? : ? : -; // Ignore all edges on nextstate + ? f ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module SDFF_X2 (CK, D, SE, SI, Q, QN); + + input CK; + input D; + input SE; + input SI; + output Q; + output QN; + reg NOTIFIER; + + seq3(IQ, nextstate, CK, NOTIFIER); + not(IQN, IQ); + buf(Q, IQ); + buf(QN, IQN); + or(nextstate, i_18, i_19); + and(i_18, SE, SI); + and(i_19, D, i_20); + not(i_20, SE); + + + specify + (posedge CK => (Q +: D)) = (0.1, 0.1); + (posedge CK => (QN -: D)) = (0.1, 0.1); + + $width(negedge CK, 0.1, 0, NOTIFIER); + $width(posedge CK, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SE, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SE, 0.1, 0.1, NOTIFIER); + $width(negedge SE, 0.1, 0, NOTIFIER); + $width(posedge SE, 0.1, 0, NOTIFIER); + $setuphold(posedge CK, negedge SI, 0.1, 0.1, NOTIFIER); + $setuphold(posedge CK, posedge SI, 0.1, 0.1, NOTIFIER); + $width(negedge SI, 0.1, 0, NOTIFIER); + $width(posedge SI, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +module TBUF_X1 (A, EN, Z); + + input A; + input EN; + output Z; + + bufif0(Z, Z_in, Z_enable); + buf(Z_enable, EN); + buf(Z_in, A); + + specify + (A => Z) = (0.1, 0.1); + (EN => Z) = (0.1, 0.1); + endspecify + +endmodule + +module TBUF_X16 (A, EN, Z); + + input A; + input EN; + output Z; + + bufif0(Z, Z_in, Z_enable); + buf(Z_enable, EN); + buf(Z_in, A); + + specify + (A => Z) = (0.1, 0.1); + (EN => Z) = (0.1, 0.1); + endspecify + +endmodule + +module TBUF_X2 (A, EN, Z); + + input A; + input EN; + output Z; + + bufif0(Z, Z_in, Z_enable); + buf(Z_enable, EN); + buf(Z_in, A); + + specify + (A => Z) = (0.1, 0.1); + (EN => Z) = (0.1, 0.1); + endspecify + +endmodule + +module TBUF_X4 (A, EN, Z); + + input A; + input EN; + output Z; + + bufif0(Z, Z_in, Z_enable); + buf(Z_enable, EN); + buf(Z_in, A); + + specify + (A => Z) = (0.1, 0.1); + (EN => Z) = (0.1, 0.1); + endspecify + +endmodule + +module TBUF_X8 (A, EN, Z); + + input A; + input EN; + output Z; + + bufif0(Z, Z_in, Z_enable); + buf(Z_enable, EN); + buf(Z_in, A); + + specify + (A => Z) = (0.1, 0.1); + (EN => Z) = (0.1, 0.1); + endspecify + +endmodule + +module TINV_X1 (EN, I, ZN); + + input EN; + input I; + output ZN; + + bufif0(ZN, ZN_in, ZN_enable); + buf(ZN_enable, EN); + not(ZN_in, I); + + specify + (EN => ZN) = (0.1, 0.1); + (I => ZN) = (0.1, 0.1); + endspecify + +endmodule + +primitive seq3 (IQ, nextstate, G, NOTIFIER); + output IQ; + input nextstate; + input G; + input NOTIFIER; + reg IQ; + + table +// nextstate G NOTIFIER : @IQ : IQ + 0 1 ? : ? : 0; + 1 1 ? : ? : 1; + * ? ? : ? : -; // Ignore all edges on nextstate + ? 0 ? : ? : -; // Ignore non-triggering clock edge + ? ? * : ? : x; // Any NOTIFIER change + endtable +endprimitive + +module TLAT_X1 (D, G, OE, Q); + + input D; + input G; + input OE; + output Q; + reg NOTIFIER; + + bufif0(Q, Q_in, Q_enable); + not(Q_enable, OE); + seq3(IQ, nextstate, G, NOTIFIER); + not(IQN, IQ); + buf(Q_in, IQ); + buf(nextstate, D); + + + specify + (D => Q) = (0.1, 0.1); + (posedge G => (Q +: D)) = (0.1, 0.1); + (OE => Q) = (0.1, 0.1); + + $setuphold(negedge G, negedge D, 0.1, 0.1, NOTIFIER); + $setuphold(negedge G, posedge D, 0.1, 0.1, NOTIFIER); + $width(negedge D, 0.1, 0, NOTIFIER); + $width(posedge D, 0.1, 0, NOTIFIER); + $width(negedge G, 0.1, 0, NOTIFIER); + $width(posedge G, 0.1, 0, NOTIFIER); + $width(negedge OE, 0.1, 0, NOTIFIER); + $width(posedge OE, 0.1, 0, NOTIFIER); + endspecify + +endmodule + +module XNOR2_X1 (A, B, ZN); + + input A; + input B; + output ZN; + + not(ZN, i_46); + xor(i_46, A, B); + + specify + if((B == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0)) (B => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module XNOR2_X2 (A, B, ZN); + + input A; + input B; + output ZN; + + not(ZN, i_46); + xor(i_46, A, B); + + specify + if((B == 1'b0)) (A => ZN) = (0.1, 0.1); + if((B == 1'b1)) (A => ZN) = (0.1, 0.1); + if((A == 1'b1)) (B => ZN) = (0.1, 0.1); + if((A == 1'b0)) (B => ZN) = (0.1, 0.1); + endspecify + +endmodule + +module XOR2_X1 (A, B, Z); + + input A; + input B; + output Z; + + xor(Z, A, B); + + specify + if((B == 1'b0)) (A => Z) = (0.1, 0.1); + if((B == 1'b1)) (A => Z) = (0.1, 0.1); + if((A == 1'b1)) (B => Z) = (0.1, 0.1); + if((A == 1'b0)) (B => Z) = (0.1, 0.1); + endspecify + +endmodule + +module XOR2_X2 (A, B, Z); + + input A; + input B; + output Z; + + xor(Z, A, B); + + specify + if((B == 1'b0)) (A => Z) = (0.1, 0.1); + if((B == 1'b1)) (A => Z) = (0.1, 0.1); + if((A == 1'b1)) (B => Z) = (0.1, 0.1); + if((A == 1'b0)) (B => Z) = (0.1, 0.1); + endspecify + +endmodule + +// +// End of file +// Index: lib/LICENSE =================================================================== --- lib/LICENSE (nonexistent) +++ lib/LICENSE (revision 22) @@ -0,0 +1,16 @@ +The Open Cell Library is intended for use by universities, other research activities, educational programs and Si2.org members. +However allowed, the Open Cell Library is not intended for commercial use. If you use the Open Cell Library for demonstration of commercial EDA tools +it is required to mention, indicate that the library was developped by Nangate. + +If you have questions or concerns then please contact us at openlibrary@nangate.com + +The Open Cell Library is provided by Nangate under the following License: + +Nangate Open Cell Library License, Version 1.0. February 20, 2008 + +Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the Open Cell Library and accompanying documentation (the "Library") covered by this license to use, reproduce, display, distribute, execute, and transmit the Library, and to prepare derivative works of the Library, and to permit third-parties to whom the Library is furnished to do so, all subject to the following: + +The copyright notices in the Library and this entire statement, including the above license grant, this restriction and the following disclaimer, must be included in all copies of the Library, in whole or in part, and all derivative works of the Library, unless such copies or derivative works are solely in the form of machine-executable object code generated by a source language processor. The library has been generated using a non-optimized open PDK and is not suited for any commercial purpose. Measuring or benchmarking the Library against any other library or standard cell set is prohibited. Any meaningful library benchmarking must be done in collaboration with Nangate or other providers of optimized and production-ready PDKs. + +THE LIBRARY IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE LIBRARY BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE LIBRARY OR THE USE OR OTHER DEALINGS IN THE LIBRARY. + Index: lib/Nangate_typ.db =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: lib/Nangate_typ.db =================================================================== --- lib/Nangate_typ.db (nonexistent) +++ lib/Nangate_typ.db (revision 22)

lib/Nangate_typ.db Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: common/src/mrma.v =================================================================== --- common/src/mrma.v (nonexistent) +++ common/src/mrma.v (revision 22) @@ -0,0 +1,111 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Multi-resource match arbiter + *** SystemVerilog is used *** + + References + Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Multi-resource arbiter decomposition, Tech report NCL-EECE-MSD-TR-2009-143, Microelectronic System Design Group, School of EECE, Newcastle University, 2009. + Stanislavs Golubcovs, Delong Shang, Fei Xia, Andrey Mokhov and Alex Yakovlev, Modular approach to multi-resource arbiter design, IEEE Symposium on Asynchronous Circuits and Systems, 2009. + + History: + 05/09/2009 Initial version. + 05/11/2009 Speed up the arbiter. + 24/05/2011 Clean up for opensource. + +*/ + +module mrma (/*AUTOARG*/ + // Outputs + ca, ra, cfg, + // Inputs + c, r, rst_n + ); + + // parameters + parameter N = 2; // the number of requests/clients + parameter M = 2; // the number of resources + + input [N-1:0] c; // requests/clients + output [N-1:0] ca; // requests ack + + input [M-1:0] r; // resources + output [M-1:0] ra; // resource ack + + output [M-1:0][N-1:0] cfg; // the generated configuration + wire [N-1:0][M-1:0] scfg; + + wire [M-1:0][N-1:0] hs; // match results + wire [M-1:0][N-1:0] blk; // blockage + wire [N-1:0][M-1:0] cblk; // shuffled blockage + wire [M-1:0] rblk; // resource blockage + wire [N-1:0] cblk; // client blockage + wire [N-1:0] cg, cm; // client requests + wire [M-1:0] rg, rm; // resource requests + + input rst_n; // active low reset + + // generate variables + genvar i, j; + + + // input arbiters + tree_arb #(N) CIArb ( + .req ( cm ), + .gnt ( cg ) + ); + + tree_arb #(M) RIArb ( + .req ( rm ), + .gnt ( rg ) + ); + + generate + // tile matrix + for (i=0; i + 08/03/2011 Tree arbiter cannot be used as the requests are not allowed to drop before ack. + 24/05/2011 Clean up for opensource. + +*/ + +module mnma(/*AUTOARG*/ + // Outputs + cfg, + // Inputs + r + ); + parameter N = 2; // number of input requests + parameter M = 2; // number of resources + + input [N-1:0][M-1:0] r; // input requests + output [M-1:0][N-1:0] cfg; // configuration to the crssbar + + wire [M-1:0][N-1:0] OPr; + wire [M-1:0][N-1:0] OPg; + wire [M-1:0][N-1:0][M-1:0] OPren; + wire [N-1:0][M-1:0] IPr; + wire [N-1:0][M-1:0] IPg; + + genvar i,j,k; + + //------------------------------------- + // OP arbiters + generate + for(i=0; ik is settle + end + and AND_OPRen (OPr[i][j], r[j][i] ,(~|OPren[i][j])); + assign cfg[i][j] = IPg[j][i]; + assign IPr[j][i] = OPg[i][j]; + end // block: CI + end // block: CO + endgenerate + +endmodule // mnma + + Index: common/src/pipe4.v =================================================================== --- common/src/pipe4.v (nonexistent) +++ common/src/pipe4.v (revision 22) @@ -0,0 +1,75 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + General pipeline stage using the 4-phase 1-of-4 QDI protocol. + *** SystemVerilog is used *** + + History: + 05/05/2009 Initial version. + 17/04/2011 Replace the common ack generation. + 23/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module pipe4(/*AUTOARG*/ + // Outputs + ia, o0, o1, o2, o3, + // Inputs + i0, i1, i2, i3, oa +`ifdef ENABLE_EOF + , i4, o4 +`endif + ); + + parameter DW = 32; // the data width of the pipeline stage + parameter SCN = DW/2; // the number of 1-of-4 sub-stage required + + input [SCN-1:0] i0, i1, i2, i3; + output [SCN-1:0] o0, o1, o2, o3; + input oa; // input ack + output ia; // output ack + +`ifdef ENABLE_EOF + input o4; // the eof bit + output i4; +`endif + + // internal signals + wire [2*SCN-2:0] tack; + + // generate the ack line + genvar i; + + // the data pipe stage + generate for (i=0; i + 20/09/2010 Supporting channel slicing and SDM using macro difinitions. + 23/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module dclos (/*AUTOARG*/ + // Outputs + so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, + eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, wo4, no4, eo4, lo4, sia, + wia, nia, eia, lia, + // Inputs + si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, + ei1, ei2, ei3, li0, li1, li2, li3, si4, wi4, ni4, ei4, li4, soa, + woa, noa, eoa, loa, imcfg, scfg, ncfg, wcfg, ecfg, lcfg + ); + + parameter MN = 2; // number of CMs + parameter NN = 2; // number of ports in an IM or OM, equ. to number of virtual circuits + parameter DW = 8; // datawidth of a single virtual circuit/port + parameter SCN = DW/2; // number of 1-of-4 sub-channels in one port + + input [NN-1:0][SCN-1:0] si0, si1, si2, si3; // south input [0], X+1 + input [NN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input [1], Y-1 + input [NN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input [2], X-1 + input [NN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input [3], Y+1 + input [NN-1:0][SCN-1:0] li0, li1, li2, li3; // local input + output [NN-1:0][SCN-1:0] so0, so1, so2, so3; // south output + output [NN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output + output [NN-1:0][SCN-1:0] no0, no1, no2, no3; // north output + output [NN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output + output [NN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output + + // eof bits and ack lines +`ifdef ENABLE_CHANNEL_SLICING + input [NN-1:0][SCN-1:0] si4, wi4, ni4, ei4, li4; + output [NN-1:0][SCN-1:0] so4, wo4, no4, eo4, lo4; + output [NN-1:0][SCN-1:0] sia, wia, nia, eia, lia; + input [NN-1:0][SCN-1:0] soa, woa, noa, eoa, loa; +`else + input [NN-1:0] si4, wi4, ni4, ei4, li4; + output [NN-1:0] so4, wo4, no4, eo4, lo4; + output [NN-1:0] sia, wia, nia, eia, lia; + input [NN-1:0] soa, woa, noa, eoa, loa; +`endif // !`ifdef ENABLE_CHANNEL_SLICING + + input [4:0][MN-1:0][NN-1:0] imcfg; // configuration for IMs + // configuration for CMs + input [MN-1:0][1:0] scfg, ncfg; + input [MN-1:0][3:0] wcfg, ecfg, lcfg; + // no OMs + + // output of IMs + wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3; + wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3; + wire [MN-1:0][SCN-1:0] imon0, imon1, imon2, imon3; + wire [MN-1:0][SCN-1:0] imoe0, imoe1, imoe2, imoe3; + wire [MN-1:0][SCN-1:0] imol0, imol1, imol2, imol3; +`ifdef ENABLE_CHANNEL_SLICING + wire [MN-1:0][SCN-1:0] imos4, imow4, imon4, imoe4, imol4; + wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola; +`else + wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4; + wire [MN-1:0] imosa, imowa, imona, imoea, imola; +`endif + + // input of CMs + wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3; +`ifdef ENABLE_CHANNEL_SLICING + wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia; +`else + wire [MN-1:0][4:0] cmi4, cmia; +`endif + + // output of CMs + wire [MN-1:0][4:0][SCN-1:0] cmo0, cmo1, cmo2, cmo3; +`ifdef ENABLE_CHANNEL_SLICING + wire [MN-1:0][4:0][SCN-1:0] cmo4, cmoa; +`else + wire [MN-1:0][4:0] cmo4, cmoa; +`endif + + genvar i,j,k; + + dcb #(.NN(NN), .MN(MN), .DW(DW)) + SIM ( + .o0 ( imos0 ), + .o1 ( imos1 ), + .o2 ( imos2 ), + .o3 ( imos3 ), + .o4 ( imos4 ), + .ia ( sia ), + .i0 ( si0 ), + .i1 ( si1 ), + .i2 ( si2 ), + .i3 ( si3 ), + .i4 ( si4 ), + .oa ( imosa ), + .cfg ( imcfg[0] ) + ); + + dcb #(.NN(NN), .MN(MN), .DW(DW)) + WIM ( + .o0 ( imow0 ), + .o1 ( imow1 ), + .o2 ( imow2 ), + .o3 ( imow3 ), + .o4 ( imow4 ), + .ia ( wia ), + .i0 ( wi0 ), + .i1 ( wi1 ), + .i2 ( wi2 ), + .i3 ( wi3 ), + .i4 ( wi4 ), + .oa ( imowa ), + .cfg ( imcfg[1] ) + ); + + dcb #(.NN(NN), .MN(MN), .DW(DW)) + NIM ( + .o0 ( imon0 ), + .o1 ( imon1 ), + .o2 ( imon2 ), + .o3 ( imon3 ), + .o4 ( imon4 ), + .ia ( nia ), + .i0 ( ni0 ), + .i1 ( ni1 ), + .i2 ( ni2 ), + .i3 ( ni3 ), + .i4 ( ni4 ), + .oa ( imona ), + .cfg ( imcfg[2] ) + ); + + dcb #(.NN(NN), .MN(MN), .DW(DW)) + EIM ( + .o0 ( imoe0 ), + .o1 ( imoe1 ), + .o2 ( imoe2 ), + .o3 ( imoe3 ), + .o4 ( imoe4 ), + .ia ( eia ), + .i0 ( ei0 ), + .i1 ( ei1 ), + .i2 ( ei2 ), + .i3 ( ei3 ), + .i4 ( ei4 ), + .oa ( imoea ), + .cfg ( imcfg[3] ) + ); + + dcb #(.NN(NN), .MN(MN), .DW(DW)) + LIM ( + .o0 ( imol0 ), + .o1 ( imol1 ), + .o2 ( imol2 ), + .o3 ( imol3 ), + .o4 ( imol4 ), + .ia ( lia ), + .i0 ( li0 ), + .i1 ( li1 ), + .i2 ( li2 ), + .i3 ( li3 ), + .i4 ( li4 ), + .oa ( imola ), + .cfg ( imcfg[4] ) + ); + + generate for(i=0; i + 23/05/2011 Use SystemVerilog for wire declaration. + 23/05/2011 Clean up for opensource. + +*/ + +module rcb (/*AUTOARG*/ + // Outputs + ira, oreq, + // Inputs + ireq, ora, cfg + ) ; + // parameters + parameter NN = 1; // number of input ports + parameter MN = 1; // number of output ports + parameter DW = 1; // datawidth a port + + input [NN-1:0][DW-1:0] ireq; // input requests + output [NN-1:0] ira; // ack for input requests + output [MN-1:0][DW-1:0] oreq; // output requests + input [DW-1:0] ora; // ack for output requests + input [MN-1:0][NN-1:0] cfg; // the crossbar configuration + + wire [MN-1:0][DW-1:0][NN-1-1:0] m; // the internal wires for requests + wire [NN-1:0][MN-1:0] ma; // the internal wires for acks + + // generate variable + genvar i, j, k; + + // request matrix + generate + for (i=0; i + 23/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module dcb (/*AUTOARG*/ + // Outputs + o0, o1, o2, o3, ia, o4, + // Inputs + i0, i1, i2, i3, oa, i4, cfg + ); + + parameter NN = 2; // number of input ports + parameter MN = 3; // number of output ports + parameter DW = 8; // data-width of a port + parameter SCN = DW/2; // number of 1-of-4 sub-channels for one port + + input [NN-1:0][SCN-1:0] i0, i1, i2, i3; // input ports + output [MN-1:0][SCN-1:0] o0, o1, o2, o3; // output ports + +`ifdef ENABLE_CHANNEL_SLICING + output [NN-1:0][SCN-1:0] ia, o4; // eof and ack + input [MN-1:0][SCN-1:0] oa, i4; +`else + output [NN-1:0] ia, o4; // eof and ack + input [MN-1:0] oa, i4; +`endif + + input [MN-1:0][NN-1:0] cfg; // crossbar configuration + + wire [MN-1:0][SCN-1:0][NN-1:0] dm0, dm1, dm2, dm3; + +`ifdef ENABLE_CHANNEL_SLICING + wire [NN-1:0][SCN-1:0][MN-1:0] am, dm4; +`else + wire [NN-1:0][MN-1:0] am, dm4; +`endif + + genvar i, j, k; + + generate + for(i=0; i + 20/09/2010 Supporting channel slicing and SDM using macro difinitions. + 23/05/2011 Clean up for opensource. + +*/ + +// the router structure definitions +`include "define.v" + +module dcb_xy (/*AUTOARG*/ + // Outputs + so0, so1, so2, so3, wo0, wo1, wo2, wo3, no0, no1, no2, no3, eo0, + eo1, eo2, eo3, lo0, lo1, lo2, lo3, so4, sia, wo4, wia, no4, nia, + eo4, eia, lo4, lia, + // Inputs + si0, si1, si2, si3, wi0, wi1, wi2, wi3, ni0, ni1, ni2, ni3, ei0, + ei1, ei2, ei3, li0, li1, li2, li3, si4, soa, wi4, woa, ni4, noa, + ei4, eoa, li4, loa, scfg, ncfg, wcfg, ecfg, lcfg + ) ; + + parameter VCN = 1; // number of virtual circuits per port + parameter VCW = 8; // the datawidth of a single virtual circuit + parameter SCN = VCW/2; // number of 1-of-4 sub-channels in one virtual circuit + + input [VCN-1:0][SCN-1:0] si0, si1, si2, si3; // south input, X+1 + output [VCN-1:0][SCN-1:0] so0, so1, so2, so3; // south output + input [VCN-1:0][SCN-1:0] wi0, wi1, wi2, wi3; // west input, Y-1 + output [VCN-1:0][SCN-1:0] wo0, wo1, wo2, wo3; // west output + input [VCN-1:0][SCN-1:0] ni0, ni1, ni2, ni3; // north input, X-1 + output [VCN-1:0][SCN-1:0] no0, no1, no2, no3; // north output + input [VCN-1:0][SCN-1:0] ei0, ei1, ei2, ei3; // east input, Y+1 + output [VCN-1:0][SCN-1:0] eo0, eo1, eo2, eo3; // east output + input [VCN-1:0][SCN-1:0] li0, li1, li2, li3; // local input + output [VCN-1:0][SCN-1:0] lo0, lo1, lo2, lo3; // local output + + // ack and eof bits +`ifdef ENABLE_CHANNEL_SLICING + input [VCN-1:0][SCN-1:0] si4, soa; + output [VCN-1:0][SCN-1:0] so4, sia; + input [VCN-1:0][SCN-1:0] wi4, woa; + output [VCN-1:0][SCN-1:0] wo4, wia; + input [VCN-1:0][SCN-1:0] ni4, noa; + output [VCN-1:0][SCN-1:0] no4, nia; + input [VCN-1:0][SCN-1:0] ei4, eoa; + output [VCN-1:0][SCN-1:0] eo4, eia; + input [VCN-1:0][SCN-1:0] li4, loa; + output [VCN-1:0][SCN-1:0] lo4, lia; +`else // !`ifdef ENABLE_CHANNEL_SLICING + input [VCN-1:0] si4, soa; + output [VCN-1:0] so4, sia; + input [VCN-1:0] wi4, woa; + output [VCN-1:0] wo4, wia; + input [VCN-1:0] ni4, noa; + output [VCN-1:0] no4, nia; + input [VCN-1:0] ei4, eoa; + output [VCN-1:0] eo4, eia; + input [VCN-1:0] li4, loa; + output [VCN-1:0] lo4, lia; +`endif + + // configurations + input [VCN-1:0][1:0][VCN-1:0] scfg, ncfg; + input [VCN-1:0][3:0][VCN-1:0] wcfg, ecfg, lcfg; + + + // ANDed wires + wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos0, tos1, tos2, tos3; // the wires to the south output port + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow0, tow1, tow2, tow3; // the wires to the west output port + wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton0, ton1, ton2, ton3; // the wires to the north output port + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe0, toe1, toe2, toe3; // the wires to the east output port + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol0, tol1, tol2, tol3; // the wires to the local output port + +`ifdef ENABLE_CHANNEL_SLICING + wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] tos4, tosa; // the wires to the south output port + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tow4, towa; // the wires to the west output port + wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] ton4, tona; // the wires to the north output port + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] toe4, toea; // the wires to the east output port + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] tol4, tola; // the wires to the local output port + + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] isa; // ack back to south + wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iwa; // ack back to west + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ina; // ack back to north + wire [VCN-1:0][SCN-1:0][1:0][VCN-1:0] iea; // ack back to east + wire [VCN-1:0][SCN-1:0][3:0][VCN-1:0] ila; // ack back to local + +`else // !`ifdef ENABLE_CHANNEL_SLICING + wire [VCN-1:0][1:0][VCN-1:0] tos4, tosa; // the wires to the south output port + wire [VCN-1:0][3:0][VCN-1:0] tow4, towa; // the wires to the west output port + wire [VCN-1:0][1:0][VCN-1:0] ton4, tona; // the wires to the north output port + wire [VCN-1:0][3:0][VCN-1:0] toe4, toea; // the wires to the east output port + wire [VCN-1:0][3:0][VCN-1:0] tol4, tola; // the wires to the local output port + + wire [VCN-1:0][3:0][VCN-1:0] isa; // ack back to south + wire [VCN-1:0][1:0][VCN-1:0] iwa; // ack back to west + wire [VCN-1:0][3:0][VCN-1:0] ina; // ack back to north + wire [VCN-1:0][1:0][VCN-1:0] iea; // ack back to east + wire [VCN-1:0][3:0][VCN-1:0] ila; // ack back to local + +`endif // !`ifdef ENABLE_CHANNEL_SLICING + + // generate + genvar i, j, k; + + + /*---------------------------- SOUTH OUPUT -------------------------------------*/ + generate for (i=0; i

common/src/dcb_xy.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: common/src/ctree.v =================================================================== --- common/src/ctree.v (nonexistent) +++ common/src/ctree.v (revision 22) @@ -0,0 +1,45 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + C-element tree, usually for common ack generation. + *** SystemVerilog is used *** + + History: + 17/04/2011 Initial version. + 23/05/2011 Clean up for opensource. + +*/ + +module ctree (/*AUTOARG*/ + // Outputs + co, + // Inputs + ci + ); + + parameter DW = 2; // the total number of leaves of the C-element tree + + input [DW-1:0] ci; // all input leaves + output co; // the combined output + + wire [2*DW-2:0] dat; + genvar i; + + assign dat[DW-1:0] = ci; + + generate for (i=0; i + 23/05/2011 Clean up for opensource. + +*/ + +module tree_arb (/*AUTOARG*/ + // Outputs + gnt, + // Inputs + req + ) ; + + // parameters + parameter MR = 2; // the number of request inputs + localparam TrLev = mlog2(MR)-1; // the number of levels of the tree + input [MR-1:0] req; // the request input + output [MR-1:0] gnt; // the grant output + + // generate variables + genvar i, j, k; + + // internal wires + wire [MR*2:0] mreq; // the internal request lines + wire [MR*2:0] mgnt; // the internal gnt lines + wire [1:0] rgnt; // the positive gnt of the root mutex + + // the hardware block + generate + if (MR == 1) // special case: only one input + begin: MA_1 + assign gnt = req; + end + else if(MR == 2) // special case: only two input + begin: MA_2 + mutex ME0 ( + .a ( req[0] ), + .b ( req[1] ), + .qa ( gnt[0] ), + .qb ( gnt[1] ) + ); + end + else + begin: MA_N + + mutex ME0 ( + .a ( mreq[0] ), + .b ( mreq[1] ), + .qa ( rgnt[0] ), + .qb ( rgnt[1] ) + ); + + assign mgnt[1:0] = ~rgnt; + + for (i=1; 2**(i+1) + 23/05/2011 Clean up for opensource. + +*/ + +module mutex_arb (/*AUTOARG*/ + // Outputs + gnt, + // Inputs + req + ); + + parameter wd = 4; // the number of request inputs + + input [wd-1:0] req; + output [wd-1:0] gnt; + + genvar i,j; + + wire [wd-1:0] arb_w [wd-1:0]; + wire [wd-1:0] gnt; + + generate + for(i=0; i + 20/05/2011 Change to general verilog description for opensource. + The Nangate cell library is used. + +*/ + +// General 2-input C-element +module c2 (a0, a1, q); + + input a0, a1; // two inputs + output q; // output + + wire [2:0] m; // internal wires + + nand U1 (m[0], a0, a1); + nand U2 (m[1], a0, q); + nand U3 (m[2], a1, q); + assign q = &m; + +endmodule + +// the 2-input C-element on data paths, different name for easy synthesis scription +module dc2 (d, a, q); + + input d; // data input + input a; // ack input + output q; // data output + + wire [2:0] m; // internal wires + + nand U1 (m[0], a, d); + nand U2 (m[1], d, q); + nand U3 (m[2], a, q); + assign q = &m; + +endmodule + +// 2-input C-element with a minus input +module c2n (a, b, q); + + input a; // the normal input + input b; // the minus input + output q; // output + + wire m; // internal wire + + and U1 (m, b, q); + or U2 (q, m, a); + +endmodule + +// 2-input C-element with a plus input +module c2p (a, b, q); + + input a; // the normal input + input b; // the plus input + output q; // output + + wire m; // internal wire + + or U1 (m, b, q); + and U2 (q, m, a); + +endmodule + +// 2-input MUTEX cell, Nangate +module mutex ( a, b, qa, qb ); // !!! dont touch !!! + + input a, b; // request inputs + output qa, qb; // grant outputs + + wire qan, qbn; // internal wires + + NAND2_X2 U1 ( .A1(a), .A2(qbn), .ZN(qan) ); // different driving strength for fast convergence + NOR3_X2 U2 ( .A1(qbn), .A2(qbn), .A3(qbn), .ZN(qb) ); // pulse filter + NOR3_X2 U3 ( .A1(qan), .A2(qan), .A3(qan), .ZN(qa) ); // pulse filter + NAND2_X1 U4 ( .A1(b), .A2(qan), .ZN(qbn) ); + +endmodule + +// 3-input C-element with a plus input +module c2p1 (a0, a1, b, q); + + input a0, a1; // normal inputs + input b; // plus input + output q; // output + + wire [2:0] m; // internal wires + + nand U1 (m[0], a0, a1, b); + nand U2 (m[1], a0, q); + nand U3 (m[2], a1, q); + assign q = &m; + +endmodule + +// the basic element of a tree arbiter +module tarb ( ngnt, ntgnt, req, treq ); + + input [1:0] req; // request input + output [1:0] ngnt; // the negative grant output + output treq; // combined request output + input ntgnt; // the negative combined grant input + + wire n1, n2; // internal wires + wire [1:0] mgnt; // outputs of the MUTEX + + mutex ME ( .a(req[0]), .b(req[1]), .qa(mgnt[0]), .qb(mgnt[1]) ); + c2n C0 ( .a(ntgnt), .b(n2), .q(ngnt[0]) ); + c2n C1 ( .a(ntgnt), .b(n1), .q(ngnt[1]) ); + nand U1 (treq, n1, n2); + nand U2 (n1, ngnt[0], mgnt[1]); + nand U3 (n2, ngnt[1], mgnt[0]); +endmodule + +// the tile in a multi-resource arbiter +module cr_blk ( bo, hs, cbi, rbi, rg, cg ); + + input rg, cg; // input requests + input cbi, rbi; // input blockage + output bo; // output blockage + output hs; // match result + + wire blk; // internal wire + + c2p1 XG ( .a0(rg), .a1(cg), .b(blk), .q(bo) ); + c2p1 HG ( .a0(cbi), .a1(rbi), .b(bo), .q(hs) ); + nor U1 (blk, rbi, cbi); + +endmodule + +// a data latch template, Nangate +module dlatch ( q, qb, d, g); + output q, qb; + input d, g; + + DLH_X1 U1 (.Q(q), .D(d), .G(g)); +endmodule + +// a delay line, Nangate +module delay (q, a); + input a; + output q; + + BUF_X2 U (.Z(q), .A(a)); +endmodule + + \ No newline at end of file Index: common/script/cell_constraint.tcl =================================================================== --- common/script/cell_constraint.tcl (nonexistent) +++ common/script/cell_constraint.tcl (revision 22) @@ -0,0 +1,71 @@ +# Asynchronous SDM NoC +# (C)2011 Wei Song +# Advanced Processor Technologies Group +# Computer Science, the Univ. of Manchester, UK +# +# Authors: +# Wei Song wsong83@gmail.com +# +# License: LGPL 3.0 or later +# +# Disable the timing loops in asynchronous cells +# currently using the Nangate 45nm cell lib. +# +# History: +# 03/07/2009 Initial version. +# 21/05/2011 Change to the Nangate cell library. + +set_dont_touch mutex +set_dont_touch delay + +uniquify -force + +# C-gates on control path +foreach_in_collection celln [get_references -hierarchical c2_*] { + set_disable_timing [get_object_name $celln]/U2 -from B -to Z + set_disable_timing [get_object_name $celln]/U3 -from B -to Z +} + +# C-gates on data path, feedback and data input are disabled from timing analysis +foreach_in_collection celln [get_references -hierarchical dc2_*] { + set_disable_timing [get_object_name $celln]/U1 -from B -to Z + set_disable_timing [get_object_name $celln]/U2 -from A -to Z + set_disable_timing [get_object_name $celln]/U2 -from B -to Z + set_disable_timing [get_object_name $celln]/U3 -from B -to Z +} + +# c2n gates +foreach_in_collection celln [get_references -hierarchical c2n_*] { + set_disable_timing [get_object_name $celln]/U1 -from B -to Z +} + +# c2p gates +foreach_in_collection celln [get_references -hierarchical c2p_*] { + set_disable_timing [get_object_name $celln]/U1 -from B -to O +} + +# mutex gates +foreach_in_collection celln [get_references -hierarchical mutex_*] { + set_disable_timing [get_object_name $celln]/U1 -from A2 -to ZN + set_disable_timing [get_object_name $celln]/U4 -from A2 -to ZN + set_dont_touch [get_object_name $celln]/U2 + set_dont_touch [get_object_name $celln]/U3 +} + +# c2p1 gates +foreach_in_collection celln [get_references -hierarchical c2p1_*] { + set_disable_timing [get_object_name $celln]/U2 -from B -to Z + set_disable_timing [get_object_name $celln]/U3 -from B -to Z +} + +# tarb +foreach_in_collection celln [get_references -hierarchical tarb_*] { + set_disable_timing [get_object_name $celln]/U2 -from A -to Z + set_disable_timing [get_object_name $celln]/U3 -from A -to Z +} + +# cr_blk +foreach_in_collection celln [get_references -hierarchical cr_blk_*] { + set_disable_timing [get_object_name $celln]/XG/U1 -from C -to Z +} + Index: common/script/tech.tcl =================================================================== --- common/script/tech.tcl (nonexistent) +++ common/script/tech.tcl (revision 22) @@ -0,0 +1,28 @@ +# Asynchronous SDM NoC +# (C)2011 Wei Song +# Advanced Processor Technologies Group +# Computer Science, the Univ. of Manchester, UK +# +# Authors: +# Wei Song wsong83@gmail.com +# +# License: LGPL 3.0 or later +# +# Script for cell library setting up. +# currently using the Nangate 45nm cell lib. +# +# History: +# 05/07/2009 Initial version. +# 20/05/2011 Change to the Nangate cell library. + +set rm_lib_dirs "../../lib" + +set rm_library "Nangate_typ.db" + +set search_path [concat ${search_path} "${rm_lib_dirs}/"] + +set synthetic_library dw_foundation.sldb +set link_library [list *] +set link_library [concat ${link_library} ${rm_library} $synthetic_library] +set target_library "${rm_library}" + Index: vc/define.v =================================================================== --- vc/define.v (nonexistent) +++ vc/define.v (revision 22) @@ -0,0 +1,20 @@ +/* + Asynchronous SDM NoC + (C)2011 Wei Song + Advanced Processor Technologies Group + Computer Science, the Univ. of Manchester, UK + + Authors: + Wei Song wsong83@gmail.com + + License: LGPL 3.0 or later + + Router configuration header file for VC routers. + + History: + 20/09/2009 Initial version. + 23/05/2011 Clean up for opensource. + +*/ + +// currently VC router does not have any configurable structure variables Index: README ===================================================================

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