OpenCores
URL https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk

Subversion Repositories async_sdm_noc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /async_sdm_noc
    from Rev 26 to Rev 27
    ↔ Reverse comparison
  •

Rev 26 → Rev 27

/branches/init/sdm/src/clos_sch.v
21,7 → 21,7
10/06/2010 Change to use PIM structure <wsong83@gmail.com>
23/08/2010 Fix the non-QDI request withdraw process <wsong83@gmail.com>
23/09/2010 Modified for Clos SDM router <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
88,7 → 88,7
.ira ( cmra[0] ),
.oreq ( sr ),
.ora ( sra ),
.gnt ( imc[0] )
.cfg ( imc[0] )
);
 
// the C-element to force the request withdrawal sequence
113,7 → 113,7
.ira ( cmra[1] ),
.oreq ( wr ),
.ora ( wra ),
.gnt ( imc[1] )
.cfg ( imc[1] )
);
 
generate for(i=0; i<N; i++) begin: WA
137,7 → 137,7
.ira ( cmra[2] ),
.oreq ( nr ),
.ora ( nra ),
.gnt ( imc[2] )
.cfg ( imc[2] )
);
 
generate for(i=0; i<N; i++) begin: NA
161,7 → 161,7
.ira ( cmra[3] ),
.oreq ( er ),
.ora ( era ),
.gnt ( imc[3] )
.cfg ( imc[3] )
);
 
generate for(i=0; i<N; i++) begin: EA
185,7 → 185,7
.ira ( cmra[4] ),
.oreq ( lr ),
.ora ( lra ),
.gnt ( imc[4] )
.cfg ( imc[4] )
);
 
generate for(i=0; i<N; i++) begin: LA
/branches/init/sdm/src/im_alloc.v
22,7 → 22,7
05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
10/06/2010 [Major] change to use PIM structure. <wsong83@gmail.com>
23/08/2010 Fix the non-QDI request withdraw process. <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
118,6 → 118,9
assign IPr[i] = |IMr[i];
end
endgenerate
assign OPrst_n[0] = rst_n;
`endif // !`ifndef ENABLE_MRMA
endmodule // im_alloc
/branches/init/sdm/src/sdm_sch.v
18,7 → 18,7
History:
28/09/2009 Initial version. <wsong83@gmail.com>
25/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
229,13 → 229,15
generate
for(i=0; i<VCN; i++) begin: OPC
delay DLY ( .q(OPrst_n[i+1]), .a(OPrst_n[i])); // dont touch
assign SOPrdy[i] = (~SOPblk[i])&SOPrst_n[i+1];
assign WOPrdy[i] = (~WOPblk[i])&WOPrst_n[i+1];
assign NOPrdy[i] = (~NOPblk[i])&NOPrst_n[i+1];
assign EOPrdy[i] = (~EOPblk[i])&EOPrst_n[i+1];
assign LOPrdy[i] = (~LOPblk[i])&LOPrst_n[i+1];
assign SOPrdy[i] = (~SOPblk[i])&OPrst_n[i+1];
assign WOPrdy[i] = (~WOPblk[i])&OPrst_n[i+1];
assign NOPrdy[i] = (~NOPblk[i])&OPrst_n[i+1];
assign EOPrdy[i] = (~EOPblk[i])&OPrst_n[i+1];
assign LOPrdy[i] = (~LOPblk[i])&OPrst_n[i+1];
end
endgenerate
 
assign OPrst_n[0] = rst_n;
`endif // !`ifndef ENABLE_MRMA
/branches/init/common/script/cell_constraint.tcl
13,7 → 13,7
#
# History:
# 03/07/2009 Initial version. <wsong83@gmail.com>
# 21/05/2011 Change to the Nangate cell library. <wsong83@gmail.com>
# 27/05/2011 Change to the Nangate cell library. <wsong83@gmail.com>
 
set_dont_touch mutex2
set_dont_touch delay
75,6 → 75,13
}
# It is not a problem if MRMA is not used in the design.
 
# mrma multi-resource match arbiter
foreach_in_collection celln [get_references -hierarchical mrma_*] {
set_disable_timing [get_object_name $celln]/*.AND_*G* -from B -to Z
set_disable_timing [get_object_name $celln]/*.AND_RG* -from A -to Z
}
# It is not a problem if MRMA is not used in the design.
 
# dcb data crossbar
foreach_in_collection celln [get_references -hierarchical dcb_*] {
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
85,3 → 92,9
set_disable_timing [get_object_name $celln]/*.A* -from B -to Z
}
#It is not a problem if there is no rcb modules in the design.
 
# mnmr m-n match allocator
foreach_in_collection celln [get_references -hierarchical mnma_*] {
set_disable_timing [get_object_name $celln]/*.AND_OPRen* -from B -to Z
}
#It is not a problem if MNMA is not used in the design.
/branches/init/common/src/mrma.v
19,7 → 19,7
History:
05/09/2009 Initial version. <wsong83@gmail.com>
05/11/2009 Speed up the arbiter. <wsong83@gmail.com>
24/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
88,7 → 88,7
assign scfg[j][i] = cfg[i][j];
// store the match results
c2p C (.q(cfg[i][j]), .a0(c[j]), .a1(hs[i][j]));
c2p C (.q(cfg[i][j]), .a(c[j]), .b(hs[i][j]));
end // block: Clm
end // block: Row
/branches/init/common/src/rcb.v
15,7 → 15,7
History:
10/12/2009 Initial version. <wsong83@gmail.com>
23/05/2011 Use SystemVerilog for wire declaration. <wsong83@gmail.com>
23/05/2011 Clean up for opensource. <wsong83@gmail.com>
27/05/2011 Clean up for opensource. <wsong83@gmail.com>
*/
 
33,11 → 33,11
input [NN-1:0][DW-1:0] ireq; // input requests
output [NN-1:0] ira; // ack for input requests
output [MN-1:0][DW-1:0] oreq; // output requests
input [DW-1:0] ora; // ack for output requests
input [MN-1:0] ora; // ack for output requests
input [MN-1:0][NN-1:0] cfg; // the crossbar configuration
wire [MN-1:0][DW-1:0][NN-1-1:0] m; // the internal wires for requests
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
wire [MN-1:0][DW-1:0][NN-1:0] m; // the internal wires for requests
wire [NN-1:0][MN-1:0] ma; // the internal wires for acks
// generate variable
genvar i, j, k;
45,8 → 45,8
// request matrix
generate
for (i=0; i<MN; i++) begin: EN
for (j=0; j<DW; j=j+1) begin: SC
for (k=0; k<NN; k=k+1) begin: IP
for (j=0; j<DW; j++) begin: SC
for (k=0; k<NN; k++) begin: IP
and AC (m[i][j][k], ireq[k][j], cfg[i][k]);
end
58,8 → 58,8
 
// ack matrix
generate
for (k=0; k<NN; k=k+1) begin: ENA
for (i=0; i<MN; i=i+1) begin: OP
for (k=0; k<NN; k++) begin: ENA
for (i=0; i<MN; i++) begin: OP
and AC (ma[k][i], ora[i], cfg[i][k]);
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.