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https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc
- from Rev 34 to Rev 35
- ↔ Reverse comparison
Rev 34 → Rev 35
/branches/init/sdm/define.h
34,7 → 34,7
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const unsigned int BufDepth = 1; // the depth of the input buffer (only useful in VC routers to determine the inital tokens in output ports) |
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const double FFreq = 0.1; // Node injection rate, in unit of MFlit/second |
const double FFreq = 0.1; // Node injection rate, in unit of MFlit/second, 0 means the maximal inject rate |
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const double Record_Period = 1e3 * 1e3; // the interval of recording the average performance to log files, in unit of ps |
const double Warm_UP = 0e4 * 1e3; // the warm up time of performance analysis, in unit of ps |
/branches/init/sdm/tb/rtdriver.cpp
170,7 → 170,7
wait(0.2, SC_NS); // a delay to avoid data override |
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// clear the eof |
rtid4.write(~mdata4); |
rtid4.write(mdata4); |
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// wait for the input port be ready again |
wait(rtinp_sig.negedge_event()); |
/branches/init/sdm/src/im_alloc.v
90,7 → 90,7
`else |
assign IPr[i][j] = |IPrm[i][j]; |
for(k=0; k<SN; k++) begin: DIRC |
c2p IPRen (.q(IPrm[i][j][k]), .a0(IMr[i][k]), .a1(~CMs[j][k])); |
c2p IPRen (.q(IPrm[i][j][k]), .a(IMr[i][k]), .b(~CMs[j][k])); |
end |
`endif |
end |
/branches/init/sdm/syn/script/constraint.tcl
41,7 → 41,7
# the delay cell in the lookahead pipeline |
# It is not a problem to get errors here if ENABLE_LOOKAHEAD is not defined. |
foreach_in_collection celln [get_references -hierarchical outp_buf_*] { |
set_disable_timing [get_object_name $celln]/DLY/U -from A -to Z |
set_disable_timing [get_object_name $celln]/*DLY/U -from A -to Z |
} |
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# set some timing path ending points |
61,8 → 61,8
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# set the timing constraints for data paths and ack paths |
# For better speed performance, please tune these delay and factors according different cell libraries |
set DATA_dly 5 |
set ACK_dly 8 |
set DATA_dly 1.0 |
set ACK_dly 1.6 |
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set_max_delay [expr ${DATA_dly} * 1.00] -from ${DPA} -to ${DPD} -group G_DATA |
set_max_delay [expr ${ACK_dly} * 1.00] -from ${DPA} -to ${DPA} -group G_ACK |
81,4 → 81,4
set_max_area 0 |
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# timing path disabled by user constraints |
suppress_message TIM-175 |
suppress_message TIM-175 |
/branches/init/common/src/cell_lib.v
16,7 → 16,7
05/05/2009 Initial version. <wsong83@gmail.com> |
20/05/2011 Change to general verilog description for opensource. |
The Nangate cell library is used. <wsong83@gmail.com> |
31/05/2011 The bugs in the C2 description is fixed. <wsong83@gmail.com> |
01/06/2011 The bugs in the C2 and C2P1 gates are fixed. <wsong83@gmail.com> |
*/ |
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// General 2-input C-element |
105,7 → 105,7
nand U1 (m[0], a0, a1, b); |
nand U2 (m[1], a0, q); |
nand U3 (m[2], a1, q); |
assign q = &m; |
assign q = ~&m; |
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endmodule |
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