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https://opencores.org/ocsvn/async_sdm_noc/async_sdm_noc/trunk
Subversion Repositories async_sdm_noc
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- This comparison shows the changes necessary to convert path
/async_sdm_noc
- from Rev 66 to Rev 67
- ↔ Reverse comparison
Rev 66 → Rev 67
/branches/clos_opt/common/src/ppc.v
21,16 → 21,16
|
module ppc(/*AUTOARG*/ |
// Outputs |
decan, |
deca, dia, |
// Inputs |
eof, doa |
eof, doa, dec |
); |
input eof, doa; |
wire deca; // the ack to eof |
output decan; // the ack to routing requests |
input eof, doa, dec; |
output deca; // the ack to eof |
output dia; // the pipe stage input ack |
|
c2p CEoF (.q(deca), .a(doa), .b(eof)); |
assign decan = ~deca; |
c2n CDIA (.q(dia), .a(eof|doa), .b(dec&(~deca))); |
|
endmodule // ppc |
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/branches/clos_opt/common/src/dclos.v
35,6 → 35,7
`ifdef ENABLE_BUFFERED_CLOS |
, soa4, woa4, noa4, eoa4, loa4 |
`endif |
, rst_n |
); |
|
parameter MN = 2; // number of CMs |
78,6 → 79,8
input [MN-1:0][3:0] wcfg, ecfg, lcfg; |
// no OMs |
|
input rst_n; // globale active low reset |
|
// output of IMs |
wire [MN-1:0][SCN-1:0] imos0, imos1, imos2, imos3; |
wire [MN-1:0][SCN-1:0] imow0, imow1, imow2, imow3; |
89,12 → 92,16
wire [MN-1:0][SCN-1:0] imosa, imowa, imona, imoea, imola; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0][SCN-1:0] imosa4, imowa4, imona4, imoea4, imola4; |
wire [MN-1:0][SCN-1:0] imosdeca, imowdeca, imondeca, imoedeca, imoldeca; |
wire [MN-1:0][SCN-1:0] imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan; |
`endif |
`else |
wire [MN-1:0] imos4, imow4, imon4, imoe4, imol4; |
wire [MN-1:0] imosa, imowa, imona, imoea, imola; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0] imosdeca, imowdeca, imondeca, imoedeca, imoldeca; |
wire [MN-1:0] imosa4, imowa4, imona4, imoea4, imola4; |
wire [MN-1:0] imoseofan, imoweofan, imoneofan, imoeeofan, imoleofan; |
`endif |
`endif |
|
102,8 → 109,14
wire [MN-1:0][4:0][SCN-1:0] cmi0, cmi1, cmi2, cmi3; |
`ifdef ENABLE_CHANNEL_SLICING |
wire [MN-1:0][4:0][SCN-1:0] cmi4, cmia; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0][4:0][SCN-1:0] cmian; |
`endif |
`else |
wire [MN-1:0][4:0] cmi4, cmia; |
`ifdef ENABLE_BUFFERED_CLOS |
wire [MN-1:0][4:0] cmian; |
`endif |
`endif |
|
// output of CMs |
226,7 → 239,7
`ifdef ENABLE_BUFFERED_CLOS |
// the buffer stage between IM and CM |
`ifdef ENABLE_CHANNEL_SLICING |
for(j=0; j<SCN; j++) begin:SC |
for(j=0; j<SCN; j++) begin:SC_S |
pipe4 #(.DW(2)) |
P ( |
.o0 ( cmi0[i][0] ), |
240,17 → 253,34
.i3 ( imos4[i] ), |
.oa ( cmian[i][0] ) |
); |
|
|
pipen #(.DW(1)) |
PEoF ( |
.d_in_a ( imosa4[i] ), |
.d_out ( cmi4[i][0] ), |
.d_in ( imos4[i] ), |
.d_out_a ( cmian[i][0] ), |
.d_in_a ( ), // imosa4[i] ), |
.d_out ( cmi4[i][0] ), |
.d_in ( imos4[i] ), |
.d_out_a ( imoseofan[i] ), |
); |
|
ppc PCTL ( |
.deca ( imosdeca[i] ), |
.dia ( imosa4[i] ), |
.eof ( cmi4[i][0] ), |
.doa ( cmia[i][0] ), |
.dec ( |
); |
|
assign cmian[i][0] = (~cmia[i][0])&rst_n; |
assign imoseofan[i] = (imosdeca[i])&rst_n; |
end // block: SC |
|
pipen #(.DW(4)) |
S_PDIR ( |
.d_in_a ( |
|
|
|
|
`else |
// shuffle the interconnects between IMs and CMs |
assign cmi0[i][0] = imos0[i]; |