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    /ata/trunk/syn/bin
    from Rev 16 to Rev 33
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Rev 16 → Rev 33

/read.dc
0,0 → 1,66
###############################################################################
#
# Pre Synthesis Script
#
# This script only reads in the design and saves it in a DB file
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Design Parameters
source ../bin/design_spec.dc
 
# ==============================================
# Setup Libraries
source ../bin/lib_spec.dc
 
# ==============================================
# Setup IO Files
 
append log_file ../log/$active_design "_pre.log"
append pre_comp_db_file ../out/$design_name "_pre.db"
 
sh rm -f $log_file
 
# ==============================================
# Setup Misc Variables
 
set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
 
# ==============================================
# Read Design
 
echo "+++++++++ Analyzing all design files ..." >> $log_file
 
foreach module $design_files {
echo "+++++++++ Reading: $module" >> $log_file
echo +++++++++ Reading: $module
set module_file_name ""
append module_file_name $module ".v"
analyze -f verilog $module_file_name >> $log_file
elaborate $module >> $log_file
}
 
current_design $active_design
 
echo "+++++++++ Linking Design ..." >> $log_file
link >> $log_file
 
echo "+++++++++ Uniquifying Design ..." >> $log_file
uniquify >> $log_file
 
echo "+++++++++ Checking Design ..." >> $log_file
check_design >> $log_file
 
# ==============================================
# Save Design
echo "+++++++++ Saving Design ..." >> $log_file
write_file -hierarchy -format db -output $pre_comp_db_file
 
/comp.dc
0,0 → 1,120
###############################################################################
#
# Actual Synthesis Script
#
# This script does the actual synthesis
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Design Parameters
source ../bin/design_spec.dc
 
# ==============================================
# Setup Libraries
source ../bin/lib_spec.dc
 
# ==============================================
# Setup IO Files
 
append log_file ../log/$active_design "_cmp.log"
append pre_comp_db_file ../out/$design_name "_pre.db"
append post_comp_db_file ../out/$design_name ".db"
append post_syn_verilog_file ../out/$design_name "_ps.v"
set junk_file /dev/null
 
sh rm -f $log_file
 
# ==============================================
# Setup Misc Variables
 
set hdlin_enable_vpp true ;# Important - this enables 'ifdefs
 
# ==============================================
# Read Design
 
echo "+++++++++ Reading Design ..." >> $log_file
read_file $pre_comp_db_file >> $log_file
 
# ==============================================
# Operating conditions
 
echo "+++++++++ Setting up Operation Conditions ..." >> $log_file
current_design $design_name
set_operating_conditions WORST >> $log_file
 
# Turn off automatic wire load selection, as this
# always (WHY ???) defaults to "zero_load"
#set auto_wire_load_selection false
#set_wire_load_mode enclosed >> $log_file
#set_wire_load_mode top >> $log_file
#set_wire_load_model -name suggested_40K >> $log_file
 
# ==============================================
# Setup Clocks and Resets
 
echo "+++++++++ Setting up Clocks ..." >> $log_file
 
set_drive 0 [find port {*clk*}]
# !!! WISHBONE Clock !!!
set clock_period 5
create_clock -period $clock_period wb_clk_i
set_clock_skew -uncertainty 0.1 wb_clk_i
set_clock_transition 0.5 wb_clk_i
set_dont_touch_network wb_clk_i
# !!! Reset !!!
set_drive 0 [find port {*rst*}]
set_dont_touch_network [find port {*rst*}]
 
# ==============================================
# Setup IOs
 
echo "+++++++++ Setting up IOs ..." >> $log_file
 
set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file
set_load 0.2 [all_outputs]
 
set_input_delay -max 1 -clock wb_clk_i [all_inputs]
set_output_delay -max 1 -clock wb_clk_i [all_outputs]
 
# ==============================================
# Setup Area Constrains
set_max_area 0.0
 
# ==============================================
# Force Ultra
set_ultra_optimization -f
 
# ==============================================
# Compile Design
 
echo "+++++++++ Starting Compile ..." >> $log_file
compile -map_effort medium -area_effort medium -ungroup_all >> $log_file
#compile -map_effort low -area_effort low >> $log_file
#compile -map_effort high -area_effort high -ungroup_all >> $log_file
#compile -map_effort high -area_effort high -auto_ungroup >> $log_file
 
# ==============================================
# Write Out the optimized design
 
echo "+++++++++ Saving Optimized Design ..." >> $log_file
write_file -format verilog -output $post_syn_verilog_file
write_file -hierarchy -format db -output $post_comp_db_file
 
# ==============================================
# Create Some Basic Reports
 
echo "+++++++++ Reporting Final Results ..." >> $log_file
report_timing -nworst 10 >> $log_file
report_area >> $log_file
 
 
/lib_spec.dc
0,0 → 1,36
###############################################################################
#
# Library Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Libraries
 
set search_path [list $search_path . \
/tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \
$hdl_src_dir]
 
set snps [getenv "SYNOPSYS"]
 
set synthetic_library ""
append synthetic_library $snps "/libraries/syn/dw01.sldb "
append synthetic_library $snps "/libraries/syn/dw02.sldb "
append synthetic_library $snps "/libraries/syn/dw03.sldb "
append synthetic_library $snps "/libraries/syn/dw04.sldb "
append synthetic_library $snps "/libraries/syn/dw05.sldb "
append synthetic_library $snps "/libraries/syn/dw06.sldb "
append synthetic_library $snps "/libraries/syn/dw07.sldb "
 
set target_library { umcl18u250t2_typ.db }
set link_library ""
append link_library $target_library " " $synthetic_library
set symbol_library { umcl18u250t2.sdb }
 
/design_spec.dc
0,0 → 1,26
###############################################################################
#
# Design Specification
#
# Author: Rudolf Usselmann
# rudi@asics.ws
#
# Revision:
# 3/7/01 RU Initial Sript
#
#
###############################################################################
 
# ==============================================
# Setup Design Parameters
 
set design_files {ud_cnt ro_cnt atahost_pio_tctrl atahost_controller atahost_top}
 
set design_name atahost_top
set active_design atahost_top
# Next Statement defines all clocks and resets in the design
set special_net {wb_rst_i rst_nreset_i wb_clk_i}
set hdl_src_dir ../../rtl/verilog/ocidec-1/
 

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