URL
https://opencores.org/ocsvn/atlas_core/atlas_core/trunk
Subversion Repositories atlas_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/atlas_core
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/trunk/core/rtl/BUS_INTERFACE.vhd
6,7 → 6,7
-- # instruction cache. The system is capable of # |
-- # generating a true 32-bit wide address for the NoC. # |
-- # **************************************************** # |
-- # Last modified: 18.03.2013 # |
-- # Last modified: 28.03.2013 # |
-- # **************************************************** # |
-- # by Stephan Nolting 4788, Hanover, Germany # |
-- ######################################################## |
644,9 → 644,8
if (CACHE_EN = '1') then -- valid data access |
if (CACHE_RW = '1') then -- cache data write access |
CACHE_MEM(to_integer(unsigned(CACHE_D_ADR(log2_cache_pages_c+log2_cache_page_size_c-1 downto 0)))) <= CACHE_DW_DATA; -- word address! |
else -- cache data read access |
CACHE_DR_DATA <= CACHE_MEM(to_integer(unsigned(CACHE_D_ADR(log2_cache_pages_c+log2_cache_page_size_c-1 downto 0)))); -- word address! |
end if; |
CACHE_DR_DATA <= CACHE_MEM(to_integer(unsigned(CACHE_D_ADR(log2_cache_pages_c+log2_cache_page_size_c-1 downto 0)))); -- word address! |
end if; |
if (I_UPDATE = '1') then -- cache instruction read access |
INSTR_DAT_O <= CACHE_MEM(to_integer(unsigned(CACHE_I_ADR(log2_cache_pages_c+log2_cache_page_size_c-1 downto 0)))); -- word address! |
/trunk/core/rtl/ATLAS_MICRO.vhd
6,7 → 6,7
-- # itself and incorporates a configurable shared/ # |
-- # distributed data/instruction memory/memories. # |
-- # **************************************************** # |
-- # Last modified: 26.03.2013 # |
-- # Last modified: 28.03.2013 # |
-- # **************************************************** # |
-- # by Stephan Nolting 4788, Hanover, Germany # |
-- ######################################################## |
154,9 → 154,8
if (MEM_REQ_FF = '1') then -- valid access |
if (MEM_RW = '1') then -- write data access |
MEM_FILE_X(to_integer(unsigned(MEM_ADR(LOG2_MEM_SIZE_G downto 1)))) <= MEM_W_DATA; |
else -- read data access |
MEM_R_DATA <= MEM_FILE_X(to_integer(unsigned(MEM_ADR(LOG2_MEM_SIZE_G downto 1)))); |
end if; |
MEM_R_DATA <= MEM_FILE_X(to_integer(unsigned(MEM_ADR(LOG2_MEM_SIZE_G downto 1)))); |
end if; |
else -- Separated I/D-Memories |
-- -------------------------------------------------------------- |
163,9 → 162,8
if (MEM_REQ_FF = '1') then-- and (HALT_I = '0') then -- valid access |
if (MEM_RW = '1') then -- write data access |
MEM_FILE_Y(to_integer(unsigned(MEM_ADR(LOG2_MEM_SIZE_G downto 1)))) <= MEM_W_DATA; |
else -- read data access |
MEM_R_DATA <= MEM_FILE_Y(to_integer(unsigned(MEM_ADR(LOG2_MEM_SIZE_G downto 1)))); |
end if; |
MEM_R_DATA <= MEM_FILE_Y(to_integer(unsigned(MEM_ADR(LOG2_MEM_SIZE_G downto 1)))); |
end if; |
end if; |
-- Instruction access |