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URL https://opencores.org/ocsvn/atlas_core/atlas_core/trunk

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  • This comparison shows the changes necessary to convert path 
    /atlas_core
    from Rev 14 to Rev 15
    ↔ Reverse comparison
  •

Rev 14 → Rev 15

/trunk/core/asm/atlas_asm.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/core/asm/src/atlas_asm.exe Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/core/asm/src/main.cpp
1049,8 → 1049,12
opcode = (2<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
else if (strcmp(arg[0], "ADC") == 0)
opcode = (3<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
else if (strcmp(arg[0], "SUB") == 0)
else if (strcmp(arg[0], "SUB") == 0){
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) { printf("WARNING: Redundant SUB will result in NEG instruction! (line &d)\n", line); warning_cnt++;}
opcode = (4<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
}
else if (strcmp(arg[0], "NEG") == 0)
opcode = (4<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[2], line);
else if (strcmp(arg[0], "SBC") == 0)
opcode = (5<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
else if ((strcmp(arg[0], "CMP") == 0) or (strcmp(arg[0], "CMPS") == 0))
1058,13 → 1062,13
else if ((strcmp(arg[0], "CPX") == 0) or (strcmp(arg[0], "CPXS") == 0))
opcode = (7<<10) | (1<<3) | (conv_reg(arg[1], line)<<4) | conv_reg(arg[2], line);
else if (strcmp(arg[0], "AND") == 0){
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) printf("WARNING: Redundant AND will result in STUB instruction! (line &d)\n", line);
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) { printf("WARNING: Redundant AND will result in STUB instruction! (line &d)\n", line); warning_cnt++;}
opcode = (8<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
}
else if (strcmp(arg[0], "STUB") == 0) // store register to user bank register
opcode = (8<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[2], line);
else if (strcmp(arg[0], "ORR") == 0){
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) printf("WARNING: Redundant ORR will result in LDUB instruction! (line &d)\n", line);
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) { printf("WARNING: Redundant ORR will result in LDUB instruction! (line &d)\n", line); warning_cnt++;}
opcode = (9<<10) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
}
else if (strcmp(arg[0], "LDUB") == 0) // load register from user bank register
1092,8 → 1096,12
opcode = (2<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
else if (strcmp(arg[0], "ADCS") == 0)
opcode = (3<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
else if (strcmp(arg[0], "SUBS") == 0)
else if (strcmp(arg[0], "SUBS") == 0){
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) { printf("WARNING: Redundant SUBS will result in NEG instruction! (line &d)\n", line); warning_cnt++;}
opcode = (4<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
}
else if (strcmp(arg[0], "NEGS") == 0)
opcode = (4<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[2], line);
else if (strcmp(arg[0], "SBCS") == 0)
opcode = (5<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
else if (strcmp(arg[0], "LDSR") == 0) // load register from msr
1105,13 → 1113,13
opcode = (7<<10) | ((temp>>3)<<7) | (1<<6) | (conv_flag_op_2(arg[2], line)<<5) | (1<<4) | (temp & 7);
}
else if (strcmp(arg[0], "ANDS") == 0){
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) printf("WARNING: Redundant ANDS will result in STUBS instruction! (line &d)\n", line);
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) { printf("WARNING: Redundant ANDS will result in STUBS instruction! (line &d)\n", line); warning_cnt++;}
opcode = (8<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
}
else if (strcmp(arg[0], "STUBS") == 0) // store register to user bank register and set flags
opcode = (8<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[2], line);
else if (strcmp(arg[0], "ORRS") == 0){
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) printf("WARNING: Redundant ORRS will result in LDUBS instruction! (line &d)\n", line);
if (conv_reg(arg[2], line) == conv_reg(arg[3], line)) { printf("WARNING: Redundant ORRS will result in LDUBS instruction! (line &d)\n", line); warning_cnt++;}
opcode = (9<<10) | (1<<3) | (conv_reg(arg[1], line)<<7) | (conv_reg(arg[2], line)<<4) | conv_reg(arg[3], line);
}
else if (strcmp(arg[0], "LDUBS") == 0) // load register from user bank register and set flags
1392,7 → 1400,7
// *****************************************************************************************************************
int main(int argc, char *argv[]){
 
printf("\nAtlas Project - Evaluation Assembler, Version 2013.04.18\n");
printf("\nAtlas Project - Evaluation Assembler, Version 2013.05.08\n");
printf("by Stephan Nolting (stnolting@gmail.com), Hanover, Germany\n\n");
 
// pre_processor.asm - intermediate processing file
/trunk/core/rtl/OP_DEC.vhd
3,7 → 3,7
-- # **************************************************** #
-- # OpCode decoding unit. #
-- # **************************************************** #
-- # Last modified: 19.04.2013 #
-- # Last modified: 08.05.2013 #
-- # **************************************************** #
-- # by Stephan Nolting 4788, Hanover, Germany #
-- ########################################################
60,7 → 60,8
-- Opcode Decoder --------------------------------------------------------------------------------------
-- --------------------------------------------------------------------------------------------------------
OPCODE_DECODER: process(INSTR_INT, MULTI_CYC_I, T_FLAG_I, M_FLAG_I, CP_PTC_I)
variable mem_acc_temp_v : std_logic_vector(3 downto 0);
variable mem_acc_temp_v : std_logic_vector(3 downto 0);
variable redundant_reg_v : std_logic;
begin
 
-- defaults --
75,6 → 76,12
CTRL_O(ctrl_bit_3_c downto ctrl_bit_0_c) <= INSTR_INT(03 downto 00); -- bit address
CTRL_O(ctrl_cond_3_c downto ctrl_cond_0_c) <= INSTR_INT(13 downto 10); -- branch condition
 
-- both operands have same addresses --
redundant_reg_v := '0';
if (INSTR_INT(06 downto 04) = INSTR_INT(02 downto 00)) then
redundant_reg_v := '1';
end if;
 
-- decoder --
case (INSTR_INT(15 downto 14)) is
 
91,7 → 98,7
 
when fs_orr_c => -- logical or // load from user bank register if redundant
CTRL_O(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_orr_c; -- logical or
if (INSTR_INT(06 downto 04) = INSTR_INT(02 downto 00)) then -- user bank load
if (redundant_reg_v = '1') then -- user bank load
CTRL_O(ctrl_ra_3_c) <= user_mode_c; -- load from user bank
CTRL_O(ctrl_rb_3_c) <= user_mode_c; -- load from user bank
if (M_FLAG_I = user_mode_c) then -- unauthorized access
101,7 → 108,7
 
when fs_and_c => -- logical and // store to user bank register if redundant
CTRL_O(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_and_c; -- logical and
if (INSTR_INT(06 downto 04) = INSTR_INT(02 downto 00)) then -- user bank store
if (redundant_reg_v = '1') then -- user bank store
CTRL_O(ctrl_rd_3_c) <= user_mode_c; -- store to user bank
if (M_FLAG_I = user_mode_c) then -- unauthorized access
CTRL_O(ctrl_syscall_c) <= '1'; -- access violation
182,9 → 189,16
when fs_inc_c | fs_add_c => -- immediate addition // addition
CTRL_O(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_adc_c;
 
when fs_dec_c | fs_sub_c => -- immediate subtraction // addition
when fs_dec_c => -- immediate subtraction
CTRL_O(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c;
 
when fs_sub_c => -- subtraction
CTRL_O(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c;
if (redundant_reg_v = '1') then -- SUB instruction with Ra = Rb: Rd = 0 - Ra (NEG Rd, Ra)
CTRL_O(ctrl_clr_la_c) <= '1'; -- set low byte of A to 0
CTRL_O(ctrl_clr_ha_c) <= '1'; -- set high byte of A to 0
end if;
 
when fs_adc_c => -- addition with carry
CTRL_O(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_adc_c;
CTRL_O(ctrl_alu_usec_c) <= '1'; -- use carry input
/trunk/core/doc/Atlas Processor Datasheet.pdf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

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