Rev 9 → Rev 11
sfmath.sty
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Deleted: svn:executable
Index: cited.bib
===================================================================
--- cited.bib (revision 9)
+++ cited.bib (nonexistent)
@@ -1,62 +0,0 @@
-@misc{Altera:Avalon,
- title = {Avalon Interface Specification},
- organization = {Altera Corporation},
- address = {101 Innovation Drive, San Jose, CA, US},
- year = {2005},
- key = {MNL-AVABUSREF-3.1},
- type = {Specification},
- url = {http://www.altera.com/literature/manual/mnl\_avalon\_spec.pdf}
-}
-
-@misc{OC:WBspec,
- title = {WISHBONE SoC Architecture Specification, Revision B.3},
- author = {Richard Herveille},
- organization = {Opencores Organization},
- address = {},
- edition = {},
- month = {Sept.},
- year = {2002},
- url = {http://www.opencores.org/downloads/wbspec_b3.pdf},
-}
-
-
-@misc{NIST:Fips197,
- title = {FIPS-197 Announcing the Advanced Encryption Standard (AES) },
- organization = {National Institute of Standards and Technology (NIST)},
- address = {100 Bureau Drive, Stop 1070, Gaithersburg, MD, US},
- edition = {Federal Information Processing Standards Publication 197},
- month = {Nov.},
- year = {2001},
- url = {http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf},
-}
-
-
-@misc{Xilinx:wp284,
- title = {Advantages of the Virtex-5 FPGA 6-Input LUT Architecture},
- author = {Andrew Percey},
- organization = {Xilinx Inc.},
- address = { 2100 Logic Drive, San Jose CA USA },
- edition = {Whitpaper 284},
- month = {Dec.},
- year = {2007},
- url = {http://www.xilinx.com/support/documentation/white_papers/wp284.pdf},
-}
-
-
-@misc{Altera:01007,
- title= {Stratix III FPGAs vs. Xilinx Virtex-5 Devices: Architecture and Performance Comparison},
- organization = {Altera Corporation},
- address = { 101 Innovation Drive, San Jose CA USA},
- edition = {Whitepaper 01007-v2.1},
- month = {Oct.},
- year = {2007},
- url ={http://www.altera.com/literature/wp/wp-01007.pdf}
-}
-
-@misc{Wiki:AvWb,
- title = {Wishbone - Computer Bus},
- organization = {wikipedia.org},
- lastchecked = {2009-04-20},
- url = {http://en.wikipedia.org/wiki/Wishbone\_computer\_bus)#Comparisons},
-}
-
cited.bib
Property changes :
Deleted: svn:executable
Index: avs_aes.tex
===================================================================
--- avs_aes.tex (revision 9)
+++ avs_aes.tex (nonexistent)
@@ -1,417 +0,0 @@
-\documentclass{ruschidoc}
-
-\usepackage[
- bookmarks,
- plainpages={false}]{hyperref}
-
-\usepackage[
- style=altlist,
- hyper=true,
- number=none,
- acronym=true,
- header=none]{glossary}
-\usepackage{capt-of}
-
-%%% Water mark
-%\usepackage{draftwatermark}
-%\SetWatermarkText{\shortstack{DRAFT}}
-%\SetWatermarkScale{0.9}
-%\SetWatermarkLightness{0.85}
-
-\makeacronym
-\makeglossary
-\input{acronym}
-\input{glossary}
-\bibliographystyle{IEEEtran}
-
-%%%%%%%%%%%%%%%%%
-% Document variables
-%%%%%%%%%%%%%%%%%
-\docDate{ \today }
-\docID{avs\_aes\_doc}
-\docRevision{0.5}
-\docStatus{Final}
-\docTitle{\mbox{AES 128/192/256 (ECB)} \mbox{Avalon\rtm-MM Slave}}
-\keywords{Avalon, bus, slave, cryptography, AES, ecb, IP core }
-
-\authorName{\mbox{Thomas Ruschival} \\ and opencores.org}
-\authorURL{www.opencores.org}
-\authorAddress{\mbox{}}
-\authorEmail{ruschi@opencores.org}
-
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-% FORMAT: Rev | Chapter | Description | Date | Reviewer \\
-\revisionList{
-0.1 & all & initial document & 2009/02/01 & T. Ruschival \\
-0.2 & all & added interrupt & 2009/03/25 & T. Ruschival \\
-0.3 & all & added generics & 2009/04/20 & T. Ruschival \\
-0.4 & all & cleanup for opencores.org & 2009/05/20 & T. Ruschival \\
-0.5 & all & final release & 2010/03/07 & T. Ruschival \\
-}
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-
-
-\begin{document}
-\maketitle
-\newpage
-\tableofcontents
-\newpage
-
-\section{Introduction}
-\label{sec:intro} The \AES is a symmetric block cypher operating on fixed block sizes
-of 128 Bit and is specified for key sizes of 128, 192 and 256 Bit designed by Joan
-Daemen and Vincent Rijmen. The algorithm was standardized by \NIST. For more
-information on the algorithm see \cite{NIST:Fips197}.\\
-This component implements an AES encryption decryption datapath in \ECB mode with
-either 128,192 or 256 Bit keys. The keylength is determined by generics at compile
-time. Also the decryption datapath can be disabled by generics if it is not needed
-for the application.\\
-The component provides an Avalon\rtm\ Memory Mapped (Avalon-MM) slave interface to
-connect to an Altera\rtm\ Avalon\rtm\ switch fabric. The Avalon\rtm\ interface is
-implemented in a way that it can also be used to connect to a Whishbone master if the
-signals are correctly mapped, see \cite{Wiki:AvWb}. For further information about the
-Whishbone bus refer to \cite{OC:WBspec}. \\
-
-\section{Interface}
-\label{sec:interface}
-The AES core is accessed by the interface described in this section. An Avalon\rtm\
-interface was chosen for its simplicity and compatibility with wishbone. Furthermore
-Avalon\rtm\ defines interrupt request signals for slaves which would be separate
-signals in a Wishbone implementation.The component can be used both in polling
-mode or can provide an interrupt for signalling. \\
-Unfortunately Avalon\rtm\ is an Altera\rtm\ proprietary technology. The actual AES
-core however is a selfcontained entity and can be embedded into other \SoC\ bus
-interfaces as well or used indepentently.
-
-\subsection{Configuration Generics}
-\label{sec:generics}
-The AES core can be configured by generics shown in table \ref{tab:generics},
-consequently they are provided by the Avalon\rtm\ interface.
-
-\begin{tabularx}{\textwidth}{|p{33mm}|p{25mm}|X|}
- \hline
- \bf{Generic name} & \bf{type} & \bf{Description}\\ \hline
- \texttt{KEYLENGTH} \label{gen:keylength} & NATURAL & Size of initial userkey. Must be 128, 192 or 256 \footnotemark[1] . \\ \hline
- \texttt{DECRYPTION} \label{gen:decryption} & BOOLEAN & Enables the instantiation of the decrypt datapath if true. \\
-\hline
-\end{tabularx}
-\footnotetext[1]{All other values raise a compilation failure}
-\captionof{table}{Component generics}
-\label{tab:generics}
-Note: \texttt{KEYLENGTH} of 192 fail synthesis with Xilinx ISE \rtm\ because of division by 6 in key schedule that cannot be mapped to shift operations (\texttt{keyexpansion.vhd}).
-
-\subsection{Signals}
-\label{sec:signals}
-The Avalon\rtm\-MM Slave interface is described in \cite{Altera:Avalon}, the component
-implements the signals shown in table \ref{tab:signals}. All signals are synchronous,
-sampled at the rising edge of the clock. The type for all signals is \texttt{IEEE1164
- std\_logic} or \texttt{std\_logic\_vector}. For signals wider that 1 Bit the range
-is \MSB\ \texttt{downto} \LSB\. \\
-This components has only output signals driven by registers no input signals are directly combinatorially connected to the
-output signals, thus combinational loops are avoided. All signals are active
-high. This component does not support burst transfers.
-
-\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
- \hline
- \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\ \hline
- \texttt{clk} \label{sig:clk} & 1 & in & Avalon\rtm\ bus clock, also used to drive the core. \\ \hline
- \texttt{reset} \label{sig:reset}& 1 & in & \emph{Synchronous} reset signal for Avalon\rtm\ bus interface.
- The core itself is designed without need for reset signals.
- \\ \hline
- \texttt{writedata} \label{sig:writedata} & 32 & in & Input data to write to location designated by \texttt{address}. Bit 31 is most significant Bit.
- \\ \hline
- \texttt{address} \label{sig:address} & 5 & in & Word offset to the components base address. The memory map of the component for the
- respective offest is described in \ref{sec:memmap}. Only full 32-Bit words can be addressed no byte addressing is implemented.
- \\ \hline
- \texttt{write}\footnotemark[1] \label{sig:write} & 1 & in & If asserted enable write of data at \texttt{writedata} to location designated by \texttt{address}.
- \\ \hline
- \texttt{read}\footnotemark[1] \label{sig:read} & 1 & in & If asserted output data at location designated by \texttt{address} to \texttt{readdata}.
- \\ \hline
- \texttt{readdata} \label{sig:readdata} & 32 & out & Data output port for reading data at the location defined by \texttt{address}. Bit 31 is most significant Bit.
- \\ \hline
- \texttt{waitrequest} \label{sig:waitrequest} & 1 & out & Asserted if writedata was not accepted, this is the case if the keyexpansion is
- not yet complete and a new is written to the \texttt{KEY} address range without previous deassertion of the \texttt{KEY\_VALID} Bit
- \\ \hline
- \texttt{irq}\label{sig:irq} & 1 & out & If Interrupt behaviour is enabled \texttt{IRQ}
- will be asserted when the operation has terminated. For use of interrupt see \ref{sec:irq}
- \\ \hline
-\end{tabularx}
-\footnotetext[1]{\texttt{read} and \texttt{write} are mutually exclusive and must not be asserted simultanously.}
-\label{tab:signals}
-\captionof{table}{Avalon\rtm\ Bus interface signals}
-
-
-\section{Memory Map}
-\label{sec:memmap}
-The AES core Avalon\rtm\ slave has an address space of 31 words accessable through the
-offset described by the signal \texttt{address}, see \ref{sig:address}. This address
-space is devided into three main sections for the 4-word input data, the 4-word
-result of the operation and the user key. The actual lenght of the userkey can vary
-between 4, 6 and 8 words depending on the keysize. For control signals and status
-information of the component and a control word is provided. The memory mapping is
-descibed in table \ref{tab:memmap}.
-
-\begin{tabularx}{\textwidth}{|p{13mm}|p{18mm}|X|}
- \hline
- \bf{Offset} & \bf{Name} & \bf{Function}\\ \hline
- \texttt{0-7} & \texttt{KEY} & Initial user key that will be used for encryption and decryption.
- The most significant word of the user key shall be written to offset \texttt{3}. This memory section is \emph{write-only} to the Avalon\rtm\ Interface.\\ \hline
- \texttt{8-11} & \texttt{DATA} &Input data, can be either interpreted as cyphertext for decryption or plain text for encryption.
- The most significant word shall be written to offset \texttt{7}. This memory section is \emph{write-only} to the Avalon\rtm\ Interface. \\ \hline
- \texttt{12-15} & \texttt{RESULT} &Result of the operation. The most significant word of the result at offset \texttt{11}.
- This memory section is \emph{read-only} to the Avalon\rtm\ Interface. \\ \hline
- \texttt{16-30} & --- & reserved \\ \hline
- \texttt{31} & \texttt{CTRL} & Control and status word of the component can be read and written. Detailed description see \ref{sec:ctrl}\\ \hline
-\end{tabularx}
-\label{tab:memmap}
-\captionof{table}{Memory map of the AES core Avalon\rtm\ slave}
-
-\subsection{Control Register}
-\label{sec:ctrl}
-The AES Core offers the register \texttt{CTRL} to control the function of the core
-and poll its status. The control register can be accessed in read and write mode.
- When wrriting to the register reserved Bits shall be assigned a value of \texttt{0}.
- Individual Bits have following functionality decribed in table \ref{tab:ctrlreg}. \\
-In case of a Avalon\rtm\ Bus reset this register is set to \texttt{0x00000000} thus
-invalidating all previously written keys and resetting the AES core.
-
-\begin{tabularx}{\textwidth}{|p{13mm}|p{18mm} |X|}
- \hline
- \bf{Offset} & \bf{Name} & \bf{Description}\\ \hline
- \texttt{31-8} & --- & reserved \\ \hline
- \texttt{7} &\texttt{KEY\_VALID} &If asserted key data in the \texttt{KEY} memory range is regarded valid and will be expanded to roundkeys.
- When deasserted all keys are invalidated and the current operation of the core is aborted. It must be asserted as long as the key shall be
- used for either encryption or decryption. \\ \hline
- \texttt{6} & \texttt{IRQ\_ENA} & Enable use of the interrupt request signal. If asserted the component will set \texttt{IRQ} after
- completing an operation. If not set the component operates in polling mode only.\\ \hline
- \texttt{5-2} & --- &reserved \\ \hline
- \texttt{1} & \texttt{DEC} \footnotemark[1] & If asserted memory content of the \texttt{DATA} range is regarded to be valid and will be
- \emph{decrypted}. This Bit shall only be deasserted externally if a running AES operation is aborted by deasserting \texttt{KEY\_VALID}. 1
- It will be set \texttt{0} by the core to signal completion of the operation.\\ \hline
- \texttt{0} & \texttt{ENC} \footnotemark[1] & If asserted memory content of the \texttt{DATA} range is regarded to be valid and will be
- \emph{encrypted}. This Bit shall only be deasserted externally if a running AES operation is aborted by deasserting \texttt{KEY\_VALID}.
- It will be set \texttt{0} by the core to signal completion of the operation. \\ \hline
-\end{tabularx}
-\footnotetext[1]{\texttt{ENC} and \texttt{DEC} are mutually exclusive and must not be asserted simultanously.}
-\label{tab:ctrlreg}
-\captionof{table}{Bits in the control register}
-
-
-\section{Protocol Sequence}
-\label{sec:usage}
-The AES component appears as memory mapped peripheral. All writes are fundamental slave write transfers, see \cite{Altera:Avalon} and take one
-clock cycle of the Avalon\rtm\ bus clock \texttt{clk}. It is not necessary to write all words of a input parameter successively or in one transfer.
-Bursts are not supported.\\
-\\
-Before any AES operation can be started the initial userkey has to be written to
-\texttt{KEY} segment of the memory map.After the user key is transferred
-to the component the \texttt{KEY\_VALID} Bit must be set to start the key
-expansion. This Bit can be set simultanously with \texttt{DEC} or \texttt{ENC} Bit of
-the control register. To invalidate the previous key and use another key the
-\texttt{KEY\_VALID} must be deasserted for at least one Avalon\rtm\ bus clock cycle
-During this cycle the new key can already be transferred.\\
-\\
-Once a key is passed and marked valid data blocks can be transferred to the
-\texttt{DATA} segment of the memory map.
-The AES operation is started by asserting the \texttt{ENC} Bit for
-encryption or \texttt{DEC} Bit for decryption.
-While asserting \texttt{ENC} or \texttt{DEC} the \texttt{KEY\_VALID} Bit must be
-kept asserted.\\
-The \texttt{ENC} or \texttt{DEC} Bit respectively is deasserted by the component
-after completing the requested operation.
-The result of the operation can be read from the \texttt{RESULT} area of the memory
-and is not cleared. It will be overwritten by succeeding operations.
-
-The underlying AES core uses the \FSM\ shown in \ref{fig:aesFSM} for processing of
-the data. The signals \texttt{data\_stable} and \texttt{key\_stable} are accessible
-over the control status word \texttt{CTRL} \ref{sec:ctrl}. \texttt{key\_ready} is a
-signal driven by the keygenerator when all keys are expanded. The signal
-\texttt{round\_index} is the counter for the rounds and the address to select a
-roundkey. \\
-\texttt{NO\_ROUNDS} is the total number of rounds the processing takes, a constant
-defined by the generic \texttt{KEYLENGTH} \ref{sec:generics}. The AES standard
-in\cite{NIST:Fips197} defines 10 rounds for 128 Bit key, 12 rounds for a 192 Bit key
-and 14 rounds for a 265 Bit key.\\
-Thus depending on the keylength the processing of a datablock needs at maximum 15
-clockcycles from \texttt{data\_stable=1} to completion, if the key is already expanded.
-
-\begin{figure}[!ht]
- \centering
- \includegraphics[width=100mm]{encrypt_FSM}
- \caption{Finite State Machine of encryption and decryption process}
- \label{fig:aesFSM}
-\end{figure}
-
-
-\subsection{Interrupt Behaviour}
-\label{sec:irq}
-By setting \texttt{IRQ\_ENA} in the control register \ref{sec:ctrl} the
-component is configured to issue interrupt requests.
-If \texttt{IRQ\_ENA} is asserted the interrupt request \texttt{IRQ} \ref{sig:irq} will be set when the
-computation has completed in addition to clearing the \texttt{ENC} or \texttt{DEC}
-Bit.
-The \texttt{IRQ} \ref{sig:irq} signal will remain set until clearing \texttt{IRQ\_ENA}
-or a read operation on the \texttt{RESULT} area of the components address range.
-
-
-\section{Ressource Usage and Throughput}
-\label{sec:ressources}
-
-The Avalon\rtm\ interface communicates a 32-Bit DWORD per clock cycle. Therefore a key is transmitted in 4 to 8 cyles
-plus one cyle to activate keyexpansion with the control word \ref{sec:ctrl}. A payload datablock or the result consist
-always of 4 DWORDs, thus it takes 4 cyles to send data to the core, one cycle to activate the computation with the
-control register \ref{sec:ctrl} and 4 cycles to retrieve the data.
-
-The keyexpansion component computes one column of a roundkey each clock cylce. AES takes, depending on the keylength,
-10, 12 or 14 roundkeys with each 4 columns, see \cite{NIST:Fips197}. The keyexpansion therefore takes 40, 48 or 56
-cycles until the encryption or decryption can start. The roundkeys are stored until invalidated, see \ref{sec:usage}
-thus this step is is only needed once after power-up until the key changes.
-
-The AES-core computes one iteration (round) of the Rijndael-Algorithm each clock cycle, thus a 128 Bit datablock is
-encrypted or decrypted in 10, 12 or 14 cylces plus an initial round.
-
-The maximum throughput $T_{max}[Bits]$ depends on the maximum operation frequency $f_{max}$ and the keylength which
-influences the number of rounds $N_{rnd} \epsilon \lbrace 10,12,14 \rbrace $.
-\begin{equation}
- T_{max}=\frac{ (1+N_{rnd}) \cdot 128 Bit}{f_{max}}
-\label{eqn:tmax}
-\end{equation}
-
-Note: Equation \ref{eqn:tmax} assumes that the roundkeys are already generated and does not include the constant of 4+1+4
-Avalon\rtm\ bus cylces for transmission of data, activation and result retrieval.
-
-
-\subsection{Exemplary FPGA implementations}
-
-The component has only be implemented and tested on an Altera\rtm\ CycloneII EP2C35
-FPGA. All other values in the table are only results of synthesis\footnotemark[0] and are not
-verified on actual hardware.
-
-\footnotetext[0]{Synthesized with Altera\rtm\ QuartusII\rtm\ Web edition Version 9.1 or Xilinx\rtm\ ISE 9.1 Webpack}
-
-The design is kept mostly vendor independent in generic VHDL. For Altera\rtm\ chips the
-AES SubByte component is specially designed using M4K Blockrams as dual-port ROM. For
-non-Altera\rtm\ FPGAs a second VHDL architecture exists also trying to make use of
-ROM functions of the target chips however the success varies on RTL compiler
-capabilities.
-
-\begin{tabularx}{\textwidth}{|p{30mm}|X|p{20mm}|p{30mm}|p{18mm}|}
- \hline
- \bf{Configuration} & \bf{Target FPGA}\footnotemark[1] & \bf{LE / Slices} & \bf{HW RAM} & $\mathbf{f_{max}[Mhz]}$ \\ \hline
- \multirow{4}{30mm}{256 Bit Key, encrypt + decrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 1609 & 18 RAMB16BWE & 91 \\ \cline{2-5}
- & \mbox{Xilinx\rtm\ Virtex5} XC5VLX30-3FF324 & - / 297 & \mbox{18 18k-Blocks} \mbox{4 36k-Blocks} & 224 \\ \cline{2-5}
- & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 1937 / - & \mbox{39912 Bits} in \mbox{22 M4K-Blocks} & 65 \\ \cline{2-5}
- & \mbox{Altera\rtm\ StratixII} EP2S30F484C5 & 585 / - & \mbox{39912 Bits} in \mbox{22 M4K-Blocks} & 103 \\
- \hline
-%%%%%%
- \multirow{2}{30mm}{128 Bit Key, encrypt + decrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 1523 & 18 RAMB16BWE & 91 \\ \cline{2-5}
- & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 1776 / - & \mbox{39912 Bits} in \mbox{22 M4K-Blocks} & 65 \\
- \hline
-%%%%%%
- \multirow{4}{30mm}{256 Bit Key, encrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 680 & 14 RAMB16BWE & 159 \\ \cline{2-5}
- & \mbox{Xilinx\rtm\ Virtex5} XC5VLX30-3FF324 & - / 297 & \mbox{10 18k-Blocks} \mbox{4 36k-Blocks} & 268 \\ \cline{2-5}
- & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 969 / - & \mbox{22528 Bits} in \mbox{14 M4K} & 97 \\ \cline{2-5}
- & \mbox{Altera\rtm\ StratixII} EP2S30F484C5 & 524 / - & \mbox{22528 Bits} in \mbox{ 14 M4K} & 145 \\
- \hline
-%%%%%%
- \multirow{2}{30mm}{128 Bit Key, encrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 594 & 14 RAMB16BWE & 159 \\ \cline{2-5}
- & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 797 / - & \mbox{22528 Bits} in \mbox{ 14 M4K} & 95 \\ \cline{2-5}
- \hline
-
-\end{tabularx}
-\footnotetext[1]{This table is not meant to be a benchmark between FPGAs of different vendors, it is only a rough
- estimation for the user of the core.
- The FPGA families cannot be compared easily, see also \cite{Xilinx:wp284} and \cite{Altera:01007}for further details. }
-\label{tab:ressources}
-\captionof{table}{ressource usage on different targets and configuration}
-
-All of the above configurations in table \ref{tab:ressources} use hardware key
-expansion. Downloading of software generated roundkeys is not yet supported. The
-decryption and encryption datapaths share a common keyexpansion block, mulitplexing
-the address signals is one of the main reasons for regression of the maximum
-frequency $f_{max}$ of the configuration compared to encryption only versions.
-
-\section{Compilation and Simulation}
-\label{sec:compilation}
-The main simulation library is ``\texttt{aes\_ecb\_lib}''. All files are expected to be
-compiled into this library as all files depend at least on the package
-\texttt{aes\_lib.aes\_ecb\_pkg}. \\
-A Makefile for Mentorgraphics\rtm\ Modelsim\rtm\ is given in \texttt{./sim/}. The
-make target \texttt{simaes} will create the library, compile all files and run a
-testbench.\\
-
-\section{The Inner Core}
-\label{sec:core}
-The algorithmic core is devided into two seperate datapaths one for encryption and a
-second for decryption operation. The two datapaths are independent, however they
-share the keyexpansion component which provides decrypt and encrypt keys (which are
-the same only in opposite order). Each datapath is controlled by its own \FSM\. If
-configured by the generic \texttt{DECRYPTION} \ref{gen:decryption} the decryption
-datapath is included and some multiplexers are generated for the shared signals,
-e.g. \texttt{result} or \texttt{roundkey\_index}.\\
-For reference the encryption data path of \texttt{aes\_core.vhd} is given in figure
-\ref{fig:aescore}. The decryption datapath is left for the reader or any other author
-of this document.
-\begin{figure}[!ht]
- \centering
- \includegraphics[width=0.9\textwidth]{CoreEncDP}
- \caption{Encrypt datapath of the AES core as implemented in aes\_core.vhd}
- \label{fig:aescore}
-\end{figure}
-
-
-\newpage
-\section{License and Liability}
-\label{sec:license}
-The ``AES 128/192/256 (ECB) Avalon\rtm-MM Slave'' component, all its subcomponents
-and documentation (like this document you are reading) are published under following
-license:\\
-
-Copyright (c) 2009, Thomas Ruschival - All rights reserved.
-
-Redistribution and use in source and binary forms, with or without modification, are
-permitted provided that the following conditions are met:
-\begin{itemize}
-\item Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-\item Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or other
- materials provided with the distribution.
-\item Neither the name of the organization nor the names of its contributors may be
- used to endorse or promote products derived from this software without specific
- prior written permission.
-\end{itemize}
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. \\
-IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE\\
-
- Note: The term ``SOFTWARE'' in the above licence applies in this case not only to
- software as executable code but also to documentation, hardware description or
- compiled netlists for actual target hardware. As Chips generally don't just
- reproduce ``the above copyright notice, this list of conditions and the following
- disclaimer in the documentation and/or other materials provided with the
- distribution'' the datasheet of the product must also contain it.\\
-
-Altera, CycloneII, StratixII and Avalon are registered trademarks of the Altera Corporation
- 101 Innovation Drive, San Jose CA USA \\
- Xilinx, Spartan3A and Virtex5 are registered trademarks of Xilinx Inc. 2100 Logic Drive, San Jose CA USA
-
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-
-\printacronym
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avs_aes.tex
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Index: figs/CoreEncDP.svg
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figs/fancy_headsep_r.eps
Property changes :
Deleted: svn:executable
Index: glossary.tex
===================================================================
--- glossary.tex (revision 9)
+++ glossary.tex (nonexistent)
@@ -1,29 +0,0 @@
-\glossary{name={Byte},
- description={String of Bits - nowadays mostly a string of 8 Bits, also called oktett},
- sort={Byte}
-}
-\glossary{name={Bit},
- description={Binary Digit, atomary information unit},
- sort={Bit}
-}
-\glossary{name={switch fabric},
- description={Interconnect between IP-Cores providing arbiration and glue logic. Altera\rtm\ Avalon\rtm\ term},
- sort={Switch fabric}
-}
-
-\glossary{name={Master},
- description={Entity initiating and controlling communication.},
- sort={Master}
-}
-
-\glossary{name={Slave},
- description={Entity responding to communication requests by a Master.},
- sort={Slave}
-}
-
-\glossary{name={memory mapped},
- description={Method of addressing peripheral components like Avalon Slaves via the same address bus as main memory},
- sort={memory mapped}
-}
-
-
\ No newline at end of file
glossary.tex
Property changes :
Deleted: svn:executable
Index: ruschidoc.cls
===================================================================
--- ruschidoc.cls (revision 9)
+++ ruschidoc.cls (nonexistent)
@@ -1,300 +0,0 @@
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- \RequirePackage[pdftex]{color}
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- \RequirePackage{graphics}
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-\graphicspath{{figs/}}
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-\def\shorttoday{\number\day-\ifcase\month\or
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- \fancyfoot{}
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- \large{\@authorURL} & & \large{\@authorEmail} \\
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ruschidoc.cls
Property changes :
Deleted: svn:executable
Index: avs_aes.pdf
===================================================================
--- avs_aes.pdf (revision 9)
+++ avs_aes.pdf (nonexistent)
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avs_aes.pdf
Property changes :
Deleted: svn:executable
Index: acronym.tex
===================================================================
--- acronym.tex (revision 9)
+++ acronym.tex (nonexistent)
@@ -1,15 +0,0 @@
-\newacronym{LSB}{Least Significant Bit}{description=least value bit in a vector}
-\newacronym{MSB}{Most Significant Bit}{description=highest value bit in a vector}
-\newacronym{SoC}{System on Chip}{description=System of seperate functional interacting together implemented on a single chip }
-\newacronym{AES}{Advanced Encryption Standard}{description=NIST approved symmetric
-block cypher}
-\newacronym{ECB}{Electronic Codebook}{description=application of a cypher algorithm
-without further processing of the blocks}
-\newacronym{FSM}{Finite State Machine}{description=Behavioural Model with finite
-number of states and transitions}
-\newacronym{NIST}{National Institute of Standards and Technology}{description=US
-standardisation office}
-
-
-
-
acronym.tex
Property changes :
Deleted: svn:executable
Index: sw/html/AEStester_8c__incl.png
===================================================================
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svn:mime-type = application/octet-stream
Index: sw/html/AEStester_8c__incl.png
===================================================================
--- sw/html/AEStester_8c__incl.png (nonexistent)
+++ sw/html/AEStester_8c__incl.png (revision 11)
sw/html/AEStester_8c__incl.png
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/tabs.css
===================================================================
--- sw/html/tabs.css (nonexistent)
+++ sw/html/tabs.css (revision 11)
@@ -0,0 +1,105 @@
+/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */
+
+DIV.tabs
+{
+ float : left;
+ width : 100%;
+ background : url("tab_b.gif") repeat-x bottom;
+ margin-bottom : 4px;
+}
+
+DIV.tabs UL
+{
+ margin : 0px;
+ padding-left : 10px;
+ list-style : none;
+}
+
+DIV.tabs LI, DIV.tabs FORM
+{
+ display : inline;
+ margin : 0px;
+ padding : 0px;
+}
+
+DIV.tabs FORM
+{
+ float : right;
+}
+
+DIV.tabs A
+{
+ float : left;
+ background : url("tab_r.gif") no-repeat right top;
+ border-bottom : 1px solid #84B0C7;
+ font-size : 80%;
+ font-weight : bold;
+ text-decoration : none;
+}
+
+DIV.tabs A:hover
+{
+ background-position: 100% -150px;
+}
+
+DIV.tabs A:link, DIV.tabs A:visited,
+DIV.tabs A:active, DIV.tabs A:hover
+{
+ color: #1A419D;
+}
+
+DIV.tabs SPAN
+{
+ float : left;
+ display : block;
+ background : url("tab_l.gif") no-repeat left top;
+ padding : 5px 9px;
+ white-space : nowrap;
+}
+
+DIV.tabs #MSearchBox
+{
+ float : right;
+ display : inline;
+ font-size : 1em;
+}
+
+DIV.tabs TD
+{
+ font-size : 80%;
+ font-weight : bold;
+ text-decoration : none;
+}
+
+
+
+/* Commented Backslash Hack hides rule from IE5-Mac \*/
+DIV.tabs SPAN {float : none;}
+/* End IE5-Mac hack */
+
+DIV.tabs A:hover SPAN
+{
+ background-position: 0% -150px;
+}
+
+DIV.tabs LI.current A
+{
+ background-position: 100% -150px;
+ border-width : 0px;
+}
+
+DIV.tabs LI.current SPAN
+{
+ background-position: 0% -150px;
+ padding-bottom : 6px;
+}
+
+DIV.navpath
+{
+ background : none;
+ border : none;
+ border-bottom : 1px solid #84B0C7;
+ text-align : center;
+ margin : 2px;
+ padding : 2px;
+}
Index: sw/html/AEStester_8c__incl.md5
===================================================================
--- sw/html/AEStester_8c__incl.md5 (nonexistent)
+++ sw/html/AEStester_8c__incl.md5 (revision 11)
@@ -0,0 +1 @@
+ff160b2d14df447519bb4aa79b4d3068
\ No newline at end of file
Index: sw/html/ftv2folderopen.png
===================================================================
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svn:mime-type = application/octet-stream
Index: sw/html/ftv2folderopen.png
===================================================================
--- sw/html/ftv2folderopen.png (nonexistent)
+++ sw/html/ftv2folderopen.png (revision 11)
sw/html/ftv2folderopen.png
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Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/graph_legend.html
===================================================================
--- sw/html/graph_legend.html (nonexistent)
+++ sw/html/graph_legend.html (revision 11)
@@ -0,0 +1,131 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Graph Legend
+
+
+
+
+
+
+
+
+
Graph Legend This page explains how to interpret the graphs that are generated by doxygen.
+
Consider the following example:
+
+class Invisible { };
+
+
+class Truncated : public Invisible { };
+
+
+class Undocumented { };
+
+
+class PublicBase : public Truncated { };
+
+
+template <class T> class Templ { };
+
+
+class ProtectedBase { };
+
+
+class PrivateBase { };
+
+
+class Used { };
+
+
+class Inherited : public PublicBase,
+ protected ProtectedBase,
+ private PrivateBase,
+ public Undocumented,
+ public Templ<int>
+{
+ private :
+ Used *m_usedClass;
+};
+ This will result in the following graph:
+
+
+
The boxes in the above graph have the following meaning:
+
+
+A filled gray box represents the struct or class for which the graph is generated.
+
+A box with a black border denotes a documented struct or class.
+
+A box with a grey border denotes an undocumented struct or class.
+
+A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.
+
+
The arrows have the following meaning:
+
+
+A dark blue arrow is used to visualize a public inheritance relation between two classes.
+
+A dark green arrow is used for protected inheritance.
+
+A dark red arrow is used for private inheritance.
+
+A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.
+
+A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.
+
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/tab_l.gif
===================================================================
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svn:mime-type = application/octet-stream
Index: sw/html/tab_l.gif
===================================================================
--- sw/html/tab_l.gif (nonexistent)
+++ sw/html/tab_l.gif (revision 11)
sw/html/tab_l.gif
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/ftv2mnode.png
===================================================================
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Index: sw/html/ftv2mnode.png
===================================================================
--- sw/html/ftv2mnode.png (nonexistent)
+++ sw/html/ftv2mnode.png (revision 11)
sw/html/ftv2mnode.png
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/globals_defs.html
===================================================================
--- sw/html/globals_defs.html (nonexistent)
+++ sw/html/globals_defs.html (revision 11)
@@ -0,0 +1,100 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Data Fields
+
+
+
+
+
+
+
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/main.html
===================================================================
--- sw/html/main.html (nonexistent)
+++ sw/html/main.html (revision 11)
@@ -0,0 +1,67 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Main Page
+
+
+
+
+
+
+
+
+
AES Avalon Slave (avs_aes) Documentation
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/ftv2pnode.png
===================================================================
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Index: sw/html/ftv2pnode.png
===================================================================
--- sw/html/ftv2pnode.png (nonexistent)
+++ sw/html/ftv2pnode.png (revision 11)
sw/html/ftv2pnode.png
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## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/ftv2doc.png
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Index: sw/html/ftv2doc.png
===================================================================
--- sw/html/ftv2doc.png (nonexistent)
+++ sw/html/ftv2doc.png (revision 11)
sw/html/ftv2doc.png
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+application/octet-stream
\ No newline at end of property
Index: sw/html/tab_r.gif
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Index: sw/html/tab_r.gif
===================================================================
--- sw/html/tab_r.gif (nonexistent)
+++ sw/html/tab_r.gif (revision 11)
sw/html/tab_r.gif
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+application/octet-stream
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Index: sw/html/AEStester_8c.html
===================================================================
--- sw/html/AEStester_8c.html (nonexistent)
+++ sw/html/AEStester_8c.html (revision 11)
@@ -0,0 +1,105 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): AEStester.c File Reference
+
+
+
+
+
+
+
+
+
AEStester.c File Reference
+
test program and example of how to use the software
+More...
+
#include <stdio.h>
+
#include <string.h>
+
#include <avs_aes.h >
+
+
+
+
Go to the source code of this file.
+
+Functions main ()
+
Detailed Description
+
test program and example of how to use the software
+
This file is part of the project avs_aes see: http://opencores.org/project,avs_aes
+
+
Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
+
+
Copyright (c) 2009, Authors and opencores.org All rights reserved.
+
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the organization nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+
Definition in file AEStester.c .
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/avs__aes_8h__dep__incl.png
===================================================================
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Index: sw/html/avs__aes_8h__dep__incl.png
===================================================================
--- sw/html/avs__aes_8h__dep__incl.png (nonexistent)
+++ sw/html/avs__aes_8h__dep__incl.png (revision 11)
sw/html/avs__aes_8h__dep__incl.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/avs__aes_8h__dep__incl.md5
===================================================================
--- sw/html/avs__aes_8h__dep__incl.md5 (nonexistent)
+++ sw/html/avs__aes_8h__dep__incl.md5 (revision 11)
@@ -0,0 +1 @@
+9e2dd4b5acdb07adca966e7d609d9a27
\ No newline at end of file
Index: sw/html/doxygen.png
===================================================================
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svn:mime-type = application/octet-stream
Index: sw/html/doxygen.png
===================================================================
--- sw/html/doxygen.png (nonexistent)
+++ sw/html/doxygen.png (revision 11)
sw/html/doxygen.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/globals_func.html
===================================================================
--- sw/html/globals_func.html (nonexistent)
+++ sw/html/globals_func.html (revision 11)
@@ -0,0 +1,110 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Data Fields
+
+
+
+
+
+
+
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/avs__aes_8c__incl.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: sw/html/avs__aes_8c__incl.png
===================================================================
--- sw/html/avs__aes_8c__incl.png (nonexistent)
+++ sw/html/avs__aes_8c__incl.png (revision 11)
sw/html/avs__aes_8c__incl.png
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/avs__aes_8c__incl.md5
===================================================================
--- sw/html/avs__aes_8c__incl.md5 (nonexistent)
+++ sw/html/avs__aes_8c__incl.md5 (revision 11)
@@ -0,0 +1 @@
+fc05da2a554dce16fff5991287ff35a7
\ No newline at end of file
Index: sw/html/tree.html
===================================================================
--- sw/html/tree.html (nonexistent)
+++ sw/html/tree.html (revision 11)
@@ -0,0 +1,83 @@
+
+
+
+
+
+
+
+
TreeView
+
+
+
+
+
+
AES Avalon Slave (avs_aes)
+
+
+
+
+
Index: sw/html/graph_legend.dot
===================================================================
--- sw/html/graph_legend.dot (nonexistent)
+++ sw/html/graph_legend.dot (revision 11)
@@ -0,0 +1,22 @@
+digraph G
+{
+ edge [fontname="FreeSans",fontsize="10",labelfontname="FreeSans",labelfontsize="10"];
+ node [fontname="FreeSans",fontsize="10",shape=record];
+ Node9 [shape="box",label="Inherited",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",fillcolor="grey75",style="filled" fontcolor="black"];
+ Node10 -> Node9 [dir=back,color="midnightblue",fontsize="10",style="solid",fontname="FreeSans"];
+ Node10 [shape="box",label="PublicBase",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="black",URL="$classPublicBase.html"];
+ Node11 -> Node10 [dir=back,color="midnightblue",fontsize="10",style="solid",fontname="FreeSans"];
+ Node11 [shape="box",label="Truncated",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="red",URL="$classTruncated.html"];
+ Node13 -> Node9 [dir=back,color="darkgreen",fontsize="10",style="solid",fontname="FreeSans"];
+ Node13 [shape="box",label="ProtectedBase",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="black",URL="$classProtectedBase.html"];
+ Node14 -> Node9 [dir=back,color="firebrick4",fontsize="10",style="solid",fontname="FreeSans"];
+ Node14 [shape="box",label="PrivateBase",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="black",URL="$classPrivateBase.html"];
+ Node15 -> Node9 [dir=back,color="midnightblue",fontsize="10",style="solid",fontname="FreeSans"];
+ Node15 [shape="box",label="Undocumented",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="grey75"];
+ Node16 -> Node9 [dir=back,color="midnightblue",fontsize="10",style="solid",fontname="FreeSans"];
+ Node16 [shape="box",label="Templ< int >",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="black",URL="$classTempl.html"];
+ Node17 -> Node16 [dir=back,color="orange",fontsize="10",style="dashed",label="< int >",fontname="FreeSans"];
+ Node17 [shape="box",label="Templ< T >",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="black",URL="$classTempl.html"];
+ Node18 -> Node9 [dir=back,color="darkorchid3",fontsize="10",style="dashed",label="m_usedClass",fontname="FreeSans"];
+ Node18 [shape="box",label="Used",fontsize="10",height=0.2,width=0.4,fontname="FreeSans",color="black",URL="$classUsed.html"];
+}
Index: sw/html/AEStester_8c__incl.map
===================================================================
--- sw/html/AEStester_8c__incl.map (nonexistent)
+++ sw/html/AEStester_8c__incl.map (revision 11)
@@ -0,0 +1,3 @@
+
+
Index: sw/html/ftv2node.png
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===================================================================
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+++ sw/html/ftv2node.png (revision 11)
sw/html/ftv2node.png
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+++ sw/html/ftv2mlastnode.png (revision 11)
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+application/octet-stream
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Index: sw/html/functions.html
===================================================================
--- sw/html/functions.html (nonexistent)
+++ sw/html/functions.html (revision 11)
@@ -0,0 +1,94 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Data Fields
+
+
+
+
+
+
+
+
+Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/AEStester_8c_source.html
===================================================================
--- sw/html/AEStester_8c_source.html (nonexistent)
+++ sw/html/AEStester_8c_source.html (revision 11)
@@ -0,0 +1,179 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): AEStester.c Source File
+
+
+
+
+
+
+
+
+
+
AEStester.c Go to the documentation of this file. #include <stdio.h>
+#include <string.h>
+#include <avs_aes.h >
+int main(){
+avs_aes_handle context;
+int i=0;
+unsigned int result[4];
+unsigned int Userkey[8] = {
+unsigned int Payload[4] = {
+"AES-Test\n" );
+avs_aes_init (&context);
+avs_aes_setKey (&context,&Userkey);
+avs_aes_setPayload (&context,&Payload);
+avs_aes_encrypt (&context);
+while (avs_aes_isBusy (&context)){
+"not ready\n" );
+"receiving 729cd44f 32a48d85 b8188185 c579ae49\n" );
+result ,4*sizeof (unsigned int ));
+for (i=0; i<4 ; i++){
+"received 0x%X \n" ,result[i]);
+avs_aes_decrypt (&context);
+while (avs_aes_isBusy (&context)){
+"not ready\n" );
+"receiving 9c7076af ac2e5716 6681d3ac 014f64c0 \n" );
+result ,4*sizeof (unsigned int ));
+for (i=0; i<4 ; i++){
+"received 0x%X \n" ,result[i]);
+avs_aes_setPayload (&context,&Payload);
+avs_aes_encrypt (&context);
+while (avs_aes_isBusy (&context)){
+"not ready\n" );
+result ,4*sizeof (unsigned int ));
+for (i=0; i<4 ; i++){
+"received 0x%X \n" ,result[i]);
+avs_aes_decrypt (&context);
+while (avs_aes_isBusy (&context)){
+"not ready\n" );
+result ,4*sizeof (unsigned int ));
+for (i=0; i<4 ; i++){
+"received 0x%X \n" ,result[i]);
+"Done \n" );
+return 0;
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/closed.gif
===================================================================
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sw/html/closed.gif
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+application/octet-stream
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Index: sw/html/ftv2vertline.png
===================================================================
--- sw/html/ftv2vertline.png (nonexistent)
+++ sw/html/ftv2vertline.png (revision 11)
sw/html/ftv2vertline.png
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===================================================================
--- sw/html/ftv2plastnode.png (nonexistent)
+++ sw/html/ftv2plastnode.png (revision 11)
sw/html/ftv2plastnode.png
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+application/octet-stream
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Index: sw/html/annotated.html
===================================================================
--- sw/html/annotated.html (nonexistent)
+++ sw/html/annotated.html (revision 11)
@@ -0,0 +1,77 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Data Structures
+
+
+
+
+
+
+
+
+
Data Structures Here are the data structures with brief descriptions:
+ avs_aes_handle Object storing addresses for this Avalon AES slave might be useful in case there are more attached, also for convinience
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/ftv2link.png
===================================================================
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svn:mime-type = application/octet-stream
Index: sw/html/ftv2link.png
===================================================================
--- sw/html/ftv2link.png (nonexistent)
+++ sw/html/ftv2link.png (revision 11)
sw/html/ftv2link.png
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+application/octet-stream
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Index: sw/html/avs__aes_8h.html
===================================================================
--- sw/html/avs__aes_8h.html (nonexistent)
+++ sw/html/avs__aes_8h.html (revision 11)
@@ -0,0 +1,521 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): avs_aes.h File Reference
+
+
+
+
+
+
+
+
+
avs_aes.h File Reference
+
header file for AES Avalon IP Core software driver offers interfaces to convinient access to the core
+More...
+
+
+
+
Go to the source code of this file.
+
+Data Structures struct avs_aes_handle object storing addresses for this Avalon AES slave might be useful in case there are more attached, also for convinience More... Defines #define KEYWORDS 8 Keylength 256 Bit AES. #define AES_BASEADDR 0x40000 base address of the Avalon Slave component in memory map #define KEY_ADDR AES_BASEADDR+0x00 memory offset for key DON'T CHANGE! #define DATA_ADDR AES_BASEADDR+0x08 memory offset of payload DON'T CHANGE! #define RESULT_ADDR AES_BASEADDR+0x10 memory offset of result DON'T CHANGE! #define AESCTRLWD AES_BASEADDR+0x18 memory offset for control word DON'T CHANGE! Functions void avs_aes_init (avs_aes_handle *context) setup the context to be used later. void avs_aes_setKey (avs_aes_handle *context, unsigned int *key) setup the context to be used later. void avs_aes_setPayload (avs_aes_handle *context, unsigned int *payload) loads payload for processing to the core basically memcopy. void avs_aes_setKeyvalid (avs_aes_handle *context) set the KEY_VALID flag in the control word used to signal the completion of writing the key ( avs_aes_setKey ) void avs_aes_encrypt (avs_aes_handle *context) set the ENCRYPT flag in the control word start encryption of (hopefully) previously loaded payload void avs_aes_decrypt (avs_aes_handle *context) set the DECRYPT flag in the control word start encryption of (hopefully) previously loaded payload int avs_aes_isBusy (avs_aes_handle *context) checks the COMPLETED flag can be used for ugly polling the slave if IRQs are not used
+
Detailed Description
+
header file for AES Avalon IP Core software driver offers interfaces to convinient access to the core
+
This file is part of the project avs_aes see: http://opencores.org/project,avs_aes
+
+
Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
+
+
Copyright (c) 2009, Authors and opencores.org All rights reserved.
+
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the organization nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+
Definition in file avs_aes.h .
+
Define Documentation
+
+
+
+
+
+ #define AES_BASEADDR 0x40000
+
+
+
+
+
+
base address of the Avalon Slave component in memory map
+
+
Definition at line 60 of file avs_aes.h .
+
+
+
+
+
+
+
+
+ #define AESCTRLWD AES_BASEADDR+0x18
+
+
+
+
+
+
memory offset for control word DON'T CHANGE!
+
+
Definition at line 75 of file avs_aes.h .
+
+
+
+
+
+
+
+
+ #define DATA_ADDR AES_BASEADDR+0x08
+
+
+
+
+
+
memory offset of payload DON'T CHANGE!
+
+
Definition at line 71 of file avs_aes.h .
+
+
+
+
+
+
+
+
+ #define KEY_ADDR AES_BASEADDR+0x00
+
+
+
+
+
+
memory offset for key DON'T CHANGE!
+
+
Constants no need to change them!
+
+
Definition at line 69 of file avs_aes.h .
+
+
+
+
+
+
+
+
+ #define KEYWORDS 8
+
+
+
+
+
+
Keylength 256 Bit AES.
+
+
Configuration items for the Avalon Slave component change them or define them elsewhere
+
+
Definition at line 53 of file avs_aes.h .
+
+
+
+
+
+
+
+
+ #define RESULT_ADDR AES_BASEADDR+0x10
+
+
+
+
+
+
memory offset of result DON'T CHANGE!
+
+
Definition at line 73 of file avs_aes.h .
+
+
+
+
Function Documentation
+
+
+
+
+
+
set the DECRYPT flag in the control word start encryption of (hopefully) previously loaded payload
+
Parameters:
+
+ context struct grouping address information
+
+
+
+
Definition at line 115 of file avs_aes.c .
+
+
control ) |= 0x00000002;
+
+
+
+
+
+
+
+
+
+
set the ENCRYPT flag in the control word start encryption of (hopefully) previously loaded payload
+
Parameters:
+
+ context struct grouping address information
+
+
+
+
Definition at line 106 of file avs_aes.c .
+
+
control ) |= 0x00000001;
+
+
+
+
+
+
+
+
+
+
setup the context to be used later.
+
+
initializes the pointers to the correct memory locations
+
Parameters:
+
+ context : struct grouping address information
+
+
+
initializes the pointers to the correct memory locations
+
Parameters:
+
+ context : struct grouping address information
+
+
+
+
Definition at line 47 of file avs_aes.c .
+
+
+
+
+
+
+
+
+
+
+
checks the COMPLETED flag can be used for ugly polling the slave if IRQs are not used
+
Parameters:
+
+ context struct grouping address information
+
+
+
Returns: 1 if still computing 0 if done.
+
+
Definition at line 125 of file avs_aes.c .
+
+
unsigned int mycontrol = *(context->control );
+return mycontrol & 0x03;
+
+
+
+
+
+
+
+
+
+ void avs_aes_setKey
+ (
+ avs_aes_handle * context ,
+
+
+ unsigned int *
+ key
+
+
+ )
+
+
+
+
+
+
setup the context to be used later.
+
initializes the pointers to the correct memory locations
+
Parameters:
+
+ context struct grouping address information key user key to load
+
+
+
+
Definition at line 62 of file avs_aes.c .
+
+
int i=0;
+unsigned int * target_ptr = (unsigned int * )context->key ;
+control ) &= (~0x00000080);
+for (i=0; i<KEYWORDS ; i++){
+control ) |= 0x00000080;
+
+
+
+
+
+
+
+
+
+ void avs_aes_setKeyvalid
+ (
+ avs_aes_handle * context
+ )
+
+
+
+
+
+
set the KEY_VALID flag in the control word used to signal the completion of writing the key ( avs_aes_setKey )
+
Parameters:
+
+ context struct grouping address information
+
+
+
+
Definition at line 96 of file avs_aes.c .
+
+
control ) |= 0x00000080;
+
+
+
+
+
+
+
+
+
+ void avs_aes_setPayload
+ (
+ avs_aes_handle * context ,
+
+
+ unsigned int *
+ payload
+
+
+ )
+
+
+
+
+
+
loads payload for processing to the core basically memcopy.
+
..
+
Parameters:
+
+ context struct grouping address information payload user data to be processed
+
+
+
+
Definition at line 81 of file avs_aes.c .
+
+
int i=0;
+unsigned int * target_ptr = (unsigned int * )context->payload ;
+for (i=0; i<4; i++){
+
+
+
+
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/avs__aes_8h__dep__incl.map
===================================================================
--- sw/html/avs__aes_8h__dep__incl.map (nonexistent)
+++ sw/html/avs__aes_8h__dep__incl.map (revision 11)
@@ -0,0 +1,4 @@
+
+
Index: sw/html/globals.html
===================================================================
--- sw/html/globals.html (nonexistent)
+++ sw/html/globals.html (revision 11)
@@ -0,0 +1,128 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Data Fields
+
+
+
+
+
+
+
+
+Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/avs__aes_8c__incl.map
===================================================================
--- sw/html/avs__aes_8c__incl.map (nonexistent)
+++ sw/html/avs__aes_8c__incl.map (revision 11)
@@ -0,0 +1,3 @@
+
+
Index: sw/html/ftv2folderclosed.png
===================================================================
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===================================================================
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+++ sw/html/ftv2folderclosed.png (revision 11)
sw/html/ftv2folderclosed.png
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Index: sw/html/avs__aes_8c_source.html
===================================================================
--- sw/html/avs__aes_8c_source.html (nonexistent)
+++ sw/html/avs__aes_8c_source.html (revision 11)
@@ -0,0 +1,199 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): avs_aes.c Source File
+
+
+
+
+
+
+
+
+
+
avs_aes.c Go to the documentation of this file. #include <avs_aes.h >
+#include <string.h>
+00047 void avs_aes_init (avs_aes_handle * context){
+key = (unsigned int *) KEY_ADDR ;
+payload = (unsigned int *) DATA_ADDR ;
+result = (unsigned int *) RESULT_ADDR ;
+control = (unsigned int *) AESCTRLWD ;
+control ) = 0x00000000;
+00062 void avs_aes_setKey (avs_aes_handle * context, unsigned int * key){
+int i=0;
+unsigned int * target_ptr = (unsigned int * )context->key ;
+control ) &= (~0x00000080);
+for (i=0; i<KEYWORDS ; i++){
+control ) |= 0x00000080;
+00081 void avs_aes_setPayload (avs_aes_handle * context, unsigned int * payload){
+int i=0;
+unsigned int * target_ptr = (unsigned int * )context->payload ;
+for (i=0; i<4; i++){
+00096 void avs_aes_setKeyvalid (avs_aes_handle * context){
+control ) |= 0x00000080;
+00106 void avs_aes_encrypt (avs_aes_handle * context){
+control ) |= 0x00000001;
+00115 void avs_aes_decrypt (avs_aes_handle * context){
+control ) |= 0x00000002;
+00125 int avs_aes_isBusy (avs_aes_handle * context){
+unsigned int mycontrol = *(context->control );
+return mycontrol & 0x03;
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/ftv2lastnode.png
===================================================================
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Index: sw/html/ftv2lastnode.png
===================================================================
--- sw/html/ftv2lastnode.png (nonexistent)
+++ sw/html/ftv2lastnode.png (revision 11)
sw/html/ftv2lastnode.png
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+application/octet-stream
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Index: sw/html/classes.html
===================================================================
--- sw/html/classes.html (nonexistent)
+++ sw/html/classes.html (revision 11)
@@ -0,0 +1,78 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Alphabetical List
+
+
+
+
+
+
+
+
+
Data Structure Index
+
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/avs__aes_8h_source.html
===================================================================
--- sw/html/avs__aes_8h_source.html (nonexistent)
+++ sw/html/avs__aes_8h_source.html (revision 11)
@@ -0,0 +1,230 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): avs_aes.h Source File
+
+
+
+
+
+
+
+
+
+
avs_aes.h Go to the documentation of this file. #ifndef AVS_AES_H_
+#define AVS_AES_H_
+#ifndef KEYWORDS
+00053 #define KEYWORDS 8
+#endif
+#ifndef AES_BASEADDR
+00060 #define AES_BASEADDR 0x40000
+#endif
+00069 #define KEY_ADDR AES_BASEADDR+0x00
+00071 #define DATA_ADDR AES_BASEADDR+0x08
+00073 #define RESULT_ADDR AES_BASEADDR+0x10
+00075 #define AESCTRLWD AES_BASEADDR+0x18
+00081 typedef struct {
+00085 volatile unsigned int * key;
+00090 volatile unsigned int * payload;
+00094 volatile unsigned int * result;
+00098 volatile unsigned int * control;
+avs_aes_handle ;
+void avs_aes_init (avs_aes_handle * context);
+void avs_aes_setKey (avs_aes_handle * context, unsigned int * key);
+void avs_aes_setPayload (avs_aes_handle * context, unsigned int * payload);
+void avs_aes_setKeyvalid (avs_aes_handle * context);
+void avs_aes_encrypt (avs_aes_handle * context);
+void avs_aes_decrypt ( avs_aes_handle * context);
+int avs_aes_isBusy (avs_aes_handle * context);
+#endif
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/graph_legend.png
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: sw/html/graph_legend.png
===================================================================
--- sw/html/graph_legend.png (nonexistent)
+++ sw/html/graph_legend.png (revision 11)
sw/html/graph_legend.png
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+application/octet-stream
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Index: sw/html/structavs__aes__handle.html
===================================================================
--- sw/html/structavs__aes__handle.html (nonexistent)
+++ sw/html/structavs__aes__handle.html (revision 11)
@@ -0,0 +1,166 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): avs_aes_handle Struct Reference
+
+
+
+
+
+
+
+
+
avs_aes_handle Struct Reference
+
object storing addresses for this Avalon AES slave might be useful in case there are more attached, also for convinience
+More...
+
+
#include <avs_aes.h >
+
+Data Fields volatile unsigned int * key pointer "KEY" field in memory mapping volatile unsigned int * payload pointer "data" field in memory mapping used for both decryption and encryption volatile unsigned int * result pointer "RESULT" field in memory mapping volatile unsigned int * control pointer to control word
+
Detailed Description
+
object storing addresses for this Avalon AES slave might be useful in case there are more attached, also for convinience
+
+
Definition at line 81 of file avs_aes.h .
+
Field Documentation
+
+
+
+
+
+
pointer to control word
+
+
Definition at line 98 of file avs_aes.h .
+
+
+
+
+
+
+
+
+
pointer "KEY" field in memory mapping
+
+
Definition at line 85 of file avs_aes.h .
+
+
+
+
+
+
+
+
+
pointer "data" field in memory mapping used for both decryption and encryption
+
+
Definition at line 90 of file avs_aes.h .
+
+
+
+
+
+
+
+
+
pointer "RESULT" field in memory mapping
+
+
Definition at line 94 of file avs_aes.h .
+
+
+
+
The documentation for this struct was generated from the following file:
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/doxygen.css
===================================================================
--- sw/html/doxygen.css (nonexistent)
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Index: sw/html/files.html
===================================================================
--- sw/html/files.html (nonexistent)
+++ sw/html/files.html (revision 11)
@@ -0,0 +1,78 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): File Index
+
+
+
+
+
+
+
+
+
File List Here is a list of all documented files with brief descriptions:
+ AEStester.c [code] Test program and example of how to use the software avs_aes.c [code] AES Avalon IP Core software driver avs_aes.h [code] Header file for AES Avalon IP Core software driver offers interfaces to convinient access to the core
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/open.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: sw/html/open.gif
===================================================================
--- sw/html/open.gif (nonexistent)
+++ sw/html/open.gif (revision 11)
sw/html/open.gif
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: sw/html/functions_vars.html
===================================================================
--- sw/html/functions_vars.html (nonexistent)
+++ sw/html/functions_vars.html (revision 11)
@@ -0,0 +1,94 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): Data Fields - Variables
+
+
+
+
+
+
+
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: sw/html/index.html
===================================================================
--- sw/html/index.html (nonexistent)
+++ sw/html/index.html (revision 11)
@@ -0,0 +1,16 @@
+
+
+
+
+
AES Avalon Slave (avs_aes)
+
+
+ <![CDATA[
+ <body>
+ <a href="main.html">Frames are disabled. Click here to go to the main page.</a>
+ </body>
+ ]]>
+
+
Index: sw/html/tab_b.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: sw/html/tab_b.gif
===================================================================
--- sw/html/tab_b.gif (nonexistent)
+++ sw/html/tab_b.gif (revision 11)
sw/html/tab_b.gif
Property changes :
Added: svn:mime-type
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Index: sw/html/ftv2blank.png
===================================================================
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svn:mime-type = application/octet-stream
Index: sw/html/ftv2blank.png
===================================================================
--- sw/html/ftv2blank.png (nonexistent)
+++ sw/html/ftv2blank.png (revision 11)
sw/html/ftv2blank.png
Property changes :
Added: svn:mime-type
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Index: sw/html/avs__aes_8c.html
===================================================================
--- sw/html/avs__aes_8c.html (nonexistent)
+++ sw/html/avs__aes_8c.html (revision 11)
@@ -0,0 +1,389 @@
+
+
+
+
+
AES Avalon Slave (avs_aes): avs_aes.c File Reference
+
+
+
+
+
+
+
+
+
avs_aes.c File Reference
+
AES Avalon IP Core software driver.
+More...
+
#include <avs_aes.h >
+
#include <string.h>
+
+
+
+
Go to the source code of this file.
+
+
Detailed Description
+
AES Avalon IP Core software driver.
+
This file is part of the project avs_aes see: http://opencores.org/project,avs_aes
+
+
Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
+
+
Copyright (c) 2009, Authors and opencores.org All rights reserved.
+
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of the organization nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
+
+
Definition in file avs_aes.c .
+
Function Documentation
+
+
+
+
+
+
set the DECRYPT flag in the control word start encryption of (hopefully) previously loaded payload
+
Parameters:
+
+ context struct grouping address information
+
+
+
+
Definition at line 115 of file avs_aes.c .
+
+
control ) |= 0x00000002;
+
+
+
+
+
+
+
+
+
+
set the ENCRYPT flag in the control word start encryption of (hopefully) previously loaded payload
+
Parameters:
+
+ context struct grouping address information
+
+
+
+
Definition at line 106 of file avs_aes.c .
+
+
control ) |= 0x00000001;
+
+
+
+
+
+
+
+
+
+
setup the context to be used later.
+
initializes the pointers to the correct memory locations
+
Parameters:
+
+ context : struct grouping address information
+
+
+
+
Definition at line 47 of file avs_aes.c .
+
+
+
+
+
+
+
+
+
+
+
checks the COMPLETED flag can be used for ugly polling the slave if IRQs are not used
+
Parameters:
+
+ context struct grouping address information
+
+
+
Returns: 1 if still computing 0 if done.
+
+
Definition at line 125 of file avs_aes.c .
+
+
unsigned int mycontrol = *(context->control );
+return mycontrol & 0x03;
+
+
+
+
+
+
+
+
+
+ void avs_aes_setKey
+ (
+ avs_aes_handle * context ,
+
+
+ unsigned int *
+ key
+
+
+ )
+
+
+
+
+
+
setup the context to be used later.
+
initializes the pointers to the correct memory locations
+
Parameters:
+
+ context struct grouping address information key user key to load
+
+
+
+
Definition at line 62 of file avs_aes.c .
+
+
int i=0;
+unsigned int * target_ptr = (unsigned int * )context->key ;
+control ) &= (~0x00000080);
+for (i=0; i<KEYWORDS ; i++){
+control ) |= 0x00000080;
+
+
+
+
+
+
+
+
+
+ void avs_aes_setKeyvalid
+ (
+ avs_aes_handle * context
+ )
+
+
+
+
+
+
set the KEY_VALID flag in the control word used to signal the completion of writing the key ( avs_aes_setKey )
+
Parameters:
+
+ context struct grouping address information
+
+
+
+
Definition at line 96 of file avs_aes.c .
+
+
control ) |= 0x00000080;
+
+
+
+
+
+
+
+
+
+ void avs_aes_setPayload
+ (
+ avs_aes_handle * context ,
+
+
+ unsigned int *
+ payload
+
+
+ )
+
+
+
+
+
+
loads payload for processing to the core basically memcopy.
+
..
+
Parameters:
+
+ context struct grouping address information payload user data to be processed
+
+
+
+
Definition at line 81 of file avs_aes.c .
+
+
int i=0;
+unsigned int * target_ptr = (unsigned int * )context->payload ;
+for (i=0; i<4; i++){
+
+
+
+
+
+
Generated on Fri Apr 2 23:22:36 2010 for AES Avalon Slave (avs_aes) by
+
+ 1.6.1
+
+
Index: manual/src/avs_aes.ist
===================================================================
--- manual/src/avs_aes.ist (nonexistent)
+++ manual/src/avs_aes.ist (revision 11)
@@ -0,0 +1,15 @@
+% makeindex style file created by LaTeX for document "avs_aes" on 2010-4-2
+keyword "\\glossaryentry"
+preamble "\\begin{theglossary}"
+postamble "\n\\end{theglossary}\n"
+group_skip "\\gloskip "
+item_0 "\n\n\\gloitem "
+delim_0 "\n\\glodelim "
+page_compositor "-"
+delim_n "\\delimN "
+delim_r "\\delimR "
+delim_t "\\delimT "
+headings_flag 1
+heading_prefix "\\glogroup"
+symhead_positive "Symbols"
+numhead_positive "Numbers"
Index: manual/src/avs_aes.bbl
===================================================================
--- manual/src/avs_aes.bbl (nonexistent)
+++ manual/src/avs_aes.bbl (revision 11)
@@ -0,0 +1,73 @@
+% Generated by IEEEtran.bst, version: 1.12 (2007/01/11)
+\begin{thebibliography}{1}
+\providecommand{\url}[1]{#1}
+\csname url@samestyle\endcsname
+\providecommand{\newblock}{\relax}
+\providecommand{\bibinfo}[2]{#2}
+\providecommand{\BIBentrySTDinterwordspacing}{\spaceskip=0pt\relax}
+\providecommand{\BIBentryALTinterwordstretchfactor}{4}
+\providecommand{\BIBentryALTinterwordspacing}{\spaceskip=\fontdimen2\font plus
+\BIBentryALTinterwordstretchfactor\fontdimen3\font minus
+ \fontdimen4\font\relax}
+\providecommand{\BIBforeignlanguage}[2]{{%
+\expandafter\ifx\csname l@#1\endcsname\relax
+\typeout{** WARNING: IEEEtran.bst: No hyphenation pattern has been}%
+\typeout{** loaded for the language `#1'. Using the pattern for}%
+\typeout{** the default language instead.}%
+\else
+\language=\csname l@#1\endcsname
+\fi
+#2}}
+\providecommand{\BIBdecl}{\relax}
+\BIBdecl
+
+\bibitem{NIST:Fips197}
+\BIBentryALTinterwordspacing
+``Fips-197 announcing the advanced encryption standard (aes),'' National
+ Institute of Standards and Technology (NIST), 100 Bureau Drive, Stop 1070,
+ Gaithersburg, MD, US, Nov. 2001. [Online]. Available:
+ \url{http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf}
+\BIBentrySTDinterwordspacing
+
+\bibitem{Wiki:AvWb}
+\BIBentryALTinterwordspacing
+``Wishbone - computer bus,'' wikipedia.org. [Online]. Available:
+ \url{http://en.wikipedia.org/wiki/Wishbone\_computer\_bus)#Comparisons}
+\BIBentrySTDinterwordspacing
+
+\bibitem{OC:WBspec}
+\BIBentryALTinterwordspacing
+R.~Herveille, ``Wishbone soc architecture specification, revision b.3,''
+ Opencores Organization, Sept. 2002. [Online]. Available:
+ \url{http://www.opencores.org/downloads/wbspec_b3.pdf}
+\BIBentrySTDinterwordspacing
+
+\bibitem{Altera:Avalon}
+\BIBentryALTinterwordspacing
+``Avalon interface specification,'' Altera Corporation, 101 Innovation Drive,
+ San Jose, CA, US, 2005. [Online]. Available:
+ \url{http://www.altera.com/literature/manual/mnl\_avalon\_spec.pdf}
+\BIBentrySTDinterwordspacing
+
+\bibitem{Xilinx:wp284}
+\BIBentryALTinterwordspacing
+A.~Percey, ``Advantages of the virtex-5 fpga 6-input lut architecture,'' Xilinx
+ Inc., 2100 Logic Drive, San Jose CA USA, Dec. 2007. [Online]. Available:
+ \url{http://www.xilinx.com/support/documentation/white_papers/wp284.pdf}
+\BIBentrySTDinterwordspacing
+
+\bibitem{Altera:01007}
+\BIBentryALTinterwordspacing
+``Stratix iii fpgas vs. xilinx virtex-5 devices: Architecture and performance
+ comparison,'' Altera Corporation, 101 Innovation Drive, San Jose CA USA, Oct.
+ 2007. [Online]. Available:
+ \url{http://www.altera.com/literature/wp/wp-01007.pdf}
+\BIBentrySTDinterwordspacing
+
+\bibitem{LaBr05}
+\BIBentryALTinterwordspacing
+L.~Brown, ``Aes calculator,'' ADFA, Canberra, Australia, 2005. [Online].
+ Available: \url{http://www.unsw.adfa.edu.au/~lpb/src/AEScalc/index.html}
+\BIBentrySTDinterwordspacing
+
+\end{thebibliography}
Index: manual/src/avs_aes.tex
===================================================================
--- manual/src/avs_aes.tex (nonexistent)
+++ manual/src/avs_aes.tex (revision 11)
@@ -0,0 +1,471 @@
+\documentclass{ruschidoc}
+
+\usepackage[
+ bookmarks,
+ plainpages={false}]{hyperref}
+
+\usepackage[
+ style=altlist,
+ hyper=true,
+ number=none,
+ acronym=true,
+ header=none]{glossary}
+\usepackage{capt-of}
+
+%%% Water mark
+%\usepackage{draftwatermark}
+%\SetWatermarkText{\shortstack{DRAFT}}
+%\SetWatermarkScale{0.9}
+%\SetWatermarkLightness{0.85}
+
+\makeacronym
+\makeglossary
+\input{acronym}
+\input{glossary}
+\bibliographystyle{IEEEtran}
+
+%%%%%%%%%%%%%%%%%
+% Document variables
+%%%%%%%%%%%%%%%%%
+\docDate{ \today }
+\docID{avs\_aes\_doc}
+\docRevision{0.5}
+\docStatus{Final}
+\docTitle{\mbox{AES 128/192/256 (ECB)} \mbox{Avalon\rtm-MM Slave}}
+\keywords{Avalon, bus, slave, cryptography, AES, ecb, IP core }
+
+\authorName{\mbox{Thomas Ruschival} \\ and opencores.org}
+\authorURL{www.opencores.org}
+\authorAddress{\mbox{}}
+\authorEmail{ruschi@opencores.org}
+
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% FORMAT: Rev | Chapter | Description | Date | Reviewer \\
+\revisionList{
+0.1 & all & initial document & 2009/02/01 & T. Ruschival \\
+0.2 & all & added interrupt & 2009/03/25 & T. Ruschival \\
+0.3 & all & added generics & 2009/04/20 & T. Ruschival \\
+0.4 & all & cleanup for opencores.org & 2009/05/20 & T. Ruschival \\
+0.5 & all & final release & 2010/03/07 & T. Ruschival \\
+0.6 & 3,6 & fixed memory map, added testbench description & 2010/04/02 & T. Ruschival \\
+}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+
+
+\begin{document}
+\maketitle
+\newpage
+\tableofcontents
+\newpage
+
+\section{Introduction}
+\label{sec:intro} The \AES is a symmetric block cypher operating on fixed block sizes
+of 128 Bit and is specified for key sizes of 128, 192 and 256 Bit designed by Joan
+Daemen and Vincent Rijmen. The algorithm was standardized by \NIST. For more
+information on the algorithm see \cite{NIST:Fips197}.\\
+This component implements an AES encryption decryption datapath in \ECB mode with
+either 128,192 or 256 Bit keys. The keylength is determined by generics at compile
+time. Also the decryption datapath can be disabled by generics if it is not needed
+for the application.\\
+The component provides an Avalon\rtm\ Memory Mapped (Avalon-MM) slave interface to
+connect to an Altera\rtm\ Avalon\rtm\ switch fabric. The Avalon\rtm\ interface is
+implemented in a way that it can also be used to connect to a Whishbone master if the
+signals are correctly mapped, see \cite{Wiki:AvWb}. For further information about the
+Whishbone bus refer to \cite{OC:WBspec}. \\
+
+\section{Interface}
+\label{sec:interface}
+The AES core is accessed by the interface described in this section. An Avalon\rtm\
+interface was chosen for its simplicity and compatibility with wishbone. Furthermore
+Avalon\rtm\ defines interrupt request signals for slaves which would be separate
+signals in a Wishbone implementation.The component can be used both in polling
+mode or can provide an interrupt for signalling. \\
+Unfortunately Avalon\rtm\ is an Altera\rtm\ proprietary technology. The actual AES
+core however is a selfcontained entity and can be embedded into other \SoC\ bus
+interfaces as well or used indepentently.
+
+\subsection{Configuration Generics}
+\label{sec:generics}
+The AES core can be configured by generics shown in table \ref{tab:generics},
+consequently they are provided by the Avalon\rtm\ interface.
+
+\begin{tabularx}{\textwidth}{|p{33mm}|p{25mm}|X|}
+ \hline
+ \bf{Generic name} & \bf{type} & \bf{Description}\\ \hline
+ \texttt{KEYLENGTH} \label{gen:keylength} & NATURAL & Size of initial userkey. Must be 128, 192 or 256 \footnotemark[1] . \\ \hline
+ \texttt{DECRYPTION} \label{gen:decryption} & BOOLEAN & Enables the instantiation of the decrypt datapath if true. \\
+\hline
+\end{tabularx}
+\footnotetext[1]{All other values raise a compilation failure}
+\captionof{table}{Component generics}
+\label{tab:generics}
+Note: \texttt{KEYLENGTH} of 192 fail synthesis with Xilinx ISE \rtm\ because of division by 6 in key schedule that cannot be mapped to shift operations (\texttt{keyexpansion.vhd}).
+
+\subsection{Signals}
+\label{sec:signals}
+The Avalon\rtm\-MM Slave interface is described in \cite{Altera:Avalon}, the component
+implements the signals shown in table \ref{tab:signals}. All signals are synchronous,
+sampled at the rising edge of the clock. The type for all signals is \texttt{IEEE1164
+ std\_logic} or \texttt{std\_logic\_vector}. For signals wider that 1 Bit the range
+is \MSB\ \texttt{downto} \LSB\. \\
+This components has only output signals driven by registers no input signals are directly combinatorially connected to the
+output signals, thus combinational loops are avoided. All signals are active
+high. This component does not support burst transfers.
+
+\begin{tabularx}{\textwidth}{|p{30mm}|p{11mm}|p{11mm}|X|}
+ \hline
+ \bf{Signal name} & \bf{Width} & \bf{In/Out} & \bf{Description}\\ \hline
+ \texttt{clk} \label{sig:clk} & 1 & in & Avalon\rtm\ bus clock, also used to drive the core. \\ \hline
+ \texttt{reset} \label{sig:reset}& 1 & in & \emph{Synchronous} reset signal for Avalon\rtm\ bus interface.
+ The core itself is designed without need for reset signals.
+ \\ \hline
+ \texttt{writedata} \label{sig:writedata} & 32 & in & Input data to write to location designated by \texttt{address}. Bit 31 is most significant Bit.
+ \\ \hline
+ \texttt{address} \label{sig:address} & 5 & in & Word offset to the components base address. The memory map of the component for the
+ respective offest is described in \ref{sec:memmap}. Only full 32-Bit words can be addressed no byte addressing is implemented.
+ \\ \hline
+ \texttt{write}\footnotemark[1] \label{sig:write} & 1 & in & If asserted enable write of data at \texttt{writedata} to location designated by \texttt{address}.
+ \\ \hline
+ \texttt{read}\footnotemark[1] \label{sig:read} & 1 & in & If asserted output data at location designated by \texttt{address} to \texttt{readdata}.
+ \\ \hline
+ \texttt{readdata} \label{sig:readdata} & 32 & out & Data output port for reading data at the location defined by \texttt{address}. Bit 31 is most significant Bit.
+ \\ \hline
+ \texttt{waitrequest} \label{sig:waitrequest} & 1 & out & Asserted if writedata was not accepted, this is the case if the keyexpansion is
+ not yet complete and a new is written to the \texttt{KEY} address range without previous deassertion of the \texttt{KEY\_VALID} Bit
+ \\ \hline
+ \texttt{irq}\label{sig:irq} & 1 & out & If Interrupt behaviour is enabled \texttt{IRQ}
+ will be asserted when the operation has terminated. For use of interrupt see \ref{sec:irq}
+ \\ \hline
+\end{tabularx}
+\footnotetext[1]{\texttt{read} and \texttt{write} are mutually exclusive and must not be asserted simultanously.}
+\label{tab:signals}
+\captionof{table}{Avalon\rtm\ Bus interface signals}
+
+
+\section{Memory Map}
+\label{sec:memmap}
+The AES core Avalon\rtm\ slave has an address space of 31 words accessable through the
+offset described by the signal \texttt{address}, see \ref{sig:address}. This address
+space is devided into three main sections for the 4-word input data, the 4-word
+result of the operation and the user key. The actual lenght of the userkey can vary
+between 4, 6 and 8 words depending on the keysize. For control signals and status
+information of the component and a control word is provided. The memory mapping is
+descibed in table \ref{tab:memmap}.\\
+
+\begin{tabularx}{\textwidth}{|p{18mm}|p{14mm} |X|}
+ \hline
+ \bf{Offset} & \bf{Name} & \bf{Description}\\ \hline
+ \texttt{0x00-0x07} & \texttt{KEY} & Initial user key that will be used for encryption and decryption.
+ The most significant word is written to offset \texttt{0x00}. This memory section is \emph{write-only} to the Avalon\rtm\ interface.\\
+\hline
+ \texttt{0x08-0x0B} & \texttt{DATA} & Input data, can be either interpreted as cyphertext for decryption or plain text for encryption.
+ The most significant word shall be written to offset \texttt{0x08}. This memory section is \emph{write-only} to the Avalon\rtm\ interface. \\
+\hline
+ \texttt{0x10-0x13} & \texttt{RESULT} & Result of the operation. The most significant word of the result at offset \texttt{0x10}.
+ This memory section is \emph{read-only} to the Avalon\rtm\ Interface. \\
+\hline
+ \texttt{0x14-0x1E} & --- & reserved \\ \hline
+ \texttt{0x1F} & \texttt{CTRL} & Control and status word of the component can be read and written. Detailed description see \ref{sec:ctrl}\\
+\hline
+\end{tabularx}
+\label{tab:memmap}
+\captionof{table}{Memory map of the AES core Avalon\rtm\ slave}
+
+\subsection{Control Register}
+\label{sec:ctrl}
+The AES Core offers the register \texttt{CTRL} to control the function of the core
+and poll its status. The control register can be accessed in read and write mode.
+ When wrriting to the register reserved Bits shall be assigned a value of \texttt{0}.
+ Individual Bits have following functionality decribed in table \ref{tab:ctrlreg}. \\
+In case of a Avalon\rtm\ Bus reset this register is set to \texttt{0x00000000} thus
+invalidating all previously written keys and resetting the AES core.
+
+\begin{tabularx}{\textwidth}{|p{13mm}|p{18mm} |X|}
+ \hline
+ \bf{Offset} & \bf{Name} & \bf{Description}\\ \hline
+ \texttt{31-8} & --- & reserved \\ \hline
+ \texttt{7} &\texttt{KEY\_VALID} &If asserted key data in the \texttt{KEY} memory range is regarded valid and will be expanded to roundkeys.
+ When deasserted all keys are invalidated and the current operation of the core is aborted. It must be asserted as long as the key shall be
+ used for either encryption or decryption. This bit must be cleared for one clock cylce to load a new key. \\ \hline
+ \texttt{6} & \texttt{IRQ\_ENA} & Enable use of the interrupt request signal. If asserted the component will set \texttt{IRQ} after
+ completing an operation. If not set the component operates in polling mode only.\\ \hline
+ \texttt{5-2} & --- &reserved \\ \hline
+ \texttt{1} & \texttt{DEC} \footnotemark[1] & If asserted memory content of the \texttt{DATA} range is regarded to be valid and will be
+ \emph{decrypted}. This Bit shall only be deasserted externally if a running AES operation is aborted by deasserting \texttt{KEY\_VALID}. 1
+ It will be set \texttt{0} by the core to signal completion of the operation.\\ \hline
+ \texttt{0} & \texttt{ENC} \footnotemark[1] & If asserted memory content of the \texttt{DATA} range is regarded to be valid and will be
+ \emph{encrypted}. This Bit shall only be deasserted externally if a running AES operation is aborted by deasserting \texttt{KEY\_VALID}.
+ It will be set \texttt{0} by the core to signal completion of the operation. \\ \hline
+\end{tabularx}
+\footnotetext[1]{\texttt{ENC} and \texttt{DEC} are mutually exclusive and must not be asserted simultanously.}
+\label{tab:ctrlreg}
+\captionof{table}{Bits in the control register}
+
+
+\section{Protocol Sequence}
+\label{sec:usage}
+The AES component appears as memory mapped peripheral. All writes are fundamental slave write transfers, see \cite{Altera:Avalon} and take one
+clock cycle of the Avalon\rtm\ bus clock \texttt{clk}. It is not necessary to write all words of a input parameter successively or in one transfer.
+Bursts are not supported.\\
+\\
+Before any AES operation can be started the initial userkey has to be written to
+\texttt{KEY} segment of the memory map.After the user key is transferred
+to the component the \texttt{KEY\_VALID} Bit must be set to start the key
+expansion. This Bit can be set simultanously with \texttt{DEC} or \texttt{ENC} Bit of
+the control register. To invalidate the previous key and use another key the
+\texttt{KEY\_VALID} must be deasserted for at least one Avalon\rtm\ bus clock cycle
+During this cycle the new key can already be transferred.\\
+\\
+Once a key is passed and marked valid data blocks can be transferred to the
+\texttt{DATA} segment of the memory map.
+The AES operation is started by asserting the \texttt{ENC} Bit for
+encryption or \texttt{DEC} Bit for decryption.
+While asserting \texttt{ENC} or \texttt{DEC} the \texttt{KEY\_VALID} Bit must be
+kept asserted.\\
+The \texttt{ENC} or \texttt{DEC} Bit respectively is deasserted by the component
+after completing the requested operation.
+The result of the operation can be read from the \texttt{RESULT} area of the memory
+and is not cleared. It will be overwritten by succeeding operations.
+
+The underlying AES core uses the \FSM\ shown in \ref{fig:aesFSM} for processing of
+the data. The signals \texttt{data\_stable} and \texttt{key\_stable} are accessible
+over the control status word \texttt{CTRL} \ref{sec:ctrl}. \texttt{key\_ready} is a
+signal driven by the keygenerator when all keys are expanded. The signal
+\texttt{round\_index} is the counter for the rounds and the address to select a
+roundkey. \\
+\texttt{NO\_ROUNDS} is the total number of rounds the processing takes, a constant
+defined by the generic \texttt{KEYLENGTH} \ref{sec:generics}. The AES standard
+in\cite{NIST:Fips197} defines 10 rounds for 128 Bit key, 12 rounds for a 192 Bit key
+and 14 rounds for a 265 Bit key.\\
+Thus depending on the keylength the processing of a datablock needs at maximum 15
+clockcycles from \texttt{data\_stable=1} to completion, if the key is already expanded.
+
+\begin{figure}[!ht]
+ \centering
+ \includegraphics[width=100mm]{encrypt_FSM}
+ \caption{Finite State Machine of encryption and decryption process}
+ \label{fig:aesFSM}
+\end{figure}
+
+
+\subsection{Interrupt Behaviour}
+\label{sec:irq}
+By setting \texttt{IRQ\_ENA} in the control register \ref{sec:ctrl} the
+component is configured to issue interrupt requests.
+If \texttt{IRQ\_ENA} is asserted the interrupt request \texttt{IRQ} \ref{sig:irq} will be set when the
+computation has completed in addition to clearing the \texttt{ENC} or \texttt{DEC}
+Bit.
+The \texttt{IRQ} \ref{sig:irq} signal will remain set until clearing \texttt{IRQ\_ENA}
+or a read operation on the \texttt{RESULT} area of the components address range.
+
+
+\section{Ressource Usage and Throughput}
+\label{sec:ressources}
+
+The Avalon\rtm\ interface communicates a 32-Bit DWORD per clock cycle. Therefore a key is transmitted in 4 to 8 cyles
+plus one cyle to activate keyexpansion with the control word \ref{sec:ctrl}. A payload datablock or the result consist
+always of 4 DWORDs, thus it takes 4 cyles to send data to the core, one cycle to activate the computation with the
+control register \ref{sec:ctrl} and 4 cycles to retrieve the data.
+
+The keyexpansion component computes one column of a roundkey each clock cylce. AES takes, depending on the keylength,
+10, 12 or 14 roundkeys with each 4 columns, see \cite{NIST:Fips197}. The keyexpansion therefore takes 40, 48 or 56
+cycles until the encryption or decryption can start. The roundkeys are stored until invalidated, see \ref{sec:usage}
+thus this step is is only needed once after power-up until the key changes.
+
+The AES-core computes one iteration (round) of the Rijndael-Algorithm each clock cycle, thus a 128 Bit datablock is
+encrypted or decrypted in 10, 12 or 14 cylces plus an initial round.
+
+The maximum throughput $T_{max}[Bits]$ depends on the maximum operation frequency $f_{max}$ and the keylength which
+influences the number of rounds $N_{rnd} \epsilon \lbrace 10,12,14 \rbrace $.
+\begin{equation}
+ T_{max}=\frac{ (1+N_{rnd}) \cdot 128 Bit}{f_{max}}
+\label{eqn:tmax}
+\end{equation}
+
+Note: Equation \ref{eqn:tmax} assumes that the roundkeys are already generated and does not include the constant of 4+1+4
+Avalon\rtm\ bus cylces for transmission of data, activation and result retrieval.
+
+
+\subsection{Exemplary FPGA implementations}
+
+The component has only be implemented and tested on an Altera\rtm\ CycloneII EP2C35
+FPGA. For this setup a Makefile is provided in \texttt{./sys/AlteraQuartus9.1}. All
+other values in the table are only results of synthesis\footnotemark[0] and are not
+verified on actual hardware.
+
+
+\footnotetext[0]{Synthesized with Altera\rtm\ QuartusII\rtm\ Web edition Version 9.1 or Xilinx\rtm\ ISE 9.1 Webpack}
+
+The design is kept mostly vendor independent in generic VHDL. For Altera\rtm\ chips the
+AES SubByte component is specially designed using M4K Blockrams as dual-port ROM. For
+non-Altera\rtm\ FPGAs a second VHDL architecture exists also trying to make use of
+ROM functions of the target chips however the success varies on RTL compiler
+capabilities.
+
+\begin{tabularx}{\textwidth}{|p{30mm}|X|p{20mm}|p{30mm}|p{18mm}|}
+ \hline
+ \bf{Configuration} & \bf{Target FPGA}\footnotemark[1] & \bf{LE / Slices} & \bf{HW RAM} & $\mathbf{f_{max}[Mhz]}$ \\ \hline
+ \multirow{4}{30mm}{256 Bit Key, encrypt + decrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 1609 & 18 RAMB16BWE & 91 \\ \cline{2-5}
+ & \mbox{Xilinx\rtm\ Virtex5} XC5VLX30-3FF324 & - / 297 & \mbox{18 18k-Blocks} \mbox{4 36k-Blocks} & 224 \\ \cline{2-5}
+ & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 1937 / - & \mbox{39912 Bits} in \mbox{22 M4K-Blocks} & 65 \\ \cline{2-5}
+ & \mbox{Altera\rtm\ StratixII} EP2S30F484C5 & 585 / - & \mbox{39912 Bits} in \mbox{22 M4K-Blocks} & 103 \\
+ \hline
+%%%%%%
+ \multirow{2}{30mm}{128 Bit Key, encrypt + decrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 1523 & 18 RAMB16BWE & 91 \\ \cline{2-5}
+ & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 1776 / - & \mbox{39912 Bits} in \mbox{22 M4K-Blocks} & 65 \\
+ \hline
+%%%%%%
+ \multirow{4}{30mm}{256 Bit Key, encrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 680 & 14 RAMB16BWE & 159 \\ \cline{2-5}
+ & \mbox{Xilinx\rtm\ Virtex5} XC5VLX30-3FF324 & - / 297 & \mbox{10 18k-Blocks} \mbox{4 36k-Blocks} & 268 \\ \cline{2-5}
+ & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 969 / - & \mbox{22528 Bits} in \mbox{14 M4K} & 97 \\ \cline{2-5}
+ & \mbox{Altera\rtm\ StratixII} EP2S30F484C5 & 524 / - & \mbox{22528 Bits} in \mbox{ 14 M4K} & 145 \\
+ \hline
+%%%%%%
+ \multirow{2}{30mm}{128 Bit Key, encrypt} & \mbox{Xilinx\rtm\ Spartan3A} XC3S1400A-5FG484 & - / 594 & 14 RAMB16BWE & 159 \\ \cline{2-5}
+ & \mbox{Altera\rtm\ CylconeII} EP2C35F484C8 & 797 / - & \mbox{22528 Bits} in \mbox{ 14 M4K} & 95 \\ \cline{2-5}
+ \hline
+
+\end{tabularx}
+\footnotetext[1]{This table is not meant to be a benchmark between FPGAs of different vendors, it is only a rough
+ estimation for the user of the core.
+ The FPGA families cannot be compared easily, see also \cite{Xilinx:wp284} and \cite{Altera:01007}for further details. }
+\label{tab:ressources}
+\captionof{table}{ressource usage on different targets and configuration}
+
+All of the above configurations in table \ref{tab:ressources} use hardware key
+expansion. Downloading of software generated roundkeys is not yet supported. The
+decryption and encryption datapaths share a common keyexpansion block, mulitplexing
+the address signals is one of the main reasons for regression of the maximum
+frequency $f_{max}$ of the configuration compared to encryption only versions.
+
+\section{Simulation and Software Driver}
+\label{sec:simdriv}
+\subsection{Testbench}
+\label{sec:testbench}
+In \texttt{./bench/VHDL/} a ``selfchecking testbench'' is provided which runs tests
+for a default \texttt{TESTKEYSIZE} is 256 Bit . For different key lengths the
+constant \texttt{TESTKEYSIZE} has to be changed appropriately. Expected results for
+all testcases and key lengths are included. The expected results were generated by
+AES Calculator applet, written by Lawrie Brown from ADFA, Canberra Australia \cite{LaBr05}. The
+testbench consists of a sequence of 5 test cases:
+\begin{enumerate}
+\item load key1, load data1, encrypt : (basic encryption test)
+\item key1, data1, decrypt: (basic decryption test)
+\item key1, data1, encrypt: (test if internal state was changed)
+\item key1, data2, encrypt: (encryption test with new data)
+\item key2, data2, encrypt: (encryption test with new key)
+\end{enumerate}
+
+\subsubsection{Simulation}
+\label{sec:simulation}
+The component library is ``\texttt{avs\_aes\_lib}''. All files are expected to be
+compiled into this library as all files depend at least on the package
+\texttt{avs\_aes\_lib.avs\_aes\_pkg}. \\
+A Makefile for Mentor Graphics\rtm\ Modelsim\rtm\ is given in \texttt{./sim/}. The
+default make target \texttt{simaes} will create the library
+``\texttt{avs\_aes\_lib}'' and a ``\texttt{work}'' library, compile all files and run
+a testbench. \\
+
+\subsection{Software Driver}
+\label{sec:software}
+This AES Core Avalon\rtm\ slave was also tested on a NiosII\rtm\ processor. To use
+it in software a simple driver is provided in \texttt{./sw/} among with an example
+program of the basic usage. Find more detailed description in the doxygen documentation in \texttt{./doc/sw/html}\\
+The driver consits of the two files \texttt{avs\_aes.c} and \texttt{avs\_aes.h}.
+\subsubsection{Configuration}
+To be adapted to different address mappings and key sizes two macros are use in \texttt{avs\_aes.h}:
+ \begin{tabularx}{\textwidth}{|p{25mm}|p{25mm} |X|}
+ \hline
+ \bf{define} & \bf{default} & \bf{Description}\\ \hline
+ \texttt{KEYWORDS} & \texttt{8} & Key size in 32 Bit words \\
+\hline
+ \texttt{AES\_BASEADDR} & \texttt{0x40000} & Base address at which the AES Core is mapped to the Avalon\rtm\ switchfabric \\
+\hline
+\end{tabularx}
+\label{tab:macros}
+\captionof{table}{user changeable macros in header}
+
+\subsubsection{Compilation}
+Yes indeed very difficult to compile two files and one header..... try this one:\\
+\texttt{GCCNIOS -I. -o test aes\_tester.c avs\_aes.c}
+
+Of course you need a cross compiler, or just use the Nios2 IDE.
+
+
+
+\section{The Inner Core}
+\label{sec:core}
+The algorithmic core is devided into two seperate datapaths one for encryption and a
+second for decryption operation. The two datapaths are independent, however they
+share the keyexpansion component which provides decrypt and encrypt keys (which are
+the same only in opposite order). Each datapath is controlled by its own \FSM\. If
+configured by the generic \texttt{DECRYPTION} \ref{gen:decryption} the decryption
+datapath is included and some multiplexers are generated for the shared signals,
+e.g. \texttt{result} or \texttt{roundkey\_index}.\\
+For reference the encryption data path of \texttt{aes\_core.vhd} is given in figure
+\ref{fig:aescore}. The decryption datapath is left for the reader or any other author
+of this document.
+\begin{figure}[!ht]
+ \centering
+ \includegraphics[width=0.9\textwidth]{CoreEncDP}
+ \caption{Encrypt datapath of the AES core as implemented in aes\_core.vhd}
+ \label{fig:aescore}
+\end{figure}
+
+
+\newpage
+\section{License and Liability}
+\label{sec:license}
+The ``AES 128/192/256 (ECB) Avalon\rtm-MM Slave'' component, all its subcomponents
+and documentation (like this document you are reading) are published under following
+license:\\
+
+Copyright (c) 2009, Thomas Ruschival - All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+\begin{itemize}
+\item Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+\item Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or other
+ materials provided with the distribution.
+\item Neither the name of the organization nor the names of its contributors may be
+ used to endorse or promote products derived from this software without specific
+ prior written permission.
+\end{itemize}
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. \\
+IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
+ OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE\\
+
+ Note: The term ``SOFTWARE'' in the above licence applies in this case not only to
+ software as executable code but also to documentation, hardware description or
+ compiled netlists for actual target hardware. As Chips generally don't just
+ reproduce ``the above copyright notice, this list of conditions and the following
+ disclaimer in the documentation and/or other materials provided with the
+ distribution'' the datasheet of the product must also contain it.\\
+
+ Altera, CycloneII, StratixII and Avalon are registered trademarks of the Altera
+ Corporation
+ 101 Innovation Drive, San Jose CA USA \\
+ Xilinx, Spartan3A and Virtex5 are registered trademarks of Xilinx Inc. 2100 Logic Drive, San Jose CA USA \\
+ Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics
+ Corporation 8005 SW Boeckman Road, Wilsonville OR USA \newpage
+
+\printacronym
+\printglossary
+
+\bibliography{cited}
+\revisionTable
+
+\end{document}
manual/src/avs_aes.tex
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: manual/src/avs_aes.acn
===================================================================
--- manual/src/avs_aes.acn (nonexistent)
+++ manual/src/avs_aes.acn (revision 11)
@@ -0,0 +1,30 @@
+\begin{theglossary}\glogroupA
+
+\gloitem {\glosslabel{acn:AES}{Advanced Encryption Standard\ (\noexpand \acronymfont {AES})}}NIST approved symmetric block cypher\relax
+\glodelim
+ \glsnumformat{3}\delimT \gloskip \glogroupE
+
+\gloitem {\glosslabel{acn:ECB}{Electronic Codebook\ (\noexpand \acronymfont {ECB})}}application of a cypher algorithm without further processing of the blocks\relax
+\glodelim
+ \glsnumformat{3}\delimT \gloskip \glogroupF
+
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Index: manual/src/cited.bib
===================================================================
--- manual/src/cited.bib (nonexistent)
+++ manual/src/cited.bib (revision 11)
@@ -0,0 +1,73 @@
+@misc{Altera:Avalon,
+ title = {Avalon Interface Specification},
+ organization = {Altera Corporation},
+ address = {101 Innovation Drive, San Jose, CA, US},
+ year = {2005},
+ key = {MNL-AVABUSREF-3.1},
+ type = {Specification},
+ url = {http://www.altera.com/literature/manual/mnl\_avalon\_spec.pdf}
+}
+
+@misc{LaBr05,
+ title = {AES Calculator},
+ author = {Lawrie Brown},
+ organization = {ADFA},
+ address = {Canberra, Australia},
+ year = {2005},
+ key = {AESCalc},
+ type = {Specification},
+ url = {http://www.unsw.adfa.edu.au/~lpb/src/AEScalc/index.html}
+}
+
+@misc{OC:WBspec,
+ title = {WISHBONE SoC Architecture Specification, Revision B.3},
+ author = {Richard Herveille},
+ organization = {Opencores Organization},
+ address = {},
+ edition = {},
+ month = {Sept.},
+ year = {2002},
+ url = {http://www.opencores.org/downloads/wbspec_b3.pdf},
+}
+
+
+@misc{NIST:Fips197,
+ title = {FIPS-197 Announcing the Advanced Encryption Standard (AES) },
+ organization = {National Institute of Standards and Technology (NIST)},
+ address = {100 Bureau Drive, Stop 1070, Gaithersburg, MD, US},
+ edition = {Federal Information Processing Standards Publication 197},
+ month = {Nov.},
+ year = {2001},
+ url = {http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf},
+}
+
+
+@misc{Xilinx:wp284,
+ title = {Advantages of the Virtex-5 FPGA 6-Input LUT Architecture},
+ author = {Andrew Percey},
+ organization = {Xilinx Inc.},
+ address = { 2100 Logic Drive, San Jose CA USA },
+ edition = {Whitpaper 284},
+ month = {Dec.},
+ year = {2007},
+ url = {http://www.xilinx.com/support/documentation/white_papers/wp284.pdf},
+}
+
+
+@misc{Altera:01007,
+ title= {Stratix III FPGAs vs. Xilinx Virtex-5 Devices: Architecture and Performance Comparison},
+ organization = {Altera Corporation},
+ address = { 101 Innovation Drive, San Jose CA USA},
+ edition = {Whitepaper 01007-v2.1},
+ month = {Oct.},
+ year = {2007},
+ url ={http://www.altera.com/literature/wp/wp-01007.pdf}
+}
+
+@misc{Wiki:AvWb,
+ title = {Wishbone - Computer Bus},
+ organization = {wikipedia.org},
+ lastchecked = {2009-04-20},
+ url = {http://en.wikipedia.org/wiki/Wishbone\_computer\_bus)#Comparisons},
+}
+
manual/src/cited.bib
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Index: manual/src/avs_aes.blg
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Index: manual/src/avs_aes.acr
===================================================================
--- manual/src/avs_aes.acr (nonexistent)
+++ manual/src/avs_aes.acr (revision 11)
@@ -0,0 +1,8 @@
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Index: manual/src/figs/logo.jpg
===================================================================
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Index: manual/src/figs/logo.jpg
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Index: manual/src/figs/CoreEncDP.svg
===================================================================
--- manual/src/figs/CoreEncDP.svg (nonexistent)
+++ manual/src/figs/CoreEncDP.svg (revision 11)
@@ -0,0 +1,1147 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ image/svg+xml
+
+
+
+
+
+ keyexpansionV2 keyword keywordaddr w_ena_keyword key_stable AES_FSM_ENCRYPT key_ready roundkey_idx
+ ena_encrypt
+
+ finished
+ sbox(0) (Highword) sbox(0) (LowWord) sbox(3) (Highword) sbox(3) (LowWord)
+ [31:24]
+
+ [23:16]
+
+ [15:8]
+
+ [7:0]
+ ... [31:24] [23:16]
+ [15:8]
+ [7:0]
+ [31:24] [23:16] [15:8] [7:0]
+
+ [31:24]
+
+ [23:16]
+
+ [15:8]
+
+ [7:0]
+ AddKey
+
+ STATE(ROUND)
+
+ STATE(ROUND-1) COL(0) COL(3) ShiftRow mixcol(0) mixcol(3) ... COL(0) COL(3) data_in AddKeyMux result
+ registered component
+
+ combinatorial component
+
+ signal
+
+ 32-Bit column
+
+ 128-Bit AES 'state'
+
+
+
Index: manual/src/figs/logo.eps
===================================================================
--- manual/src/figs/logo.eps (nonexistent)
+++ manual/src/figs/logo.eps (revision 11)
@@ -0,0 +1,509 @@
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manual/src/sfmath.sty
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: manual/src/avs_aes.glo
===================================================================
--- manual/src/avs_aes.glo (nonexistent)
+++ manual/src/avs_aes.glo (revision 11)
@@ -0,0 +1,6 @@
+\glossaryentry{Byte@{\glosslabel{glo:Byte}{Byte}}String of Bits - nowadays mostly a string of 8 Bits, also called oktett\relax|glsnumformat}{1}
+\glossaryentry{Bit@{\glosslabel{glo:Bit}{Bit}}Binary Digit, atomary information unit\relax|glsnumformat}{1}
+\glossaryentry{Switch fabric@{\glosslabel{glo:Switch fabric}{switch fabric}}Interconnect between IP-Cores providing arbiration and glue logic. Altera\rtm \ Avalon\rtm \ term\relax|glsnumformat}{1}
+\glossaryentry{Master@{\glosslabel{glo:Master}{Master}}Entity initiating and controlling communication.\relax|glsnumformat}{1}
+\glossaryentry{Slave@{\glosslabel{glo:Slave}{Slave}}Entity responding to communication requests by a Master.\relax|glsnumformat}{1}
+\glossaryentry{memory mapped@{\glosslabel{glo:memory mapped}{memory mapped}}Method of addressing peripheral components like Avalon Slaves via the same address bus as main memory\relax|glsnumformat}{1}
Index: manual/src/glossary.tex
===================================================================
--- manual/src/glossary.tex (nonexistent)
+++ manual/src/glossary.tex (revision 11)
@@ -0,0 +1,29 @@
+\glossary{name={Byte},
+ description={String of Bits - nowadays mostly a string of 8 Bits, also called oktett},
+ sort={Byte}
+}
+\glossary{name={Bit},
+ description={Binary Digit, atomary information unit},
+ sort={Bit}
+}
+\glossary{name={switch fabric},
+ description={Interconnect between IP-Cores providing arbiration and glue logic. Altera\rtm\ Avalon\rtm\ term},
+ sort={Switch fabric}
+}
+
+\glossary{name={Master},
+ description={Entity initiating and controlling communication.},
+ sort={Master}
+}
+
+\glossary{name={Slave},
+ description={Entity responding to communication requests by a Master.},
+ sort={Slave}
+}
+
+\glossary{name={memory mapped},
+ description={Method of addressing peripheral components like Avalon Slaves via the same address bus as main memory},
+ sort={memory mapped}
+}
+
+
\ No newline at end of file
manual/src/glossary.tex
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: manual/src/ruschidoc.cls
===================================================================
--- manual/src/ruschidoc.cls (nonexistent)
+++ manual/src/ruschidoc.cls (revision 11)
@@ -0,0 +1,300 @@
+\NeedsTeXFormat{LaTeX2e}
+\ProvidesClass{ruschidoc}
+\LoadClass[11pt,a4paper,twoside]{article}
+\RequirePackage[intlimits,sumlimits]{amsmath}
+\RequirePackage{amssymb}
+\RequirePackage{amsfonts}
+\RequirePackage{fancyhdr}
+\RequirePackage[T1]{fontenc}
+\RequirePackage[latin1]{inputenc}
+\RequirePackage{amsmath}
+\RequirePackage{helvet}
+\RequirePackage[amssymb]{SIunits}
+\RequirePackage[helvet]{sfmath}
+\RequirePackage{lastpage}
+\RequirePackage{tabularx}
+\RequirePackage{multirow}
+\RequirePackage{listings}
+\RequirePackage{textcomp}
+
+%% Some packages need special options for PDFtex
+\RequirePackage{ifpdf}
+\ifpdf
+ \RequirePackage[pdftex]{color}
+ \RequirePackage[pdftex]{graphics}
+ \DeclareGraphicsExtensions{.pdf, .png, .jpg}
+\else
+ \RequirePackage{color}
+ \RequirePackage{graphics}
+ \DeclareGraphicsExtensions{.eps, .ps}
+\fi
+\graphicspath{{figs/}}
+\RequirePackage{graphicx}
+\RequirePackage{subfigure}
+\RequirePackage{psfrag}
+\RequirePackage{colortbl}
+
+% ************************ Page layout ************************
+\topmargin -20mm
+\headheight 30mm
+\headsep 6mm
+\footskip 11mm
+\oddsidemargin 2mm
+\evensidemargin 2mm
+\marginparsep 145mm
+\marginparwidth 8mm
+\textwidth 162mm
+\textheight 225mm
+\parindent 0mm
+\parskip 3mm
+
+%Floats (tables, figures)
+% http://www.eng.cam.ac.uk/help/tpl/textprocessing/squeeze.html
+\floatsep 10mm
+\intextsep 2ex
+\textfloatsep 10pt
+\abovecaptionskip 5pt
+\belowcaptionskip 5pt
+% Section and subsection are de-idented (text body is idented)
+\def\@secindent{8mm}
+% how wide is the header
+\def\@htwidth{172mm}
+
+%colors
+\definecolor{lightgrey}{rgb}{0.95,0.95,0.95}
+
+%% Change the font
+\renewcommand{\familydefault}{\sfdefault}
+%% Make Registered Trademark symbol raised
+\newcommand{\tm}{\textsuperscript{\texttrademark}}
+\newcommand{\rtm}{\textsuperscript{\textregistered}}
+\renewcommand{\copyright}{\textcopyright}
+
+
+\setcounter{secnumdepth}{4}
+\setcounter{tocdepth}{3}
+\newlength\captionwidth
+\setlength\captionwidth{13cm}
+
+\renewcommand{\paragraph}[1]{\newpar{#1}\ \vspace{0.3cm}\\}
+
+\renewcommand{\section}{\@startsection
+{section}% % the name
+{1}% % the level
+{-\@secindent}% % the indent
+{-18pt}%
+{6pt}% % the after skip
+{\Large\bf}} % the style
+
+\renewcommand{\subsection}{\@startsection
+{subsection}% % the name
+{1}% % the level
+{-\@secindent}% % the indent
+{-6pt}%
+{6pt}% % the after skip
+{\large\bf}} % the style
+
+\renewcommand{\subsubsection}{\@startsection
+{subsubsection}% % the name
+{1}% % the level
+{-\@secindent}% % the indent
+{-6pt}%
+{6pt}% % the after skip
+{\bf}} % the style
+
+
+
+
+% ************************ Date format ************************
+\def\shorttoday{\ifcase\month\or
+ Jan\or Feb\or Mar\or Apr\or May\or Jun\or Jul\or Aug\or
+ Sep\or Oct\or Nov\or Dec\fi~\number\day, \number\year}
+
+\def\shorttoday{\number\day-\ifcase\month\or
+ Jan\or Feb\or Mar\or Apr\or May\or Jun\or Jul\or Aug\or
+ Sep\or Oct\or Nov\or Dec\fi-\number\year}
+
+\newcommand{\paddedday}{\ifnum\number\day<10 0\number\day\else \number\day\fi}
+\newcommand{\paddedmonth}{\ifnum\number\month<10 0\number\month\else \number\month\fi}
+
+\def\shorttoday{\number\year/\paddedmonth/\paddedday}
+
+
+% ************************ Document Variables ************************
+% main author
+\newcommand*{\authorName}[1]{\def\@authorName{#1}}
+\authorName{}
+% Additional Authors
+\newcommand*{\authorAddress}[1]{\def\@authorAddress{#1}}
+\authorAddress{}
+\newcommand*{\authorURL}[1]{\def\@authorURL{#1}}
+\authorURL{}
+\newcommand*{\authorEmail}[1]{\def\@authorEmail{#1}}
+\authorEmail{}
+% When was the document written/submitted (not compiled)
+\newcommand*{\docDate}[1]{\def\@docDate{#1}}
+\docDate{}
+% unique identifier
+\newcommand*{\docID}[1]{\def\@docID{#1}}
+\docID{}
+% type of document
+\newcommand*{\docType}[1]{\def\@docType{#1}}
+\docType{Technical Note}
+% Title of the document
+\newcommand*{\docTitle}[1]{\def\@docTitle{#1}}
+\docTitle{}
+% Title of the document
+\newcommand*{\docSubtitle}[1]{\def\@docSubtitle{#1}}
+\docSubtitle{}
+% current revision
+\newcommand*{\docRevision}[1]{\def\@docRevision{#1}}
+\docRevision{0.1}
+% Status Draft/revision/ final
+\newcommand*{\docStatus}[1]{\def\@docStatus{#1}}
+\docStatus{Draft}
+% Who will receive the doc -- differnece to customers???
+\newcommand*{\recipientList}[1]{\def\@recipientList{#1}}
+% list of keywords
+\newcommand*{\keywords}[1]{\def\@keywords{#1}}
+\keywords{}
+% list of revisions
+\newcommand*{\revisionList}[1]{\def\@revisionList{#1}}
+\revisionList{}
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\newenvironment{CompactList}
+{\begin{list}{}{
+ \setlength{\leftmargin}{0.5cm}
+ \setlength{\itemsep}{0pt}
+ \setlength{\parsep}{0pt}
+ \setlength{\topsep}{0pt}
+ \renewcommand{\makelabel}{\hfill}}}
+{\end{list}}
+
+\newenvironment{CompactItemize}
+{
+ \begin{itemize}
+ \setlength{\itemsep}{-3pt}
+ \setlength{\parsep}{0pt}
+ \setlength{\topsep}{0pt}
+ \setlength{\partopsep}{0pt}
+}
+{\end{itemize}}
+
+\newcommand{\entrylabel}[1]{
+ {\parbox[b]{\labelwidth}{\makebox[0pt][l]{\textbf{#1}}\vspace{1.5\baselineskip}}}}
+
+\newcommand{\paragraphbreak}[1]{\paragraph{#1}\ \vspace{0.3cm}\\}
+\newcommand{\subparagraphbreak}[1]{\subparagraph{#1}\ \vspace{0.3cm}\\}
+
+\newenvironment{Desc}
+{\begin{list}{}
+ {
+ \settowidth{\labelwidth}{40pt}
+ \setlength{\leftmargin}{\labelwidth}
+ \setlength{\parsep}{0pt}
+ \setlength{\itemsep}{-4pt}
+ \renewcommand{\makelabel}{\entrylabel}
+ }
+}
+{\end{list}}
+ \lstset{
+ breaklines,
+ tabsize=5,
+ columns=flexible,
+ extendedchars,
+ xleftmargin=2em,
+ basicstyle=\scriptsize\sffamily,
+ showstringspaces=false,
+ emptylines=*1,
+ frame=single,
+ literate={[]}{[{$\;$}]}3,
+ captionpos=b
+ backgroundcolor=\color{lightgrey}}
+%\lstlistingname="Listing"
+
+
+% ************************ Header/footer ************************
+\pagestyle{fancy}
+\renewcommand{\headrulewidth}{0.0pt}
+\renewcommand{\footrulewidth}{0.0pt}
+
+\fancyhead[O,E]{
+ \leftskip-\@secindent
+ \begin{tabularx}{185mm}{p{98mm} p{45mm} p{25mm}}
+ \hskip2mm \sc{ \@docTitle } & & \hskip2mm \thepage / \pageref{LastPage}
+ \end{tabularx}
+ \includegraphics[width=\@htwidth]{fancy_headsep_r}
+}
+
+
+
+ \fancyfoot{}
+ \fancyfoot[ER,OL]{
+ \tiny{All rights reserved - \copyright \number\year \ \@authorName}
+ }
+ \fancyfoot[EL,OR]{
+ \tiny{\@docID \ (v. \@docRevision) - \@\shorttoday}
+ }
+
+
+\fancypagestyle{plain}{
+ \renewcommand{\headrulewidth}{0.0pt}
+ \renewcommand{\footrulewidth}{0.0pt}
+ \fancyhead{}
+ \fancyfoot[EL,OL]{}
+ \renewcommand{\headrulewidth}{0pt}
+ }
+
+
+
+
+\renewenvironment{abstract}{
+ \small
+ \begin{center}
+ {\bf\large \abstractname
+ \vspace{-.5em}\vspace{\z@}}
+ \end{center}
+}
+
+% ************************ Revision table *********************
+\newcommand{ \revisionTable } {
+ \section*{Change History}
+ \begin{tabularx}{\textwidth} {| p{11mm} | p{14mm} | X | p{23mm} | p{32mm} |}
+ \hline
+ Rev. & Chapter & Description & Date & Reviewer \\
+ \hline
+ \@revisionList
+ \hline
+ \end{tabularx}
+}
+
+% ************************ Cover table ************************
+\def\@maketitle{
+ \vglue80mm
+ %% Title
+ \begin{minipage}{0.65\linewidth}
+ \begin{flushleft}
+ \Huge{\textbf{\sc{\@docTitle}}}
+ \end{flushleft}
+ \end{minipage}
+%% fancy line
+ \vskip4pt
+ \leftskip-17mm
+ \includegraphics[width=1.1\textwidth]{fancy_headsep_r}
+ \vspace{3pt}
+%% addess
+ \vglue55mm
+ \begin{tabularx}{\textwidth}{p{55mm} X p{65mm}}
+ \begin{minipage}{60mm}
+ \includegraphics[width=20mm]{logo}
+ \end{minipage} & &
+ \begin{minipage}{62mm}
+ \Large{\@authorName} \\
+ \large{\@authorAddress}
+ \end{minipage} \\
+ & & \\
+ \large{\@authorURL} & & \large{\@authorEmail} \\
+ \end{tabularx}
+ \vspace{2ex}
+} %% End of maketitle
manual/src/ruschidoc.cls
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: manual/src/avs_aes.gls
===================================================================
--- manual/src/avs_aes.gls (nonexistent)
+++ manual/src/avs_aes.gls (revision 11)
@@ -0,0 +1,26 @@
+\begin{theglossary}\glogroupB
+
+\gloitem {\glosslabel{glo:Bit}{Bit}}Binary Digit, atomary information unit\relax
+\glodelim
+ \glsnumformat{1}\delimT
+
+\gloitem {\glosslabel{glo:Byte}{Byte}}String of Bits - nowadays mostly a string of 8 Bits, also called oktett\relax
+\glodelim
+ \glsnumformat{1}\delimT \gloskip \glogroupM
+
+\gloitem {\glosslabel{glo:Master}{Master}}Entity initiating and controlling communication.\relax
+\glodelim
+ \glsnumformat{1}\delimT
+
+\gloitem {\glosslabel{glo:memory mapped}{memory mapped}}Method of addressing peripheral components like Avalon Slaves via the same address bus as main memory\relax
+\glodelim
+ \glsnumformat{1}\delimT \gloskip \glogroupS
+
+\gloitem {\glosslabel{glo:Slave}{Slave}}Entity responding to communication requests by a Master.\relax
+\glodelim
+ \glsnumformat{1}\delimT
+
+\gloitem {\glosslabel{glo:Switch fabric}{switch fabric}}Interconnect between IP-Cores providing arbiration and glue logic. Altera\rtm \ Avalon\rtm \ term\relax
+\glodelim
+ \glsnumformat{1}\delimT
+\end{theglossary}
Index: manual/src/avs_aes.toc
===================================================================
--- manual/src/avs_aes.toc (nonexistent)
+++ manual/src/avs_aes.toc (revision 11)
@@ -0,0 +1,18 @@
+\contentsline {section}{\numberline {1}Introduction}{3}{section.1}
+\contentsline {section}{\numberline {2}Interface}{3}{section.2}
+\contentsline {subsection}{\numberline {2.1}Configuration Generics}{3}{subsection.2.1}
+\contentsline {subsection}{\numberline {2.2}Signals}{4}{subsection.2.2}
+\contentsline {section}{\numberline {3}Memory Map}{4}{section.3}
+\contentsline {subsection}{\numberline {3.1}Control Register}{5}{subsection.3.1}
+\contentsline {section}{\numberline {4}Protocol Sequence}{6}{section.4}
+\contentsline {subsection}{\numberline {4.1}Interrupt Behaviour}{7}{subsection.4.1}
+\contentsline {section}{\numberline {5}Ressource Usage and Throughput}{7}{section.5}
+\contentsline {subsection}{\numberline {5.1}Exemplary FPGA implementations}{8}{subsection.5.1}
+\contentsline {section}{\numberline {6}Simulation and Software Driver}{9}{section.6}
+\contentsline {subsection}{\numberline {6.1}Testbench}{9}{subsection.6.1}
+\contentsline {subsubsection}{\numberline {6.1.1}Simulation}{10}{subsubsection.6.1.1}
+\contentsline {subsection}{\numberline {6.2}Software Driver}{10}{subsection.6.2}
+\contentsline {subsubsection}{\numberline {6.2.1}Configuration}{10}{subsubsection.6.2.1}
+\contentsline {subsubsection}{\numberline {6.2.2}Compilation}{10}{subsubsection.6.2.2}
+\contentsline {section}{\numberline {7}The Inner Core}{10}{section.7}
+\contentsline {section}{\numberline {8}License and Liability}{13}{section.8}
Index: manual/src/acronym.tex
===================================================================
--- manual/src/acronym.tex (nonexistent)
+++ manual/src/acronym.tex (revision 11)
@@ -0,0 +1,15 @@
+\newacronym{LSB}{Least Significant Bit}{description=least value bit in a vector}
+\newacronym{MSB}{Most Significant Bit}{description=highest value bit in a vector}
+\newacronym{SoC}{System on Chip}{description=System of seperate functional interacting together implemented on a single chip }
+\newacronym{AES}{Advanced Encryption Standard}{description=NIST approved symmetric
+block cypher}
+\newacronym{ECB}{Electronic Codebook}{description=application of a cypher algorithm
+without further processing of the blocks}
+\newacronym{FSM}{Finite State Machine}{description=Behavioural Model with finite
+number of states and transitions}
+\newacronym{NIST}{National Institute of Standards and Technology}{description=US
+standardisation office}
+
+
+
+
manual/src/acronym.tex
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
+
1.6.1
+
+
Index: sw/html/tab_l.gif
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: sw/html/tab_l.gif
===================================================================
--- sw/html/tab_l.gif (nonexistent)
+++ sw/html/tab_l.gif (revision 11)
