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URL https://opencores.org/ocsvn/avs_aes/avs_aes/trunk

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    /avs_aes/trunk/hdl
    from Rev 10 to Rev 11
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Rev 10 → Rev 11

/aes_ecb/sbox.hex File deleted
/aes_ecb/aes_core.vhd File deleted
/aes_ecb/shiftrow_inv.vhd File deleted
/aes_ecb/aes_fsm_encrypt.vhd File deleted
/aes_ecb/avs_aes.vhd File deleted
/aes_ecb/aes_ecb_pkg.vhd File deleted
/aes_ecb/keyexpansionV2.vhd File deleted
/aes_ecb/sboxM4k.vhd File deleted
/aes_ecb/sbox_arch1.vhd File deleted
/aes_ecb/sbox_inv.hex File deleted
/aes_ecb/mux2.vhd File deleted
/aes_ecb/mixcol_fwd.vhd File deleted
/aes_ecb/mixcol.vhd File deleted
/aes_ecb/mux3.vhd File deleted
/aes_ecb/memory_word.vhd File deleted
/aes_ecb/keygenerate.vhd File deleted
/aes_ecb/shiftrow_fwd.vhd File deleted
/aes_ecb/shiftrow.vhd File deleted
/aes_ecb/avs_aes_tb.vhd File deleted
/aes_ecb/aes_fsm_decrypt.vhd File deleted
/aes_ecb/mixcol_inv.vhd File deleted
/aes_ecb/addroundkey.vhd File deleted
/aes_ecb/sbox.vhd File deleted
/VHDL/shiftrow_fwd.vhd
0,0 → 1,117
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description: (Encryption implementation of Shiftrow)
-- Shift Row rotates the Rows of the AES Block
-- This module takes the whole Rijdael state as input, extracts the rows,
-- shifts them and rebuilts the state.
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
 
architecture fwd of Shiftrow is
-- type of converting the columns into rows
subtype ROW is BYTEARRAY(0 to 3);
-- Row signal for easier handling of the shift operations
signal row1_in : Row; -- 1st row
signal row2_in : Row; -- 2nd row
signal row3_in : Row; -- 3rd row
signal row4_in : Row; -- 4th row
-- single rows after shift operation
-- row1 of the shifted state = row1 of unshifted state
signal row2_out : Row; -- 2nd row
signal row3_out : Row; -- 3rd row
signal row4_out : Row; -- 4th row
begin -- architecture arch1
-- purpose: build the temorary internal signals for easier handling
-- type : combinational
-- inputs : state_in
-- outputs: state_out
build_in : process (state_in) is
begin -- process build_in
-- state is a DWORD array with 16, 24 or 32 Byte in 4,6 or 8 columns
-- thus we loop through the columns and slice the column in its bytes
for col_cnt in 0 to (state_in'high) loop
row1_in(col_cnt) <= state_in(col_cnt)(31 downto 24);
row2_in(col_cnt) <= state_in(col_cnt)(23 downto 16);
row3_in(col_cnt) <= state_in(col_cnt)(15 downto 8);
row4_in(col_cnt) <= state_in(col_cnt)(7 downto 0);
end loop; -- col_cnt
end process build_in;
 
 
-- purpose: shift rows of Rindael state by 'shift_delta'
-- type : combinational
-- inputs : row(1 to 4)_in
-- outputs: row(1 to 4)_out
shifter : process (row2_in, row3_in, row4_in) is
begin
-- 1st row was never shifted so no reverse action needed
-- rotate 2nd row left
row2_out <= row2_in(row2_in'left+1 to row2_in'right) & row2_in(row2_in'left);
--rotate by 2 left
row3_out <= row3_in(row3_in'left+2 to row3_in'right) & row3_in(row3_in'left to row3_in'left+1);
-- rotate by 3 left
row4_out <= row4_in(row4_in'left+3 to row4_in'right) & row4_in(row4_in'left to row4_in'left+2);
end process shifter;
 
 
-- purpose: rebuilt the state form the shifted rows
-- type : combinational
-- inputs : row1_out, row2_out, row3_out, row4_out
-- outputs: state_out
rebuilt_state : process (row1_in, row2_out, row3_out, row4_out) is
begin -- process rebuilt_state
for col_cnt in 0 to state_out'high loop -- works because 15/4=3
state_out(col_cnt)(31 downto 24) <= row1_in(col_cnt);
state_out(col_cnt)(23 downto 16) <= row2_out(col_cnt);
state_out(col_cnt)(15 downto 8) <= row3_out(col_cnt);
state_out(col_cnt)(7 downto 0) <= row4_out(col_cnt);
end loop; -- col_cnt
end process rebuilt_state;
 
end architecture fwd;
/VHDL/shiftrow.vhd
0,0 → 1,60
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description: (THIS IS ONLY THE ENTITY FOR THE SHIFTROW COMPONENTS)
-- Shift Row rotates the Rows of the AES Block
-- This module takes the whole Rijdael state as input, extracts the rows,
-- shifts them and rebuilts the state.
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity Shiftrow is
port (
state_in : in STATE; -- Raw input data to be shifted
state_out : out STATE -- shifted result
);
end entity Shiftrow;
 
/VHDL/aes_fsm_decrypt.vhd
0,0 → 1,172
-------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Statemachine controlling the decryption datapath within aes_core.vhd does no
-- dataprocessing itself but only set enables and multiplexer selector ports
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Thomas Ruschival
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity aes_fsm_decrypt is
generic (
NO_ROUNDS : NATURAL := 10); -- number of rounds
port (
clk : in STD_LOGIC; -- System clock
data_stable : in STD_LOGIC; -- flag valid data/activate the process
-- interface for keygenerator
key_ready : in STD_LOGIC; -- flag valid roundkeys
round_index_out : out NIBBLE; -- address for roundkeys memory
-- Result of Process
finished : out STD_LOGIC; -- flag valid result
-- Control ports for the Core
round_type_sel : out STD_LOGIC_VECTOR(1 downto 0) -- selector for mux around mixcols
);
end entity aes_fsm_decrypt;
 
--
architecture Arch1 of AES_FSM_DECRYPT is
-- types for the FSM
type AESstates is (WAIT_KEY, WAIT_DATA, INITIAL_ROUND,DO_ROUND, FINAL_ROUND);
 
-- FSM signals
signal FSM : AESstates; -- current state
signal next_FSM : AESstates; -- combinational next state
 
-- Round Counter & address for keygenerate
signal round_index : NIBBLE; -- currently processed round
signal next_round_index : NIBBLE; -- next round, index for keygenerate
begin
---------------------------------------------------------------------------
-- assign internal values to interface ports
---------------------------------------------------------------------------
round_index_out <= next_round_index; -- roundkey address
 
-- purpose: combinational generation of next state for encrytion FSM
-- type : sequential
-- inputs : FSM, data_stable, key_ready, round_index
-- outputs: next_FSM
gen_next_fsm : process (FSM, data_stable, key_ready, round_index) is
begin -- process gen_next_fsm
case FSM is
when WAIT_KEY =>
if key_ready = '1' then
next_FSM <= WAIT_DATA;
else
next_FSM <= WAIT_KEY;
end if;
when WAIT_DATA =>
if data_stable = '1' then
next_FSM <= INITIAL_ROUND;
else
next_FSM <= WAIT_DATA;
end if;
when INITIAL_ROUND =>
next_FSM <= DO_ROUND;
when DO_ROUND =>
if round_index = X"1" then
next_FSM <= FINAL_ROUND;
else
next_FSM <= DO_ROUND;
end if;
when FINAL_ROUND =>
next_FSM <= WAIT_DATA;
-- pragma synthesis_off
when others =>
report "FSM in strange state - aborting" severity failure;
-- pragma synthesis_on
end case;
 
-- Default behaviour in case key is invalid
if key_ready = '0' then
next_FSM <= WAIT_KEY;
end if;
end process gen_next_fsm;
 
 
-- purpose: assign outputs for decryption
-- type : combinational
-- inputs : FSM
com_output_assign : process (FSM, round_index) is
begin -- process com_output_assign
-- save defaults for decrypt_FSM
round_type_sel <= "00"; -- signal initial_round
next_round_index <= round_index;
finished <= '0';
 
case FSM is
when WAIT_KEY =>
-- start at last index
next_round_index <= STD_LOGIC_VECTOR(to_unsigned(NO_ROUNDS,4));
when WAIT_DATA =>
next_round_index <= STD_LOGIC_VECTOR(to_unsigned(NO_ROUNDS,4));
when INITIAL_ROUND =>
round_type_sel <= "00"; -- use Data_in for Addkey and pass
-- result directly to Inverse Shiftrow
next_round_index <= STD_LOGIC_VECTOR(UNSIGNED(round_index)-1);
when DO_ROUND =>
round_type_sel <= "01";
next_round_index <= STD_LOGIC_VECTOR(UNSIGNED(round_index)-1);
when FINAL_ROUND =>
round_type_sel <= "01";
finished <= '1';
when others =>
null;
end case;
end process com_output_assign;
 
-- purpose: clocked FSM for decryption
-- type : sequential
-- inputs : clk, res_n
clocked_FSM : process (clk) is
begin -- process clocked_FSM
if rising_edge(clk) then -- rising clock edge
FSM <= next_FSM;
round_index <= next_round_index;
end if;
end process clocked_FSM;
 
end architecture Arch1;
/VHDL/mixcol_inv.vhd
0,0 → 1,162
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Mix the columns of the AES Block (decryption version)
-- Invert what was computed in mixcol_fwd.vhd
-- For decrytion the inverse matrix is needed:
--
-- | E B D 9 | a(n,0)
-- | 9 E B D | x a(n,1)
-- | D 9 E B | a(n,2)
-- | B D 9 E | a(n,3)
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
 
architecture inv of mixcol
is
signal byte0 : BYTE;
signal byte1 : BYTE;
signal byte2 : BYTE;
signal byte3 : BYTE;
begin -- architecture ARCH1
 
-- Easier handling of the single cells of the column
byte0 <= col_in(31 downto 24);
byte1 <= col_in(23 downto 16);
byte2 <= col_in(15 downto 8);
byte3 <= col_in(7 downto 0);
 
-- purpose: multiplies the column of the input block with the matrix
-- type : combinational
-- inputs : direction,byte0,byte1,byte2,byte3
-- outputs: col_out
matrix_mult : process ( byte0, byte1, byte2, byte3) is
-- temporary results for the row-col multiplication have to be 9 Bits
-- long because the input is shifted left
variable tmp_res0 : STD_LOGIC_VECTOR(10 downto 0); -- result of row1*col
variable tmp_res1 : STD_LOGIC_VECTOR(10 downto 0); -- result of row2*col
variable tmp_res2 : STD_LOGIC_VECTOR(10 downto 0); -- result of row3*col
variable tmp_res3 : STD_LOGIC_VECTOR(10 downto 0); -- result of row4*col
begin -- process matrix_mult
-- Multiply by 1st row of the inverse matrix ( E B D 9 )
tmp_res0 := byte0 & "000" xor '0' & byte0 & "00" xor "00" & byte0 & '0' xor -- byte0*8+byte0*4+byte0*2 +
byte1 & "000" xor "00" & byte1 & '0' xor "000" & byte1 xor -- byte1*8 + byte1*2 + byte1
byte2 & "000" xor "0" & byte2 & "00" xor "000" & byte2 xor -- byte2*8 + byte2*4 + byte2
byte3 & "000" xor "000" & byte3; -- byte3*8 + byte3*1
 
-- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
if tmp_res0(10) = '1' then
tmp_res0 := tmp_res0 xor "10001101100";
end if;
if tmp_res0(9) = '1' then
tmp_res0 := tmp_res0 xor "01000110110";
end if;
if tmp_res0(8) = '1' then
tmp_res0 := tmp_res0 xor "00100011011";
end if;
 
-- Multiply by 2nd row of the inverse matrix ( 9 E B D )
tmp_res1 := byte0 & "000" xor "000" & byte0 xor
byte1 & "000" xor "0" & byte1 & "00" xor "00" & byte1 & '0' xor
byte2 & "000" xor "00" & byte2 & '0' xor "000" & byte2 xor
byte3 & "000" xor '0' & byte3 & "00" xor "000" & byte3;
 
-- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
if tmp_res1(10) = '1' then
tmp_res1 := tmp_res1 xor "10001101100";
end if;
if tmp_res1(9) = '1' then
tmp_res1 := tmp_res1 xor "01000110110";
end if;
if tmp_res1(8) = '1' then
tmp_res1 := tmp_res1 xor "00100011011";
end if;
 
-- Multiply by 3rd row of the inverse matrix (D 9 E B)
tmp_res2 := byte0 & "000" xor "0" & byte0 & "00" xor "000" & byte0 xor -- byte0*8 + byte0*4 + byte0
byte1 & "000" xor "000" & byte1 xor -- byte1*8 + byte1
byte2 & "000" xor "0" & byte2 & "00" xor "00" & byte2 &'0' xor -- byte2*8 + byte2*4 + byte2*2
byte3 & "000" xor "00" & byte3 & '0' xor "000" & byte3; -- byte3*8 + byte3*2 + byte3
-- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
if tmp_res2(10) = '1' then
tmp_res2 := tmp_res2 xor "10001101100";
end if;
if tmp_res2(9) = '1' then
tmp_res2 := tmp_res2 xor "01000110110";
end if;
if tmp_res2(8) = '1' then
tmp_res2 := tmp_res2 xor "00100011011";
end if;
 
-- Multiply by 4th row of the inverse matrix (B D 9 E)
tmp_res3 := byte0 & "000" xor "00" & byte0 & '0' xor "000" & byte0 xor -- byte0*8 + byte0*2 + byte0*1
byte1 & "000" xor '0' & byte1 &"00" xor "000" & byte1 xor -- byte1*8 + byte1*4 + byte1
byte2 & "000" xor "000" & byte2 xor -- byte2*8 + byte2
byte3 & "000" xor "0" & byte3 & "00" xor "00" & byte3 &'0'; -- byte3*8 + byte3*4 + byte3*2
 
-- check if bits>7 = 1 and XOR with magic numbers to make it 8 BIT
if tmp_res3(10) = '1' then
tmp_res3 := tmp_res3 xor "10001101100";
end if;
if tmp_res3(9) = '1' then
tmp_res3 := tmp_res3 xor "01000110110";
end if;
if tmp_res3(8) = '1' then
tmp_res3 := tmp_res3 xor "00100011011";
end if;
 
-- build output signal (BYTE_RANGE =7 downto 0 see util_pkg.vhd)
col_out(31 downto 24) <= tmp_res0(BYTE_RANGE);
col_out(23 downto 16) <= tmp_res1(BYTE_RANGE);
col_out(15 downto 8) <= tmp_res2(BYTE_RANGE);
col_out(7 downto 0) <= tmp_res3(BYTE_RANGE);
end process matrix_mult;
 
end architecture inv;
 
/VHDL/addroundkey.vhd
0,0 → 1,75
-------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- AddRoundKey module for AES algorithm, basically a simple XOR for states and
-- keyblocks.... just a simple XOR wrapped into a component for nicer usage.
--
--
-------------------------------------------------------------------------------
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Thomas Ruschival
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity AddRoundKey is
port (
roundkey : in KEYBLOCK; -- Roundkey
cypherblock : in STATE; -- State for this round
result : out STATE); -- result
end entity AddRoundKey;
 
architecture arch1 of AddRoundKey is
 
begin -- architecture arch1
 
-- purpose: Adding (Xor) roundkey words with Keywords
-- type : combinational
-- inputs : cypherblock, roundkey
-- outputs: result
Xoring : process (cypherblock, roundkey) is
begin -- process Xoring
for cnt in cypherblock'range loop
result(cnt) <= cypherblock(cnt) xor roundkey(cnt);
end loop; -- cnt
end process Xoring;
 
end architecture arch1;
/VHDL/aes_core.vhd
0,0 → 1,373
-------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Complete structural description of the AES core. No processes or protocol
-- handling is done at this level. This component is entirely depending on the
-- underlying elements.
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Thomas Ruschival
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity AES_CORE is
generic (
KEYLENGTH : NATURAL := 128; -- Size of keyblock (128, 192, 256 Bits)
DECRYPTION : BOOLEAN := false -- include decrypt datapath
);
port(
clk : in STD_LOGIC; -- system clock
data_in : in STATE; -- payload to encrypt
data_stable : in STD_LOGIC; -- flag valid payload
keyword : in DWORD; -- word of original userkey
keywordaddr : in STD_LOGIC_VECTOR(2 downto 0); -- keyword register address
w_ena_keyword : in STD_LOGIC; -- write enable of keyword to wordaddr
key_stable : in STD_LOGIC; -- key is complete and valid, start expansion
decrypt_mode : in STD_LOGIC; -- decrypt='1',encrypt='0'
keyexp_done : out STD_LOGIC; -- keyprocessing is done
result : out STATE; -- output
finished : out STD_LOGIC -- output valid
);
-- number of rounds 10, 12 or 14, needed for looping
constant NO_ROUNDS : NATURAL := lookupRounds(KEYLENGTH);
end AES_CORE;
 
 
architecture arch1 of AES_CORE is
---------------------------------------------------------------------------
-- signal for encrypt datapath
---------------------------------------------------------------------------
signal addkey_in_enc : STATE; -- State for this round
signal mixcol_out_enc : STATE; -- State with mixed Colums
signal sbox_out_enc : STATE; -- 4 columns output form ROM
signal shiftrow_out_enc : STATE; -- shifted state
signal addkey_out_enc : STATE; -- result of add key
-- control signals
signal roundkey_idx_enc : NIBBLE; -- index for selecting roundkey
signal round_type_enc : STD_LOGIC_VECTOR(1 downto 0); -- switch to select ports
signal finished_enc : STD_LOGIC; -- encryption has terminated
signal ena_encrypt : STD_LOGIC; -- enable encryption fsm only if not
-- decryption is running
-- (data_stable AND not decrypt_mode='1')
---------------------------------------------------------------------------
-- Signals for decrypt datapath
---------------------------------------------------------------------------
signal addkey_in_dec : STATE; -- input for addkey
signal addkey_out_dec : STATE; -- output of addkey
signal mixcol_out_dec : STATE; -- State with mixed Colums
signal sbox_out_dec : STATE; -- 4 columns output form ROM
signal shiftrow_in_dec : STATE; -- multiplexer output for shiftrow
signal shiftrow_out_dec : STATE; -- shifted state
-- control signals
signal round_type_dec : STD_LOGIC_VECTOR(1 downto 0); -- switch to select ports
signal roundkey_idx_dec : NIBBLE; -- index for selecting roundkey
signal finished_dec : STD_LOGIC; -- decryption has terminated
signal ena_decrypt : STD_LOGIC; -- enable encryption fsm only if not
-- decryption is running
-- (data_stable AND decrypt_mode='1')
---------------------------------------------------------------------------
-- Common signals encrypt and decrypt
---------------------------------------------------------------------------
signal roundkey_idx : NIBBLE; -- multiplexed round index
signal key_ready : STD_LOGIC; -- ouput of keyexpansion
signal roundkey : KEYBLOCK; -- Roundkey
 
begin -- architecture arch1
---------------------------------------------------------------------------
-- Multiplexers for switching encrypt and decrypt controller
-- only needed if decryption datapath is enabled
---------------------------------------------------------------------------
decryption_result_mux : if DECRYPTION generate
-- Multiplexed result port
ResultMux : for i in 0 to 3 generate
Multiplex : mux2
generic map (
IOwidth => DWORD_WIDTH)
port map (
inport_a => addkey_out_enc(i),
inport_b => addkey_out_dec(i),
selector => decrypt_mode, -- decrypt='1',encrypt='0'
outport => Result(i));
end generate ResultMux;
 
-- Multiplexed control over key index
keyindexMux : mux2
generic map (
IOwidth => NIBBLE_WIDTH)
port map (
inport_a => roundkey_idx_enc,
inport_b => roundkey_idx_dec,
selector => decrypt_mode, -- decrypt='1',encrypt='0'
outport => roundkey_idx);
 
-- Multiplexed finished signal
finished <= finished_enc when decrypt_mode = '0' else finished_dec;
end generate decryption_result_mux;
 
---------------------------------------------------------------------------
-- No DECRYPTION MODE --> multiplexers not needed
---------------------------------------------------------------------------
ecryption_only : if not DECRYPTION generate
-- result:
result <= addkey_out_enc;
--finished flag
finished <= finished_enc;
-- key index:
roundkey_idx <= roundkey_idx_enc;
end generate ecryption_only;
 
 
---------------------------------------------------------------------------
-- Key generator for roundkeys (decrypt and encrypt)
---------------------------------------------------------------------------
roundkey_generator : keyexpansionV2
generic map (
KEYLENGTH => KEYLENGTH) -- Size of keyblock (128, 192, 256 Bits)
port map (
clk => clk, -- system clock
keyword => keyword, -- word of original userkey
keywordaddr => keywordaddr, -- keyword register address
w_ena_keyword => w_ena_keyword, -- write enable of keyword to wordaddr
key_stable => key_stable, -- key is completa and valid, start expansion
roundkey_idx => roundkey_idx, -- index for selecting roundkey
roundkey => roundkey, -- key for each round
ready => key_ready); -- expansion done, roundkeys ready
 
-- Signal to the top level instance for availability of key
-- maybe used to create avalon waitrequests if key is written to keyaddress
-- range while other key is still in processing
keyexp_done <= key_ready;
 
-------------------------------------------------------------------------------
-- Encrypt datapath (always included)
-------------------------------------------------------------------------------
 
---------------------------------------------------------------------------
-- encryption FSM is always needed
---------------------------------------------------------------------------
ena_encrypt <= data_stable and not decrypt_mode;
 
-- Controller for encrypt
FSM_ENC : AES_FSM_ENCRYPT
generic map (
NO_ROUNDS => NO_ROUNDS)
port map (
clk => clk,
data_stable => ena_encrypt,
key_ready => key_ready,
round_index_out => roundkey_idx_enc,
finished => finished_enc,
round_type_sel => round_type_enc
);
 
---------------------------------------------------------------------------
-- 4 SboxBlocks of 2 SboxM4K each for the single columns
---------------------------------------------------------------------------
sboxROMs_enc : for i in 0 to 3 generate
HighWord : sbox
generic map (
INVERSE => false)
port map (
clk => clk,
address_a => addkey_out_enc(i)(31 downto 24),
address_b => addkey_out_enc(i)(23 downto 16),
q_a => sbox_out_enc(i)(31 downto 24),
q_b => sbox_out_enc(i)(23 downto 16));
LowWord : sbox
generic map (
INVERSE => false)
port map (
clk => clk,
address_a => addkey_out_enc(i)(15 downto 8),
address_b => addkey_out_enc(i)(7 downto 0),
q_a => sbox_out_enc(i)(15 downto 8),
q_b => sbox_out_enc(i)(7 downto 0));
end generate sboxROMs_enc;
 
 
---------------------------------------------------------------------------
-- Shiftrow step (encryption datapath)
---------------------------------------------------------------------------
shiftrow_enc : entity avs_aes_lib.Shiftrow(fwd)
port map (
state_in => sbox_out_enc,
state_out => shiftrow_out_enc
);
 
---------------------------------------------------------------------------
-- mix column step
---------------------------------------------------------------------------
MixColArray_enc : for i in 0 to 3 generate
mix_column_enc : entity avs_aes_lib.Mixcol(fwd)
port map (
col_in => shiftrow_out_enc(i),
col_out => mixcol_out_enc(i));
end generate MixColArray_enc;
 
---------------------------------------------------------------------------
-- Multiplexer for input to AddRoundKey, depending on round_type
-- Initial round "00": directly feed data_in (data block)
-- regular round "01": feed result from mix_column
-- final round "10": skip mixcolumn and feed result from shiftrow
---------------------------------------------------------------------------
AddKeyMuxArray_enc : for i in 0 to 3 generate
AddKeyMux : mux3
generic map (
IOwidth => DWORD_WIDTH)
port map (
inport_a => data_in(i),
inport_b => mixcol_out_enc(i),
inport_c => shiftrow_out_enc(i),
selector => round_type_enc,
outport => addkey_in_enc(i));
end generate AddKeyMuxArray_enc;
 
---------------------------------------------------------------------------
-- key addition (encrypt datapath)
---------------------------------------------------------------------------
Keyadder_enc : AddRoundKey
port map (
roundkey => roundkey,
cypherblock => addkey_in_enc,
result => addkey_out_enc
);
 
---------------------------------------------------------------------------
-- Decrypt datapath
---------------------------------------------------------------------------
decrypt_datapath : if DECRYPTION generate
---------------------------------------------------------------------------
-- Decryption FSM
---------------------------------------------------------------------------
ena_decrypt <= data_stable and decrypt_mode;
 
FSM_DEC : AES_FSM_DECRYPT
generic map (
NO_ROUNDS => NO_ROUNDS)
port map (
clk => clk,
data_stable => ena_decrypt,
key_ready => key_ready,
round_index_out => roundkey_idx_dec,
finished => finished_dec,
round_type_sel => round_type_dec
);
 
---------------------------------------------------------------------------
-- key addition (Decrypt datapath)
-- Multiplexed input on addkey (data_in or feedback)
---------------------------------------------------------------------------
AKinputMux : for i in 0 to 3 generate
mux : Mux2
generic map (
IOwidth => DWORD_WIDTH)
port map (
inport_a => data_in(i),
inport_b => sbox_out_dec(i),
selector => round_type_dec(0),
outport => addkey_in_dec(i));
end generate AKinputMux;
 
Keyadder_dec : AddRoundKey
port map (
roundkey => roundkey,
cypherblock => addkey_in_dec,
result => addkey_out_dec
);
---------------------------------------------------------------------------
-- Inverse mixcolumn
---------------------------------------------------------------------------
InverseMixCol : for i in 0 to 3 generate
mix_column_dec : entity avs_aes_lib.Mixcol(inv)
port map (
col_in => addkey_out_dec(i),
col_out => mixcol_out_dec(i));
end generate InverseMixCol;
 
---------------------------------------------------------------------------
-- Inverse Shiftrow
-- multiplexed input form either addkey_out_dec during loop or mixcol_out_dec
-- when exiting loop
---------------------------------------------------------------------------
SRinputMux : for i in 0 to 3 generate
mux : Mux2
generic map (
IOwidth => 32)
port map (
inport_a => addkey_out_dec(i),
inport_b => mixcol_out_dec(i),
selector => round_type_dec(0),
outport => shiftrow_in_dec(i));
end generate SRinputMux;
 
Shiftrow_dec : entity avs_aes_lib.Shiftrow(inv)
port map (
state_in => shiftrow_in_dec,
state_out => shiftrow_out_dec
);
 
---------------------------------------------------------------------------
-- 4 INVERSE SboxBlocks of 2 SboxM4K each for the single columns
---------------------------------------------------------------------------
sboxROMs_dec : for i in 0 to 3 generate
HighWord : sbox
generic map (
INVERSE => true)
port map (
clk => clk,
address_a => shiftrow_out_dec(i)(31 downto 24),
address_b => shiftrow_out_dec(i)(23 downto 16),
q_a => sbox_out_dec(i)(31 downto 24),
q_b => sbox_out_dec(i)(23 downto 16));
LowWord : sbox
generic map (
INVERSE => true)
port map (
clk => clk,
address_a => shiftrow_out_dec(i)(15 downto 8),
address_b => shiftrow_out_dec(i)(7 downto 0),
q_a => sbox_out_dec(i)(15 downto 8),
q_b => sbox_out_dec(i)(7 downto 0));
end generate sboxROMs_dec;
end generate decrypt_datapath;
 
end architecture arch1;
/VHDL/shiftrow_inv.vhd
0,0 → 1,116
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description: DECRYPTION implementation of Shift row.
-- Shift Row rotates the Rows of the AES Block
-- This module takes the whole Rijdael state as input, extracts the rows,
-- shifts them and rebuilts the state.
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
 
architecture inv of Shiftrow is
-- type of converting the columns into rows
subtype ROW is BYTEARRAY(0 to 3);
 
-- Row signal for easier handling of the shift operations
signal row1_in : Row; -- 1st row
signal row2_in : Row; -- 2nd row
signal row3_in : Row; -- 3rd row
signal row4_in : Row; -- 4th row
-- single rows after shift operation
-- row1 of the shifted state = row1 of unshifted state
signal row2_out : Row; -- 2nd row
signal row3_out : Row; -- 3rd row
signal row4_out : Row; -- 4th row
begin -- architecture arch1
-- purpose: build the temorary internal signals for easier handling
-- type : combinational
-- inputs : state_in
-- outputs: state_out
build_in : process (state_in) is
begin -- process build_in
-- state is a DWORD array with 32 Byte in 4 columns
-- thus we loop through the columns and slice the column in its bytes
for col_cnt in 0 to (state_in'high) loop
row1_in(col_cnt) <= state_in(col_cnt)(31 downto 24);
row2_in(col_cnt) <= state_in(col_cnt)(23 downto 16);
row3_in(col_cnt) <= state_in(col_cnt)(15 downto 8);
row4_in(col_cnt) <= state_in(col_cnt)(7 downto 0);
end loop; -- col_cnt
end process build_in;
 
 
-- purpose: Undo the shifting of rows
-- type : combinational
-- inputs : row(1 to 4)_in
-- outputs: row(1 to 4)_out
shifter : process (row2_in, row3_in, row4_in) is
begin
-- row2 is always shifted by one cell
row2_out <= row2_in(row2_in'right) & row2_in(row2_in'left to row2_in'right-1);
-- row3 is shifted by two
row3_out <= row3_in(row3_in'right-1 to row3_in'right) & row3_in(row3_in'left to row3_in'right-2);
-- rotate by 3 right
row4_out <= row4_in(row4_in'right-2 to row4_in'right) & row4_in(row4_in'left to row4_in'right-3);
end process shifter;
 
 
-- purpose: rebuilt the state form the shifted rows
-- type : combinational
-- inputs : row1_out, row2_out, row3_out, row4_out
-- outputs: state_out
rebuilt_state : process (row1_in, row2_out, row3_out, row4_out) is
begin -- process rebuilt_state
for col_cnt in 0 to state_out'high loop -- works because 15/4=3
state_out(col_cnt)(31 downto 24) <= row1_in(col_cnt);
state_out(col_cnt)(23 downto 16) <= row2_out(col_cnt);
state_out(col_cnt)(15 downto 8) <= row3_out(col_cnt);
state_out(col_cnt)(7 downto 0) <= row4_out(col_cnt);
end loop; -- col_cnt
end process rebuilt_state;
end architecture inv;
/VHDL/aes_fsm_encrypt.vhd
0,0 → 1,174
-------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Statemachine controlling the encryption datapath within aes_core.vhd does no
-- dataprocessing itself but only set enables and multiplexer selector ports
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Thomas Ruschival
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity aes_fsm_encrypt is
generic (
NO_ROUNDS : NATURAL := 10); -- number of rounds
port (
clk : in STD_LOGIC; -- System clock
data_stable : in STD_LOGIC; -- flag valid data/activate the process
-- interface for keygenerator
key_ready : in STD_LOGIC; -- flag valid roundkeys
round_index_out : out NIBBLE; -- address for roundkeys memory
-- Result of Process
finished : out STD_LOGIC; -- flag valid result
-- Control ports for the Core
round_type_sel : out STD_LOGIC_VECTOR(1 downto 0) -- selector for mux around mixcols
);
end entity aes_fsm_encrypt;
 
--
architecture Arch1 of AES_FSM_ENCRYPT is
-- types for the FSM
type AESstates is (WAIT_KEY, WAIT_DATA, INITIAL_ROUND, DO_ROUND, FINAL_ROUND);
 
-- FSM signals
signal FSM : AESstates; -- current state
signal next_FSM : AESstates; -- combinational next state
 
-- Round Counter & address for keygenerate
signal round_index : NIBBLE; -- currently processed round
signal next_round_index : NIBBLE; -- next round, index for keygenerate
begin
---------------------------------------------------------------------------
-- assign internal values to interface ports
---------------------------------------------------------------------------
round_index_out <= next_round_index; -- roundkey address
 
-- purpose: combinational generation of next state for encrytion FSM
-- type : sequential
-- inputs : FSM, data_stable, key_ready, round_index
-- outputs: next_FSM
gen_next_fsm : process (FSM, data_stable, key_ready, round_index) is
begin -- process gen_next_fsm
case FSM is
when WAIT_KEY =>
if key_ready = '1' then
next_FSM <= WAIT_DATA;
else
next_FSM <= WAIT_KEY;
end if;
when WAIT_DATA =>
if data_stable = '1' then
next_FSM <= INITIAL_ROUND;
else
next_FSM <= WAIT_DATA;
end if;
when INITIAL_ROUND =>
next_FSM <= DO_ROUND;
when DO_ROUND =>
if round_index = STD_LOGIC_VECTOR(to_unsigned(NO_ROUNDS-1, 4)) then
next_FSM <= FINAL_ROUND;
else
next_FSM <= DO_ROUND;
end if;
when FINAL_ROUND =>
next_FSM <= WAIT_DATA;
-- pragma synthesis_off
when others =>
report "FSM in strange state - aborting" severity error;
next_FSM <= WAIT_KEY;
-- pragma synthesis_on
end case;
 
-- Default behaviour in case key is invalid
if key_ready = '0' then
next_FSM <= WAIT_KEY;
end if;
end process gen_next_fsm;
 
 
-- purpose: assign outputs for encryption
-- type : combinational
-- inputs : FSM
com_output_assign : process (FSM, round_index) is
begin -- process com_output_assign
-- save defaults for encrypt_FSM
round_type_sel <= "00"; -- signal initial_round
next_round_index <= round_index;
finished <= '0';
 
case FSM is
when WAIT_KEY =>
next_round_index <= X"0";
when WAIT_DATA =>
next_round_index <= X"0";
when INITIAL_ROUND =>
round_type_sel <= "00"; -- data_in as input to AddKey
-- data is stable, FSM will switch to DO_ROUND in next cycle
next_round_index <= X"1"; -- start DO_ROUND with 1st expanded key
when DO_ROUND =>
round_type_sel <= "01";
next_round_index <= STD_LOGIC_VECTOR(UNSIGNED(round_index)+1);
when FINAL_ROUND =>
-- select signal around mixcols
round_type_sel <= "10";
next_round_index <= X"0";
finished <= '1';
when others =>
null;
end case;
end process com_output_assign;
 
-- purpose: clocked FSM for encryption
-- type : sequential
-- inputs : clk, res_n
clocked_FSM : process (clk) is
begin -- process clocked_FSM
if rising_edge(clk) then -- rising clock edge
FSM <= next_FSM;
round_index <= next_round_index;
end if;
end process clocked_FSM;
 
end architecture Arch1;
/VHDL/avs_aes.vhd
0,0 → 1,288
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Avalon Slave bus interface for aes_core. Top level component to integrate
-- into SoC
--
-- Memory address offsets:
-- 0 - 7 key
-- 8 - 11 input data if write='1', result of operation if read='1'
-- 12- 14 result of operation
-- 31 command word
--
-- Command word bit offsets meanings:
-- Byte 3-1 reserved
--
-- Byte 0:
-- Bit 7 key valid --> run key expansion
-- Bit 6 interrupt enabled
-- Bit 5-2 reserved
-- Bit 1 input data valid interpret as cypher text --> run decrypt mode
-- Bit 0 input data valid interpret as clear text --> run encrypt mode
--
-- All other bits are regarded as "reserved". The bits in one byte of the
-- command word are mutually exclusive. the behavior of the core is not
-- specified if more than one bit is set.
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity avs_AES is
generic (
KEYLENGTH : NATURAL := 256; -- AES key length
DECRYPTION : BOOLEAN := true); -- With decrypt or encrypt only
port (
-- Avalon global
clk : in STD_LOGIC; -- avalon bus clock
reset : in STD_LOGIC; -- avalon bus reset
-- Interface specific
avs_s1_chipselect : in STD_LOGIC; -- enable component
avs_s1_writedata : in STD_LOGIC_VECTOR(31 downto 0); -- data write port
avs_s1_address : in STD_LOGIC_VECTOR(4 downto 0); -- slave address space offset
avs_s1_write : in STD_LOGIC; -- write enable
avs_s1_read : in STD_LOGIC; -- read request form avalon
avs_s1_irq : out STD_LOGIC; -- interrupt to signal completion
avs_s1_waitrequest : out STD_LOGIC; -- slave not ready, request master
-- to retry later
avs_s1_readdata : out STD_LOGIC_VECTOR(31 downto 0) -- result read port
);
end entity avs_AES;
 
architecture arch1 of avs_aes is
-- Signals interfacing the AES core
signal data_stable : STD_LOGIC; -- input data is valid --> process it
signal data_in : STATE; -- register for input data of core
 
signal w_ena_keyword : STD_LOGIC; -- write enable of keyword to wordaddr
signal key_stable : STD_LOGIC; -- key is complete and valid, start expansion
 
signal decrypt_mode : STD_LOGIC; -- decrypt='1',encrypt='0'
signal result : STATE; -- output
signal finished : STD_LOGIC; -- output valid
 
-- internal logic
signal result_reg : STATE; -- register for result
signal ctrl_reg : DWORD; -- control register
signal irq : STD_LOGIC; -- internal interrupt request (register)
signal irq_i : STD_LOGIC; -- combinational value for interrupt
 
signal irq_ena : STD_LOGIC; -- alias for ctrl_reg(6)
 
signal w_ena_data_in : STD_LOGIC; -- write enable of data_in register
signal w_ena_ctrl_reg : STD_LOGIC; -- write enable of control register
signal keyexp_done : STD_LOGIC; -- signal to create waitrequests if new key is written while previous is still in
-- expansion
begin -- architecture arch1
 
-- map internal irq to avalon interface
avs_s1_irq <= irq;
 
-- rename signals for better debugging, will be optimized away in synthesis
key_stable <= ctrl_reg(7);
irq_ena <= ctrl_reg(6);
 
---------------------------------------------------------------------------
-- depending on generic enable decrypt_mode signal or permanently disable
-- it
---------------------------------------------------------------------------
enable_decrypt_mode : if DECRYPTION generate
decrypt_mode <= ctrl_reg(1);
data_stable <= ctrl_reg(0) or ctrl_reg(1);
end generate enable_decrypt_mode;
 
disable_decrypt_mode : if not DECRYPTION generate
decrypt_mode <= '0';
data_stable <= ctrl_reg(0);
end generate disable_decrypt_mode;
 
 
-- purpose: write input data to registers
-- type : sequential
-- inputs : clk
-- outputs: ctrl_reg, irq, avs_s1_readdata, key, data
write_inputs : process (clk) is
begin -- process write_inputs
if rising_edge(clk) then
-- synchronous reset
if reset = '1' then
irq <= '0';
ctrl_reg <= (others => '0');
end if;
-- DFF for IRQ
irq <= irq_i;
-- write control register
if w_ena_ctrl_reg = '1' then
ctrl_reg <= avs_s1_writedata;
end if;
-- write input to data register
if w_ena_data_in = '1' then
data_in(to_integer(UNSIGNED(avs_s1_address(1 downto 0)))) <= avs_s1_writedata;
end if;
 
-- signalling the outside world about the terminiation of the
-- computation by blanking the data_stable register bits
if finished = '1' then
-- Work is done - reset ENC and DEC
ctrl_reg(1 downto 0) <= "00";
end if;
end if;
end process write_inputs;
 
 
 
-- purpose: set/reset interrupt request flag
-- type : combinational
-- inputs : finished, avs_s1_read, irq, irq_ena
-- outputs: irq_i
IRQhandling : process (avs_s1_read, finished, irq, irq_ena) is
begin -- process IRQhandling
 
-- Set the interrupt if enabed and process finished
if irq_ena = '1' and finished = '1' then
irq_i <= '1';
elsif irq_ena = '0' or avs_s1_read = '1' then
-- any read operation resets the interrupt
irq_i <= '0';
else
irq_i <= irq; -- just keep the way it is
end if;
 
end process IRQhandling;
 
 
-- purpose: decode the write operation to the address ranges and map it to the
-- registers - any other write address range
-- e.g. avs_s1_address(4 downto 3) = "10" (result) is illegal
-- type : combinational
decode_write : process (avs_s1_address, avs_s1_write, key_stable,
keyexp_done) is
begin
-- safe default to avoid latching
w_ena_data_in <= '0';
w_ena_ctrl_reg <= '0';
w_ena_keyword <= '0';
avs_s1_waitrequest <= '0';
-- only do something if chipselect is asserted and write operation
-- requested
if avs_s1_write = '1' then
if avs_s1_address(4 downto 3) = "00" then
-- write of keywords
w_ena_keyword <= '1';
-- stall the write process if old key is still in processing
-- the user can interrupt the expansion by deasserting key_stable
avs_s1_waitrequest <= key_stable and not keyexp_done;
elsif avs_s1_address(4 downto 3) = "01" then
-- write of data
w_ena_data_in <= '1';
elsif avs_s1_address(4 downto 3) = "11" then
-- write of control register
w_ena_ctrl_reg <= '1';
end if;
end if;
end process decode_write;
 
 
-- purpose: assign read data
-- type :
-- inputs :
-- outputs: read_data
decode_read : process (avs_s1_address, avs_s1_read, ctrl_reg, result_reg) is
begin
-- only address 0x10 to 0x1F are for read, thus address bit 4
-- is always set when reading
if avs_s1_read = '1' and avs_s1_address(3) = '0' then
-- address looks something like 10xxx which corresponds to
-- 0x10 to 0x17, however result has only 4 words thus
-- address bits 1 and 0 are sufficient for decoding
avs_s1_readdata <= result_reg(to_integer(UNSIGNED(avs_s1_address(1 downto 0))));
else
-- address looks something like 11xxx which corresponds to
-- 0x18 to 0x1F, in this case always map control register,
-- we have plenty of address space so currently no exact
-- addressation needed.
-- save default, if nothing else is addressed show control register
avs_s1_readdata <= ctrl_reg;
end if;
end process decode_read;
 
 
 
-- purpose: store the combinational output of the AES core to a register
-- type : sequential
-- inputs : clk, res_n
-- outputs: result
store_result : process (clk) is
begin -- process store_result
if rising_edge(clk) then -- rising clock edge
-- Core has terminated, store the result and reset the
if finished = '1' then
result_reg <= result;
end if;
end if;
end process store_result;
 
 
---------------------------------------------------------------------------
-- Instance of the core
---------------------------------------------------------------------------
AES_CORE_1 : AES_CORE
generic map (
KEYLENGTH => KEYLENGTH, -- Size of keyblock (128, 192, 256 Bits)
DECRYPTION => DECRYPTION) -- include decrypt datapath
port map (
clk => clk, -- system clock
data_in => data_in, -- payload to encrypt
data_stable => data_stable, -- flag valid payload
keyword => avs_s1_writedata, -- word of original userkey
keywordaddr => avs_s1_address(2 downto 0), -- keyword register address
w_ena_keyword => w_ena_keyword, -- write enable of keyword to wordaddr
key_stable => key_stable, -- key is complete and valid, start expansion
decrypt_mode => decrypt_mode, -- decrypt='1',encrypt='0'
keyexp_done => keyexp_done, -- key is completely expanded
result => result, -- output
finished => finished); -- output valid
 
end architecture arch1;
/VHDL/avs_aes_pkg.vhd
0,0 → 1,386
-------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Central file for definition of types and global functions for handling of
-- datatypes and generics. All components are defined here.
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Thomas Ruschival
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
package avs_aes_pkg is
-- tiny 4 bit value
constant NIBBLE_WIDTH : NATURAL := 4;
subtype NIBBLE_RANGE is NATURAL range NIBBLE_WIDTH-1 downto 0;
subtype NIBBLE is STD_LOGIC_VECTOR(NIBBLE_RANGE);
-- type definition byte: 8 bit = byte (cell of the
-- state)
constant BYTE_WIDTH : NATURAL := 8;
subtype BYTE_RANGE is NATURAL range BYTE_WIDTH-1 downto 0;
subtype BYTE is STD_LOGIC_VECTOR(BYTE_RANGE);
 
-- Type definition word: 16 bit = word
constant WORD_WIDTH : NATURAL := 16;
subtype WORD_RANGE is NATURAL range WORD_WIDTH-1 downto 0;
subtype WORD is STD_LOGIC_VECTOR(WORD_RANGE); -- storage type "word"
 
-- type definition Dword: 32 bit = dword
constant DWORD_WIDTH : NATURAL := 32;
subtype DWORD_RANGE is NATURAL range DWORD_WIDTH-1 downto 0;
subtype DWORD is STD_LOGIC_VECTOR(DWORD_RANGE);
 
-- type definition Qword: 64 bit = qword
constant QWORD_WIDTH : NATURAL := 64;
subtype QWORD_RANGE is NATURAL range QWORD_WIDTH-1 downto 0;
subtype QWORD is STD_LOGIC_VECTOR(QWORD_RANGE);
 
 
---------------------------------------------------------------------------
-- aggregates of Signals
---------------------------------------------------------------------------
-- array of 64 bit words
type QWORDARRAY is array (NATURAL range <>) of QWORD;
-- array of 32 bit words
type DWORDARRAY is array (NATURAL range <>) of DWORD;
-- array of 16 bit words
type WORDARRAY is array (NATURAL range <>) of WORD;
-- array of 8 bit words
type BYTEARRAY is array (NATURAL range <>) of BYTE;
-- array of NATURALS
type NATURALARRAY is array (NATURAL range <>) of NATURAL;
-- array of integers
type INTEGERARRAY is array (NATURAL range <>) of INTEGER;
 
-- Byte Matrix
type BYTEMATRIX is array (NATURAL range <>, NATURAL range <>) of BYTE;
 
 
 
---------------------------------------------------------------------------
-- types for signal mnemonics
---------------------------------------------------------------------------
type ACCESS_MODE is (W , R); -- Modes how memory can be accessed
type CRYPTODIRECTION is (encrypt, decrypt); -- Switch to encrypt or decrypt
 
---------------------------------------------------------------------------
-- constants for convienience
---------------------------------------------------------------------------
constant NULL_QWORD : QWORD := (others => '0'); -- Qword to clear memory
constant NULL_DWORD : DWORD := (others => '0'); -- Dword to clear memory
constant NULL_WORD : WORD := (others => '0'); -- word to clear memory
constant NULL_BYTE : BYTE := (others => '0'); -- byte to clear memory
 
 
 
 
-- The state type is the matrix unfolded into a linear representation
-- the length of a column is always fixed so every 32 Bit of this vector
-- represents a column of the state
--
-- once and for all: THE COLUMNS STAND WITH THE MSB (Bit 31) AT THE TOP!!
-- => cell0, cell4, cell8... are byte0 of the column
--
-- state: ==> BYTEARRAY (0 to (BLOCKLENGTH/8)-1);
-- cell0 cell4 ...
-- cell1 cell5 ... ==> cell0,cell1,cell2,cell3,cell4,cell5....
-- cell2 cell6 ... ^ ^-bit[8]
-- cell3 ... ... ^-bit[0]
subtype STATE is DWORDARRAY (0 to 3);
-- alias KEYBLOCK is STATE;
-- DUMB xilinx compiler does not know aliases for subtypes.....
subtype KEYBLOCK is DWORDARRAY (0 to 3);
 
 
-- Round constants for XOR in Keygenerator
constant ROUNDCONSTANTS : BYTEARRAY(0 to 15) := (X"00", X"01", X"02", X"04", X"08", X"10", X"20", X"40",
X"80", X"1B", X"36", X"6C", X"D8", X"AB", X"4D", X"9A");
 
-------------------------------------------------------------------------------
-- General (useful) Components
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- register word with variable width
---------------------------------------------------------------------------
component memory_word
generic (
IOwidth : POSITIVE := 1 -- width of register
);
port (
data_in : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- input
data_out : out STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- output
res_n : in STD_LOGIC; -- system reset active low
ena : in STD_LOGIC; -- enable write
clk : in STD_LOGIC -- system clock
);
end component;
 
 
---------------------------------------------------------------------------
-- 2:1 STD_LOGIC_VECTOR multiplexer
---------------------------------------------------------------------------
component mux2
generic (
IOwidth : POSITIVE := 1 -- width of I/O ports
);
port (
inport_a : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 1
inport_b : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 2
selector : in STD_LOGIC; -- switch TO select ports
outport : out STD_LOGIC_VECTOR (IOwidth-1 downto 0) -- output
);
end component;
---------------------------------------------------------------------------
-- 3:1 multiplexer
---------------------------------------------------------------------------
component mux3
generic (
IOwidth : POSITIVE := 1 -- width of I/O ports
);
port (
inport_a : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 1
inport_b : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 2
inport_c : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 3
selector : in STD_LOGIC_VECTOR(1 downto 0); -- switch TO select ports
outport : out STD_LOGIC_VECTOR (IOwidth-1 downto 0) -- output
);
end component;
 
---------------------------------------------------------------------------
-- Components relevant for AVS_AES
---------------------------------------------------------------------------
component AddRoundKey
port (
roundkey : in KEYBLOCK; -- Roundkey
cypherblock : in STATE; -- State for this round
result : out STATE
);
end component;
 
---------------------------------------------------------------------------
-- FSM that controls the dataflow of AES_ECB encryption
---------------------------------------------------------------------------
component AES_FSM_ENCRYPT is
generic (
NO_ROUNDS : NATURAL := 10); -- number of rounds
port (
clk : in STD_LOGIC; -- System clock
data_stable : in STD_LOGIC; -- flag valid data/activate the process
-- interface for keygenerator
key_ready : in STD_LOGIC; -- flag valid roundkeys
round_index_out : out NIBBLE; -- address for roundkeys memory
-- Result of Process
finished : out STD_LOGIC; -- flag valid result
-- Control ports for the Core
round_type_sel : out STD_LOGIC_VECTOR(1 downto 0) -- selector for mux around mixcols
);
end component;
 
---------------------------------------------------------------------------
-- FSM that controls the dataflow of AES_ECB decryption
---------------------------------------------------------------------------
component AES_FSM_DECRYPT is
generic (
NO_ROUNDS : NATURAL := 10); -- number of rounds
port (
clk : in STD_LOGIC; -- System clock
data_stable : in STD_LOGIC; -- flag valid data/activate the process
-- interface for keygenerator
key_ready : in STD_LOGIC; -- flag valid roundkeys
round_index_out : out NIBBLE; -- address for roundkeys memory
-- Result of Process
finished : out STD_LOGIC; -- flag valid result
-- Control ports for the Core
round_type_sel : out STD_LOGIC_VECTOR(1 downto 0) -- selector for mux around mixcols
);
end component;
 
 
---------------------------------------------------------------------------
-- Mixcolumn component
-- (has 2 architectures inverse and forward)
---------------------------------------------------------------------------
component Mixcol is
port (
col_in : in DWORD; -- one column of the state
col_out : out DWORD); -- output column
end component Mixcol;
 
---------------------------------------------------------------------------
-- Sbox component
-- The interface is 2x8Bit because Altera megafunction is supposed to be at max
-- 8Bit dual port ROM (and I relied on a altera quartus generated component
-- before) see architecture m4k
-------------------------------------------------------------------------------
component sbox is
generic (
INVERSE : BOOLEAN); -- is this the inverse or the forward
-- lookup table.
-- TRUE -> inverse sbox
-- FALSE -> forward sbox
port (
clk : in STD_LOGIC; -- system clock
address_a : in STD_LOGIC_VECTOR (7 downto 0); -- 1st byte
address_b : in STD_LOGIC_VECTOR (7 downto 0); -- 2nd byte
q_a : out STD_LOGIC_VECTOR (7 downto 0); -- substituted 1st byte
q_b : out STD_LOGIC_VECTOR (7 downto 0)); -- substituted 2nd byte
end component sbox;
 
---------------------------------------------------------------------------
-- Encrypt version of Shiftrow component
-- (has 2 architectures inverse and forward)
---------------------------------------------------------------------------
component Shiftrow
port (
state_in : in STATE; -- Raw input data TO be shifted
state_out : out STATE -- shifted result
);
end component;
 
---------------------------------------------------------------------------
-- Keykenerator for roundkeys
---------------------------------------------------------------------------
component keyexpansionV2 is
generic (
KEYLENGTH : NATURAL); -- Size of keyblock (128, 192, 256 Bits)
port (
clk : in STD_LOGIC; -- system clock
keyword : in DWORD; -- word of original userkey
keywordaddr : in STD_LOGIC_VECTOR(2 downto 0); -- keyword register address
w_ena_keyword : in STD_LOGIC; -- write enable of keyword to wordaddr
key_stable : in STD_LOGIC; -- key is completa and valid, start expansion
roundkey_idx : in NIBBLE; -- index for selecting roundkey
roundkey : out KEYBLOCK; -- key for each round
ready : out STD_LOGIC); -- expansion done, roundkeys ready
end component keyexpansionV2;
 
 
---------------------------------------------------------------------------
-- Keykenerator for roundkeys
---------------------------------------------------------------------------
component keygenerator is
generic (
KEYLENGTH : NATURAL := 128; -- Size of keyblock (128, 192, 256 Bits)
NO_ROUNDS : NATURAL := 10 -- how many rounds
);
port (
clk : in STD_LOGIC; -- system clock
initialkey : in KEYBLOCK; -- original userkey
key_stable : in STD_LOGIC; -- signal for enabling write of initial
-- key and signal valid key
-- ena=0->blank_key
round : in NIBBLE; -- index for selecting roundkey
roundkey : out KEYBLOCK; -- key for each round
ready : out STD_LOGIC
);
end component;
 
 
 
---------------------------------------------------------------------------
-- Complete Core implementation
---------------------------------------------------------------------------
component AES_CORE is
generic (
KEYLENGTH : NATURAL; -- Size of keyblock (128, 192, 256 Bits)
DECRYPTION : BOOLEAN); -- include decrypt datapath
port (
clk : in STD_LOGIC; -- system clock
data_in : in STATE; -- payload to encrypt
data_stable : in STD_LOGIC; -- flag valid payload
keyword : in DWORD; -- word of original userkey
keywordaddr : in STD_LOGIC_VECTOR(2 downto 0); -- keyword register address
w_ena_keyword : in STD_LOGIC; -- write enable of keyword to wordaddr
key_stable : in STD_LOGIC; -- key is complete and valid, start expansion
decrypt_mode : in STD_LOGIC; -- decrypt='1',encrypt='0'
keyexp_done : out STD_LOGIC; -- keyprocessing is done
result : out STATE; -- output
finished : out STD_LOGIC); -- output valid
end component AES_CORE;
---------------------------------------------------------------------------
-- function to calculate number of rounds based on keylength, returns
-- either 10,12 or 14
---------------------------------------------------------------------------
function lookupRounds (keylen : in NATURAL) return NATURAL;
 
---------------------------------------------------------------------------
-- Functions for convinience
---------------------------------------------------------------------------
-- modulo additon DWORD+DWORD=DWORD
function "+" (left, right : in DWORD) return DWORD;
 
end package avs_aes_pkg;
 
package body avs_aes_pkg is
 
---------------------------------------------------------------------------
-- function to calculate number of rounds based on keylength, returns
-- either 10,12 or 14
---------------------------------------------------------------------------
function lookupRounds(keylen : in NATURAL) return NATURAL is
begin
assert (keylen = 128 or keylen = 192 or keylen = 256)
report "Wrong KEYLENGTH parameter" severity failure;
if keylen = 128 then
return 10;
elsif keylen = 192 then
return 12;
elsif keylen = 256 then
return 14;
else
return 0;
end if;
end;
 
-- modulo additon DWORD+DWORD=DWORD
function "+" (left, right : in DWORD) return DWORD
is
variable result : UNSIGNED(DWORD_RANGE);
begin
result := UNSIGNED(left) + UNSIGNED(right);
return STD_LOGIC_VECTOR(result);
end function;
 
end package body avs_aes_pkg;
/VHDL/keyexpansionV2.vhd
0,0 → 1,453
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description: hardware keyexpansion core.
-------------------------------------------------------------------------------
-- Generates all roundkeys for the AES algorithm. in each round on key is used
-- to XOR with the round data, e.g. the state. because this is for encryption
-- of multiple plaintext blocks always the same roundkey sequence the keys are
-- stored until a new key is provided.
-- Starting from an initial 128, 192 or 256 Bit key (table of 4,6 or eight
-- columns = i) the sucessive roundkeys are calculated in the following way:
-- 1.) The 1st round is done with the initial key with the dwords dw[0] to
-- dw[i-1]
-- 2.) dw[n*i] is build through rotating dw[i-1] 1 left, Substituting its
-- contents with the Sbox function, the result then is XORed with
-- roundconstant[n] and it is again XORed with dw[(n-1)i].
-------------------------------------------------------------------------------
-- TODO: Implement another copy of this as wrapper to RAM to enable software
-- keyexpanion
--
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity keyexpansionV2 is
generic (
KEYLENGTH : NATURAL := 128 -- Size of keyblock (128, 192, 256 Bits)
);
port (
clk : in STD_LOGIC; -- system clock
keyword : in DWORD; -- word of original userkey
keywordaddr : in STD_LOGIC_VECTOR(2 downto 0); -- keyword register address
w_ena_keyword : in STD_LOGIC; -- write enable of keyword to wordaddr
key_stable : in STD_LOGIC; -- key is completa and valid, start expansion
-- key_stable=0-> invalidate key
roundkey_idx : in NIBBLE; -- index for selecting roundkey
roundkey : out KEYBLOCK; -- key for each round
ready : out STD_LOGIC -- expansion done, roundkeys ready
);
-- number of rounds, needed for looping
constant NO_ROUNDS : NATURAL := lookupRounds(KEYLENGTH);
-- Number of columns in user key: 4,6, or 8
constant Nk : NATURAL := KEYLENGTH/DWORD_WIDTH;
-- Number of interations
constant LOOP_BOUND : NATURAL := 4*NO_ROUNDS;
end entity keyexpansionV2;
 
 
architecture ach1 of keyexpansionV2 is
 
-- Round constants for XOR i/Nk is max 10 for Nk=4
constant GF_ROUNDCONSTANTS_4_6 : BYTEARRAY(0 to 10) :=
(X"01", X"02", X"04", X"08", X"10", X"20", X"40", X"80", X"1B", X"36", X"6C");
-- keep quartus from complaining about "index not wide enough for all
-- elements in the array" i/Nk is max 7 for Nk=8
constant GF_ROUNDCONSTANTS_8 : BYTEARRAY(0 to 7) :=
(X"01", X"02", X"04", X"08", X"10", X"20", X"40", X"80");
signal roundconstant : BYTE;
 
-- memory for roundkeys
type MEMORY_128 is array (0 to 15) of STD_LOGIC_VECTOR(127 downto 0);
signal KEYMEM : MEMORY_128;
 
-- key memory signals
signal mem_in : STD_LOGIC_VECTOR(127 downto 0); -- in port for keymemory
signal mem_out : STD_LOGIC_VECTOR(127 downto 0); -- out port of keymemory
signal keymem_addr : UNSIGNED(3 downto 0); -- address of RAM
signal w_ena_keymem : STD_LOGIC; -- write enable to keymemory
-- write address for keymemory
signal w_addr : UNSIGNED(3 downto 0); -- register
signal next_w_addr : UNSIGNED(3 downto 0); -- combinational next value
 
-- Interconnect for shiftregister
signal keyshiftreg_in : DWORDARRAY(Nk-1 downto 0); -- input from multiplexers
signal keyshiftreg_out : DWORDARRAY(Nk-1 downto 0); -- output
signal keyshiftreg_ena : STD_LOGIC_VECTOR(7 downto 0); -- enable of single registers
-- Selector for Load multiplexer, only select keyword to be written to
-- shiftreg if key_stable is deasserted loadmux_sel <= not key_stable
signal loadmux_sel : STD_LOGIC;
 
---------------------------------------------------------------------------
-- datapath expansion algorithm
---------------------------------------------------------------------------
signal exp_in : DWORD; -- in for expansion logic (w[i-1])
signal rot_out : DWORD; -- rotated column (in to sbox)
signal to_sbox : DWORD; -- substituted key column (out from sbox)
signal from_sbox : DWORD; -- substituted key column (out from sbox)
signal delayed_col : DWORD; -- delayed unprocessed key column w[i-1] | imod4/=0
signal XorRcon_out : DWORD; -- rotated,substituted,XORed with Rcon column w[i-1]|imod4=0
signal mux_processed : DWORD; -- multiplexed delayed_col or XorRcon_out
signal Xor_lastblock_in : DWORD; -- input for w[i-1] XOR w[i-Nk]
signal last_word : DWORD; -- result of expansion w[i] --> w[i-1] for next round
 
---------------------------------------------------------------------------
-- Controller signals
---------------------------------------------------------------------------
signal first_round : STD_LOGIC; -- selector Mux_input only '0' in first round
signal shift_ena : STD_LOGIC; -- enable shift of register bank w[i-1] to w[i-Nk]
signal imodNk0 : STD_LOGIC; -- mux selector delayed_col or XorRcon_out if imodNk=0
-- Special logic for Nk=8 256 Bit key
signal imod84 : STD_LOGIC; -- mux selector around Rotate to substitute if imod8=4
-- Statemachine
type KEYEXPANSIONSTATES is (INIT, SUBSTITUTE, SHIFT, WRITELAST, DONE);
signal expState : KEYEXPANSIONSTATES; -- register value
signal next_expState : KEYEXPANSIONSTATES; -- combinational next value
-- counter for expanded keywords (max Nk*(Nr+1)=4*(14+1))
signal i : UNSIGNED(5 downto 0); -- register
signal next_i : UNSIGNED(5 downto 0); -- combinational next value
begin -- architecture ach1
 
-------------------------------------------------------------------------------
-- Key load and shift register datapath
-------------------------------------------------------------------------------
loadmux_sel <= not key_stable;
 
Shiftreg : for i in 0 to Nk-1 generate
-- ordinary words are regular shift registers
rest_of_shiftreg : if i /= Nk-1 generate
loadmux : Mux2
generic map (
IOwidth => DWORD_WIDTH)
port map (
inport_a => keyshiftreg_out(i+1),
inport_b => keyword,
selector => loadmux_sel,
outport => keyshiftreg_in(i));
keywordregister : memory_word
generic map (
IOwidth => DWORD_WIDTH)
port map (
data_in => keyshiftreg_in(i),
data_out => keyshiftreg_out(i),
res_n => '1',
clk => clk,
ena => keyshiftreg_ena(i));
end generate;
-- last word is different: here result from last expansion round is
-- shifted in
lastDWORD : if i = Nk-1 generate
lastw_loadmux : Mux2
generic map (
IOwidth => DWORD_WIDTH)
port map (
inport_a => last_word, -- loopback form expansion logic
inport_b => keyword,
selector => loadmux_sel,
outport => keyshiftreg_in(i));
 
last_keywordreg : memory_word
generic map (
IOwidth => DWORD_WIDTH)
port map (
data_in => keyshiftreg_in(i),
data_out => keyshiftreg_out(i),
res_n => '1',
clk => clk,
ena => keyshiftreg_ena(i));
end generate lastDWORD;
end generate Shiftreg;
 
-- Lower 4 Keywords will be written to key ram
mem_in <= keyshiftreg_out(0) &keyshiftreg_out(1) & keyshiftreg_out(2) & keyshiftreg_out(3);
-- map memory port to a nice state
roundkey <= (0 => mem_out(127 downto 96),
1 => mem_out(95 downto 64),
2 => mem_out(63 downto 32),
3 => mem_out(31 downto 0));
 
-- purpose: represent ram for storage of roundkeys (DP ram should be inferred)
-- type : sequential
-- inputs : clk, res_n
-- outputs: mem_out
keymemory : process (clk) is
begin -- process keymemory
if rising_edge(clk) then -- rising clock edge
if w_ena_keymem = '1' then
KEYMEM(to_integer(w_addr)) <= mem_in;
end if;
mem_out <= KEYMEM(to_integer(UNSIGNED(roundkey_idx)));
end if;
end process keymemory;
 
 
-- purpose: set the respective enable bits for each register if either registes must be shifted
-- right. only enable external write if key_stable='0'
-- or are loaded with userkey
-- type : combinational
-- inputs : w_ena_keyword, shift_ena,keywordaddr
-- outpukeyshiftreg_ena
enableRegs : process (key_stable, keywordaddr, shift_ena, w_ena_keyword) is
begin -- process enableRegs
-- default: freeze the registers
keyshiftreg_ena <= (others => '0');
-- if words are loaded externally only enable register for respective address
-- words must only be written if key_stable is not asserted and
-- therefore the FSM is in INIT state
if w_ena_keyword = '1' and key_stable = '0' then
keyshiftreg_ena(to_integer(UNSIGNED(keywordaddr))) <= '1';
-- if register shall be shifted, enable all
elsif shift_ena = '1' then
keyshiftreg_ena <= (others => '1');
end if;
end process enableRegs;
 
-- purpose: write combinational next_write address to register
-- type : sequential
-- inputs : clk, next_w_addr
-- outputs: w_addr
address_incr : process (clk) is
begin -- process address_incr
if rising_edge(clk) then -- rising clock edge
w_addr <= next_w_addr;
end if;
end process address_incr;
 
 
-------------------------------------------------------------------------------
-- Expansion Datapath
-------------------------------------------------------------------------------
 
---------------------------------------------------------------------------
-- Rotate left the key column a1,a2,a3,a4 --> a2,a3,4,a1
---------------------------------------------------------------------------
rot_out <= keyshiftreg_out(Nk-1)(23 downto 0) & keyshiftreg_out(Nk-1)(31 downto 24);
 
---------------------------------------------------------------------------
-- Special datapath for 256Bit key (Nk=8) if imodNk=4 to
-- substitute w[i-1]
---------------------------------------------------------------------------
NK8_sboxin : if KEYLENGTH = 256 generate
Nk8_sboxmux : mux2
generic map (
IOwidth => 32)
port map (
inport_a => rot_out,
inport_b => keyshiftreg_out(Nk-1),
selector => imod84,
outport => to_sbox);
 
-- Logic to switch the multiplexer
imod84 <= '1' when (i mod 8 = 4) else '0';
end generate NK8_sboxin;
 
 
regular_sboxin : if KEYLENGTH /= 256 generate
to_sbox <= rot_out;
end generate regular_sboxin;
 
---------------------------------------------------------------------------
-- Keygenerate gets its own sboxes to substitute columns to define clear
-- interface and increase f_max as this was on the critical path while
-- shared with aes_core_encrypt
---------------------------------------------------------------------------
HighWord : sbox
generic map (
INVERSE => false)
port map (
clk => clk,
address_a => to_sbox(31 downto 24),
address_b => to_sbox(23 downto 16),
q_a => from_sbox(31 downto 24),
q_b => from_sbox(23 downto 16));
LowWord : sbox
generic map (
INVERSE => false)
port map (
clk => clk,
address_a => to_sbox(15 downto 8),
address_b => to_sbox(7 downto 0),
q_a => from_sbox(15 downto 8),
q_b => from_sbox(7 downto 0));
 
---------------------------------------------------------------------------
-- Xor column with Roundconstant[i/Nk], make it 32 BIT
---------------------------------------------------------------------------
XorRcon_out <= from_sbox xor (roundconstant & X"000000");
 
---------------------------------------------------------------------------
-- select intermediate result of processed w[i-1] either direct or
-- processed with Sub(Rot(W[i-1]) XOR roundconstant if i mod Nk = 0
---------------------------------------------------------------------------
Mux_wi_1 : mux2
generic map (
IOwidth => DWORD_WIDTH)
port map (
inport_a => keyshiftreg_out(Nk-1),
inport_b => XorRcon_out,
selector => imodNk0,
outport => mux_processed);
-- Logic to switch the multiplexer
imodNk0 <= '1' when (i mod Nk = 0) else '0';
 
---------------------------------------------------------------------------
-- Special datapath for 256Bit key (Nk=8) if imodNk=4 to
-- substitute w[i-1]
---------------------------------------------------------------------------
NK8_wi_1 : if KEYLENGTH = 256 generate
Nk8_mux_wi_1 : mux2
generic map (
IOwidth => 32)
port map (
inport_a => mux_processed,
inport_b => from_sbox,
selector => imod84,
outport => Xor_lastblock_in);
end generate NK8_wi_1;
 
 
regular_wi_1 : if KEYLENGTH /= 256 generate
Xor_lastblock_in <= mux_processed;
end generate regular_wi_1;
 
---------------------------------------------------------------------------
-- Xor currently processed column w[i-1] with w[i-Nk]
---------------------------------------------------------------------------
last_word <= Xor_lastblock_in xor keyshiftreg_out(0);
 
 
-------------------------------------------------------------------------------
-- Controller for keyexpansion algorithm
-------------------------------------------------------------------------------
 
-- purpose: Compute the next state of keyexpansion FSM
-- type : combinational
-- inputs : expState, i, key_stable
-- outputs: next_expState
nextState : process (expState, i, key_stable) is
begin
-- Save defaults to avoid latches
next_expState <= expState;
-- FSM
case expState is
when INIT =>
if key_stable = '1' then
next_expState <= SUBSTITUTE;
end if;
when SUBSTITUTE =>
next_expState <= SHIFT;
when SHIFT =>
if i = LOOP_BOUND then
next_expState <= DONE;
else
next_expState <= SUBSTITUTE;
end if;
when WRITELAST =>
next_expState <= DONE;
when DONE =>
-- just stay
next_expState <= expState;
end case;
-- reset the process whenever key is invalid
if key_stable = '0' then
next_expState <= INIT;
end if;
end process nextState;
 
-- purpose: assign signals according to input and current state
-- type : combinational
-- inputs : expState, i
-- outputs: shift_ena, next_i, ready
stateToOutput : process (expState, i, w_addr) is
begin
-- Save defaults to avoid latches
shift_ena <= '0';
next_i <= i;
ready <= '0';
w_ena_keymem <= '0';
next_w_addr <= w_addr;
case expState is
when INIT =>
-- reset all variables to defined state
next_i <= (others => '0');
next_w_addr <= (others => '0');
when SUBSTITUTE =>
-- Substitute is a mere wait state for 1 cycle until SBOX has done
-- the lookup
null;
when SHIFT =>
next_i <= i+1;
shift_ena <= '1';
if (i mod 4 = 0) then
w_ena_keymem <= '1';
next_w_addr <= w_addr+1;
end if;
when WRITELAST =>
w_ena_keymem <= '1';
next_w_addr <= w_addr+1;
when DONE =>
ready <= '1';
when others => null;
end case;
end process stateToOutput;
 
-- purpose: write state and variables to registers
-- type : sequential
-- inputs : clk, res_n
-- outputs:
registeredFSMsignals : process (clk) is
begin -- process registeredFSMsignals
if rising_edge(clk) then -- rising clock edge
i <= next_i;
expState <= next_expState;
if Nk = 8 then
roundconstant <= GF_ROUNDCONSTANTS_8(to_integer(i)/Nk);
else
-- TODO : avoid divide operator, error when compiling with Nk=6 anx ISE 10.1
roundconstant <= GF_ROUNDCONSTANTS_4_6(to_integer(i)/Nk);
end if;
end if;
end process registeredFSMsignals;
 
end architecture ach1;
/VHDL/sboxM4k.vhd
0,0 → 1,188
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- instantiation of an Altera M4K blockram as dual port ROM
-- they have the nice feature of allowing an initialization file. with the
-- generic rominitfile it is possible to select the encryption or decryption
-- version sbox.hex and sbox_inv.hex
-- Only 8-Bit dual port was supported on CyloneII... this is why we need a lot
-- of blockrams in aes_core.vhd AND keyexpansionV2.vhd
--
-------------------------------------------------------------------------------
-- Todo:
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
library altera_mf;
use altera_mf.all;
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
 
 
architecture M4k of sbox is
---------------------------------------------------------------------------
-- Altera Stuff
-- ( I don't want this in avs_aes_pkg because it is vendor specific)
---------------------------------------------------------------------------
component altsyncram
generic (
ADDRESS_REG_B : STRING;
CLOCK_ENABLE_INPUT_A : STRING;
CLOCK_ENABLE_INPUT_B : STRING;
CLOCK_ENABLE_OUTPUT_A : STRING;
CLOCK_ENABLE_OUTPUT_B : STRING;
INDATA_REG_B : STRING;
INIT_FILE : STRING;
INTENDED_DEVICE_FAMILY : STRING;
LPM_TYPE : STRING;
NUMWORDS_A : NATURAL;
NUMWORDS_B : NATURAL;
OPERATION_MODE : STRING;
OUTDATA_ACLR_A : STRING;
OUTDATA_ACLR_B : STRING;
OUTDATA_REG_A : STRING;
OUTDATA_REG_B : STRING;
POWER_UP_UNINITIALIZED : STRING;
WIDTHAD_A : NATURAL;
WIDTHAD_B : NATURAL;
WIDTH_A : NATURAL;
WIDTH_B : NATURAL;
WIDTH_BYTEENA_A : NATURAL;
WIDTH_BYTEENA_B : NATURAL;
WRCONTROL_WRADDRESS_REG_B : STRING
);
port (
wren_a : in STD_LOGIC;
wren_b : in STD_LOGIC;
clock0 : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR (7 downto 0);
address_b : in STD_LOGIC_VECTOR (7 downto 0);
q_a : out STD_LOGIC_VECTOR (7 downto 0);
q_b : out STD_LOGIC_VECTOR (7 downto 0);
data_a : in STD_LOGIC_VECTOR (7 downto 0);
data_b : in STD_LOGIC_VECTOR (7 downto 0)
);
end component;
begin
 
assign_inverse : if INVERSE generate
m4kblock_inv : altsyncram
generic map (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "sbox_inv.hex",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
outdata_reg_b => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 8,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
port map (
wren_a => '0', -- we don't write to ROM
wren_b => '0', -- we don't write to ROM
clock0 => clk,
data_a => (others => '0'), -- dumb compiler wants it anyway
data_b => (others => '0'), -- dumb compiler wants it anyway
address_a => address_a,
address_b => address_b,
q_a => q_a,
q_b => q_b
);
end generate assign_inverse;
 
assign_encrypt : if not INVERSE generate
m4kblock_fwd : altsyncram
generic map (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "sbox.hex",
intended_device_family => "Cyclone II",
lpm_type => "altsyncram",
numwords_a => 256,
numwords_b => 256,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
outdata_reg_b => "UNREGISTERED", -- IMPORTANT not CLOCK0!!!
power_up_uninitialized => "FALSE",
widthad_a => 8,
widthad_b => 8,
width_a => 8,
width_b => 8,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
port map (
wren_a => '0', -- we don't write to ROM
wren_b => '0', -- we don't write to ROM
clock0 => clk,
data_a => (others => '0'), -- dumb compiler wants it anyway
data_b => (others => '0'), -- dumb compiler wants it anyway
address_a => address_a,
address_b => address_b,
q_a => q_a,
q_b => q_b
);
end generate assign_encrypt;
end M4k;
/VHDL/sbox_arch1.vhd
0,0 → 1,153
----------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Sbox implements a lookup ROM for nonlinear substitution of a Bytearray.
-- trying to make use of Altera Blockram and Xilinx Blockram without using
-- vendor specific implementation like in sboxM4k.
--
-------------------------------------------------------------------------------!
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
architecture ARCH1 of sbox is
---------------------------------------------------------------------------
-- Sbox of Rindael for nonlinear substitution of bytes
-- taken from wikipedia.de
-- Here just the values as lookup table - tried to make use of RAM as ROM
---------------------------------------------------------------------------
constant decrypt_table : BYTEARRAY(0 to 255) := (
0 => X"52", 1 => X"09", 2 => X"6A", 3 => X"D5", 4 => X"30", 5 => X"36", 6 => X"A5", 7 => X"38",
8 => X"BF", 9 => X"40", 10 => X"A3", 11 => X"9E", 12 => X"81", 13 => X"F3", 14 => X"D7", 15 => X"FB",
16 => X"7C", 17 => X"E3", 18 => X"39", 19 => X"82", 20 => X"9B", 21 => X"2F", 22 => X"FF", 23 => X"87",
24 => X"34", 25 => X"8E", 26 => X"43", 27 => X"44", 28 => X"C4", 29 => X"DE", 30 => X"E9", 31 => X"CB",
32 => X"54", 33 => X"7B", 34 => X"94", 35 => X"32", 36 => X"A6", 37 => X"C2", 38 => X"23", 39 => X"3D",
40 => X"EE", 41 => X"4C", 42 => X"95", 43 => X"0B", 44 => X"42", 45 => X"FA", 46 => X"C3", 47 => X"4E",
48 => X"08", 49 => X"2E", 50 => X"A1", 51 => X"66", 52 => X"28", 53 => X"D9", 54 => X"24", 55 => X"B2",
56 => X"76", 57 => X"5B", 58 => X"A2", 59 => X"49", 60 => X"6D", 61 => X"8B", 62 => X"D1", 63 => X"25",
64 => X"72", 65 => X"F8", 66 => X"F6", 67 => X"64", 68 => X"86", 69 => X"68", 70 => X"98", 71 => X"16",
72 => X"D4", 73 => X"A4", 74 => X"5C", 75 => X"CC", 76 => X"5D", 77 => X"65", 78 => X"B6", 79 => X"92",
80 => X"6C", 81 => X"70", 82 => X"48", 83 => X"50", 84 => X"FD", 85 => X"ED", 86 => X"B9", 87 => X"DA",
88 => X"5E", 89 => X"15", 90 => X"46", 91 => X"57", 92 => X"A7", 93 => X"8D", 94 => X"9D", 95 => X"84",
96 => X"90", 97 => X"D8", 98 => X"AB", 99 => X"00", 100 => X"8C", 101 => X"BC", 102 => X"D3", 103 => X"0A",
104 => X"F7", 105 => X"E4", 106 => X"58", 107 => X"05", 108 => X"B8", 109 => X"B3", 110 => X"45", 111 => X"06",
112 => X"D0", 113 => X"2C", 114 => X"1E", 115 => X"8F", 116 => X"CA", 117 => X"3F", 118 => X"0F", 119 => X"02",
120 => X"C1", 121 => X"AF", 122 => X"BD", 123 => X"03", 124 => X"01", 125 => X"13", 126 => X"8A", 127 => X"6B",
128 => X"3A", 129 => X"91", 130 => X"11", 131 => X"41", 132 => X"4F", 133 => X"67", 134 => X"DC", 135 => X"EA",
136 => X"97", 137 => X"F2", 138 => X"CF", 139 => X"CE", 140 => X"F0", 141 => X"B4", 142 => X"E6", 143 => X"73",
144 => X"96", 145 => X"AC", 146 => X"74", 147 => X"22", 148 => X"E7", 149 => X"AD", 150 => X"35", 151 => X"85",
152 => X"E2", 153 => X"F9", 154 => X"37", 155 => X"E8", 156 => X"1C", 157 => X"75", 158 => X"DF", 159 => X"6E",
160 => X"47", 161 => X"F1", 162 => X"1A", 163 => X"71", 164 => X"1D", 165 => X"29", 166 => X"C5", 167 => X"89",
168 => X"6F", 169 => X"B7", 170 => X"62", 171 => X"0E", 172 => X"AA", 173 => X"18", 174 => X"BE", 175 => X"1B",
176 => X"FC", 177 => X"56", 178 => X"3E", 179 => X"4B", 180 => X"C6", 181 => X"D2", 182 => X"79", 183 => X"20",
184 => X"9A", 185 => X"DB", 186 => X"C0", 187 => X"FE", 188 => X"78", 189 => X"CD", 190 => X"5A", 191 => X"F4",
192 => X"1F", 193 => X"DD", 194 => X"A8", 195 => X"33", 196 => X"88", 197 => X"07", 198 => X"C7", 199 => X"31",
200 => X"B1", 201 => X"12", 202 => X"10", 203 => X"59", 204 => X"27", 205 => X"80", 206 => X"EC", 207 => X"5F",
208 => X"60", 209 => X"51", 210 => X"7F", 211 => X"A9", 212 => X"19", 213 => X"B5", 214 => X"4A", 215 => X"0D",
216 => X"2D", 217 => X"E5", 218 => X"7A", 219 => X"9F", 220 => X"93", 221 => X"C9", 222 => X"9C", 223 => X"EF",
224 => X"A0", 225 => X"E0", 226 => X"3B", 227 => X"4D", 228 => X"AE", 229 => X"2A", 230 => X"F5", 231 => X"B0",
232 => X"C8", 233 => X"EB", 234 => X"BB", 235 => X"3C", 236 => X"83", 237 => X"53", 238 => X"99", 239 => X"61",
240 => X"17", 241 => X"2B", 242 => X"04", 243 => X"7E", 244 => X"BA", 245 => X"77", 246 => X"D6", 247 => X"26",
248 => X"E1", 249 => X"69", 250 => X"14", 251 => X"63", 252 => X"55", 253 => X"21", 254 => X"0C", 255 => X"7D"
);
 
 
constant encrypt_table : BYTEARRAY(0 to 255) := (
0 => X"63", 1 => X"7C", 2 => X"77", 3 => X"7B", 4 => X"F2", 5 => X"6B", 6 => X"6F", 7 => X"C5",
8 => X"30", 9 => X"01", 10 => X"67", 11 => X"2B", 12 => X"FE", 13 => X"D7", 14 => X"AB", 15 => X"76",
16 => X"CA", 17 => X"82", 18 => X"C9", 19 => X"7D", 20 => X"FA", 21 => X"59", 22 => X"47", 23 => X"F0",
24 => X"AD", 25 => X"D4", 26 => X"A2", 27 => X"AF", 28 => X"9C", 29 => X"A4", 30 => X"72", 31 => X"C0",
32 => X"B7", 33 => X"FD", 34 => X"93", 35 => X"26", 36 => X"36", 37 => X"3F", 38 => X"F7", 39 => X"CC",
40 => X"34", 41 => X"A5", 42 => X"E5", 43 => X"F1", 44 => X"71", 45 => X"D8", 46 => X"31", 47 => X"15",
48 => X"04", 49 => X"C7", 50 => X"23", 51 => X"C3", 52 => X"18", 53 => X"96", 54 => X"05", 55 => X"9A",
56 => X"07", 57 => X"12", 58 => X"80", 59 => X"E2", 60 => X"EB", 61 => X"27", 62 => X"B2", 63 => X"75",
64 => X"09", 65 => X"83", 66 => X"2C", 67 => X"1A", 68 => X"1B", 69 => X"6E", 70 => X"5A", 71 => X"A0",
72 => X"52", 73 => X"3B", 74 => X"D6", 75 => X"B3", 76 => X"29", 77 => X"E3", 78 => X"2F", 79 => X"84",
80 => X"53", 81 => X"D1", 82 => X"00", 83 => X"ED", 84 => X"20", 85 => X"FC", 86 => X"B1", 87 => X"5B",
88 => X"6A", 89 => X"CB", 90 => X"BE", 91 => X"39", 92 => X"4A", 93 => X"4C", 94 => X"58", 95 => X"CF",
96 => X"D0", 97 => X"EF", 98 => X"AA", 99 => X"FB", 100 => X"43", 101 => X"4D", 102 => X"33", 103 => X"85",
104 => X"45", 105 => X"F9", 106 => X"02", 107 => X"7F", 108 => X"50", 109 => X"3C", 110 => X"9F", 111 => X"A8",
112 => X"51", 113 => X"A3", 114 => X"40", 115 => X"8F", 116 => X"92", 117 => X"9D", 118 => X"38", 119 => X"F5",
120 => X"BC", 121 => X"B6", 122 => X"DA", 123 => X"21", 124 => X"10", 125 => X"FF", 126 => X"F3", 127 => X"D2",
128 => X"CD", 129 => X"0C", 130 => X"13", 131 => X"EC", 132 => X"5F", 133 => X"97", 134 => X"44", 135 => X"17",
136 => X"C4", 137 => X"A7", 138 => X"7E", 139 => X"3D", 140 => X"64", 141 => X"5D", 142 => X"19", 143 => X"73",
144 => X"60", 145 => X"81", 146 => X"4F", 147 => X"DC", 148 => X"22", 149 => X"2A", 150 => X"90", 151 => X"88",
152 => X"46", 153 => X"EE", 154 => X"B8", 155 => X"14", 156 => X"DE", 157 => X"5E", 158 => X"0B", 159 => X"DB",
160 => X"E0", 161 => X"32", 162 => X"3A", 163 => X"0A", 164 => X"49", 165 => X"06", 166 => X"24", 167 => X"5C",
168 => X"C2", 169 => X"D3", 170 => X"AC", 171 => X"62", 172 => X"91", 173 => X"95", 174 => X"E4", 175 => X"79",
176 => X"E7", 177 => X"C8", 178 => X"37", 179 => X"6D", 180 => X"8D", 181 => X"D5", 182 => X"4E", 183 => X"A9",
184 => X"6C", 185 => X"56", 186 => X"F4", 187 => X"EA", 188 => X"65", 189 => X"7A", 190 => X"AE", 191 => X"08",
192 => X"BA", 193 => X"78", 194 => X"25", 195 => X"2E", 196 => X"1C", 197 => X"A6", 198 => X"B4", 199 => X"C6",
200 => X"E8", 201 => X"DD", 202 => X"74", 203 => X"1F", 204 => X"4B", 205 => X"BD", 206 => X"8B", 207 => X"8A",
208 => X"70", 209 => X"3E", 210 => X"B5", 211 => X"66", 212 => X"48", 213 => X"03", 214 => X"F6", 215 => X"0E",
216 => X"61", 217 => X"35", 218 => X"57", 219 => X"B9", 220 => X"86", 221 => X"C1", 222 => X"1D", 223 => X"9E",
224 => X"E1", 225 => X"F8", 226 => X"98", 227 => X"11", 228 => X"69", 229 => X"D9", 230 => X"8E", 231 => X"94",
232 => X"9B", 233 => X"1E", 234 => X"87", 235 => X"E9", 236 => X"CE", 237 => X"55", 238 => X"28", 239 => X"DF",
240 => X"8C", 241 => X"A1", 242 => X"89", 243 => X"0D", 244 => X"BF", 245 => X"E6", 246 => X"42", 247 => X"68",
248 => X"41", 249 => X"99", 250 => X"2D", 251 => X"0F", 252 => X"B0", 253 => X"54", 254 => X"BB", 255 => X"16"
);
 
signal SBOXROM : BYTEARRAY(0 to 255); -- actual storage
begin
assign_inverse : if INVERSE generate
SBOXROM <= decrypt_table;
end generate assign_inverse;
 
assign_encrypt : if not INVERSE generate
SBOXROM <= encrypt_table;
end generate assign_encrypt;
 
 
-- purpose: lookup content of the rom
-- type : sequential
-- inputs : clk
-- outputs: q_a, q_b
assign_output : process (clk) is
begin
if rising_edge(clk) then
q_a <= SBOXROM(to_integer(UNSIGNED(address_a)));
q_b <= SBOXROM(to_integer(UNSIGNED(address_b)));
end if;
end process assign_output;
 
end ARCH1;
/VHDL/mixcol_fwd.vhd
0,0 → 1,151
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Mix the columns of the AES Block (encryption version)
-- A column is always a word of 32 Bit, nomatter what the blocklength is.
--
-- For encryption the input vector is multiplied by this matrix
--
-- | 2 3 1 1 | a(n,0)
-- | 1 2 3 1 | x a(n,1)
-- | 1 1 2 3 | a(n,2)
-- | 3 1 1 2 | a(n,3)
--
-- where the multiplication is defined over the GF(2^8) Galois field.
-- in this finite field addition is an XOR, multiplication by 2 is a simple
-- shift left like in "normal" math. So the multiplication by 3 is a shiftleft
-- and XOR operation.
-- 2*a = a shl 2
-- 3*a = (a shl 2) XOR a
-- If bit leftmost (MSB) bit is '1' the result is too big to fit in a Byte and
-- has to be XORed with the magic number "100_0110_1100", "10_0011_0110",
-- "1_0001_1011" sucessively until it fits... don't ask me where it
-- comes from - I have no clue and skipped the gory math details of the algorithm.
-- the most is taken from: http://en.wikipedia.org/wiki/Rijndael_Galois_field
-- Or you ask the mathematician of at your disposal...
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
 
 
 
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
 
architecture fwd of mixcol
is
signal byte0 : BYTE;
signal byte1 : BYTE;
signal byte2 : BYTE;
signal byte3 : BYTE;
begin -- architecture ARCH1
 
-- Easier handling of the single cells of the column
byte0 <= col_in(31 downto 24);
byte1 <= col_in(23 downto 16);
byte2 <= col_in(15 downto 8);
byte3 <= col_in(7 downto 0);
 
-- purpose: multiplies the column of the input block with the matrix
-- type : combinational
-- inputs : direction,byte0,byte1,byte2,byte3
-- outputs: col_out
matrix_mult : process (byte0, byte1, byte2, byte3) is
-- temporary results for the row-col multiplication have to be 9 Bits
-- long because the input is shifted left
variable tmp_res0 : STD_LOGIC_VECTOR(10 downto 0); -- result of row1*col
variable tmp_res1 : STD_LOGIC_VECTOR(10 downto 0); -- result of row2*col
variable tmp_res2 : STD_LOGIC_VECTOR(10 downto 0); -- result of row3*col
variable tmp_res3 : STD_LOGIC_VECTOR(10 downto 0); -- result of row4*col
begin -- process matrix_mult
-- Multiply by 1st row of the encrypt matrix (2 3 1 1)
tmp_res0 := "00" & (byte0 & '0' xor -- byte0*2 +
byte1 & '0' xor '0'& byte1 xor -- byte1*2 + byte1 +
'0' & byte2 xor -- byte2*1 (expanded to 9 bit)
'0' & byte3); -- byte3*1 (expanded to 9 bit)
-- check if the 9th byte=1 and XOR with magic number to make it 8 BIT
if tmp_res0(8) = '1' then
tmp_res0 := tmp_res0 xor "00100011011";
end if;
 
-- Multiply by 2nd row of the encrypt matrix (1 2 3 1)
tmp_res1 := "00" & ('0' & byte0 xor -- byte0*1 (expanded to 9 bit)
byte1 & '0' xor -- byte1*2
byte2 & '0' xor '0' & byte2 xor -- byte2*2 + byte2
'0' & byte3); -- byte3*1 (expanded to 9 bit)
-- check if the 9th byte=1 and XOR with magic number to make it 8 BIT
if tmp_res1(8) = '1' then
tmp_res1 := tmp_res1 xor "00100011011";
end if;
 
-- Multiply by 3rd row of the encrypt matrix (1 1 2 3)
tmp_res2 := "00" & ('0' & byte0 xor -- byte0*1 (expanded to 9 bit)
'0' & byte1 xor -- byte1*1 (expanded to 9 bit)
byte2 & '0' xor -- byte2*3
byte3 & '0' xor '0' & byte3); -- byte3*3
-- check if the 9th byte=1 and XOR with magic number to make it 8 BIT
if tmp_res2(8) = '1' then
tmp_res2 := tmp_res2 xor "00100011011";
end if;
 
-- Multiply by 4th row of the encrypt matrix (3 1 1 2)
tmp_res3 := "00" & (byte0 & '0' xor '0' & byte0 xor -- byte0*3
'0' & byte1 xor -- byte1*1 (expanded to 9 bit)
'0' & byte2 xor -- byte2*1 (expanded to 9 bit)
byte3 & '0'); -- byte3*2
-- check if the 9th byte=1 and XOR with magic number to make it 8 BIT
if tmp_res3(8) = '1' then
tmp_res3 := tmp_res3 xor "00100011011";
end if;
 
 
-- build output signal (BYTE_RANGE =7 downto 0 see util_pkg.vhd)
col_out(31 downto 24) <= tmp_res0(BYTE_RANGE);
col_out(23 downto 16) <= tmp_res1(BYTE_RANGE);
col_out(15 downto 8) <= tmp_res2(BYTE_RANGE);
col_out(7 downto 0) <= tmp_res3(BYTE_RANGE);
end process matrix_mult;
 
end architecture fwd;
 
/VHDL/mixcol.vhd
0,0 → 1,60
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- This is only the entity to the architectures fwd and INV of mixcolumn as
-- they have the same interface
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
library avs_aes_lib;
use avs_aes_lib.avs_aes_pkg.all;
 
entity Mixcol is
port (
col_in : in DWORD; -- one column of the state
col_out : out DWORD -- output column
);
end entity Mixcol;
 
/VHDL/memory_word.vhd
0,0 → 1,80
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description: Register - nothing special
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity memory_word is
generic (
IOwidth : POSITIVE := 1); -- width in bits
port (
data_in : in STD_LOGIC_VECTOR(IOwidth-1 downto 0);
data_out : out STD_LOGIC_VECTOR(IOwidth-1 downto 0);
res_n : in STD_LOGIC; -- system reset active low
ena : in STD_LOGIC; -- enable write
clk : in STD_LOGIC); -- system clock
end entity memory_word;
 
architecture arch1 of memory_word is
signal data : STD_LOGIC_VECTOR(IOwidth-1 downto 0); -- storage
begin -- architecture arch1
 
-- purpose: write data to register at clock edge if enabled
-- type : sequential
-- inputs : clk, res_n, data_in,ena
write_mem : process (clk, res_n) is
begin -- process write_mem
if res_n = '0' then
data <= (others => '0');
elsif rising_edge(clk) then
if ena = '1' then
data <= data_in;
end if;
end if;
end process write_mem;
 
-- data can always be read
data_out <= data;
end architecture arch1;
/VHDL/sbox.vhd
0,0 → 1,69
------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description:
-- Sbox implements a lookup ROM for nonlinear substitution of a Bytearray.
-- This is only the entity for either arch1 (which is pure VHDL) or M4K which
-- is an Altera M4K-Blockram implementation.
--
-------------------------------------------------------------------------------!
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
 
-------------------------------------------------------------------------------
-- The interface is 2x8Bit because Altera megafunction is supposed to be at max
-- 8Bit dual port ROM (and I relied on a altera quartus generated component
-- before) see architecture m4k
-------------------------------------------------------------------------------
entity sbox is
generic (
INVERSE : BOOLEAN := false -- is this the inverse or the forward
-- lookup table.
-- TRUE -> inverse sbox
-- FALSE -> forward sbox
);
port(
clk : in STD_LOGIC; -- system clock
address_a : in STD_LOGIC_VECTOR (7 downto 0); -- 1st byte
address_b : in STD_LOGIC_VECTOR (7 downto 0); -- 2nd byte
q_a : out STD_LOGIC_VECTOR (7 downto 0); -- substituted 1st byte
q_b : out STD_LOGIC_VECTOR (7 downto 0) -- substituted 2nd byte
);
end sbox;
 
/VHDL/mux2.vhd
0,0 → 1,85
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description: Mux2, 2-Port-N-Bit Bit Mulitplexer
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
 
entity mux2 is
generic (
IOwidth : POSITIVE := 32 -- width of I/O ports
);
port (
inport_a : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 1
inport_b : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 2
selector : in STD_LOGIC; -- switch to select ports
outport : out STD_LOGIC_VECTOR (IOwidth-1 downto 0) -- output
);
end mux2;
 
 
architecture arch1 of mux2 is
 
begin -- arch1
 
-- purpose: switch the ports
-- type : combinational
-- inputs : selector,inport_a,inport_b
-- outputs: outport
muxing : process (inport_a, inport_b, selector)
begin -- PROCESS selector
-- default behaviour to avoid latch
outport <= inport_a;
case selector is
when '0' =>
outport <= inport_a;
when '1' =>
outport <= inport_b;
when others =>
--pragma synthesis_off
report "!! selector in arch1 of mux2 has strange value !!" severity warning;
--pragma synthesis_on
end case;
end process muxing;
 
end arch1;
/VHDL/mux3.vhd
0,0 → 1,86
--------------------------------------------------------------------------------
-- This file is part of the project avs_aes
-- see: http://opencores.org/project,avs_aes
--
-- description: Mux2, 3-Port-N-Bit Bit Mulitplexer
--
-------------------------------------------------------------------------------
--
-- Author(s):
-- Thomas Ruschival -- ruschi@opencores.org (www.ruschival.de)
--
--------------------------------------------------------------------------------
-- Copyright (c) 2009, Authors and opencores.org
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- * Neither the name of the organization nor the names of its contributors
-- may be used to endorse or promote products derived from this software without
-- specific prior written permission.
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
-- OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-- THE POSSIBILITY OF SUCH DAMAGE
-------------------------------------------------------------------------------
-- version management:
-- $Author$
-- $Date$
-- $Revision$
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity mux3 is
generic (
IOwidth : POSITIVE := 1 -- width of I/O ports
);
port (
inport_a : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 1
inport_b : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 2
inport_c : in STD_LOGIC_VECTOR (IOwidth-1 downto 0); -- port 3
selector : in STD_LOGIC_VECTOR (1 downto 0);-- switch to select ports
outport : out STD_LOGIC_VECTOR (IOwidth-1 downto 0) -- output
);
end mux3;
 
 
architecture arch1 of mux3 is
 
begin -- arch1
 
-- purpose: switch the ports
-- type : combinational
-- inputs : selector,inport_a,inport_b
-- outputs: outport
muxing : process (inport_a, inport_b, inport_c, selector)
begin -- PROCESS selector
case selector is
when "00" =>
outport <= inport_a;
when "01" =>
outport <= inport_b;
when "10" =>
outport <= inport_c;
when others =>
outport <= (others => 'X');
--pragma synthesis_off
report "!! selector in arch1 of mux3 has strange value !!" severity warning;
--pragma synthesis_on
end case;
end process muxing;
 
end arch1;
/VHDL/sbox.hex
0,0 → 1,257
:01000000639C
:010001007C82
:010002007786
:010003007B81
:01000400F209
:010005006B8F
:010006006F8A
:01000700C533
:0100080030C7
:0100090001F5
:01000A00678E
:01000B002BC9
:01000C00FEF5
:01000D00D71B
:01000E00AB46
:01000F00767A
:01001000CA25
:01001100826C
:01001200C924
:010013007D6F
:01001400FAF1
:010015005991
:0100160047A2
:01001700F0F8
:01001800AD3A
:01001900D412
:01001A00A243
:01001B00AF35
:01001C009C47
:01001D00A43E
:01001E00726F
:01001F00C020
:01002000B728
:01002100FDE1
:01002200934A
:0100230026B6
:0100240036A5
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/VHDL/sbox_inv.hex
0,0 → 1,257
:0100000052AD
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