URL
https://opencores.org/ocsvn/ax4lbr/ax4lbr/trunk
Subversion Repositories ax4lbr
Compare Revisions
- This comparison shows the changes necessary to convert path
/ax4lbr
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/trunk/rtl/axil2wb.vhd
81,6 → 81,9
S_AXI_BRESP : out std_logic_vector(1 downto 0); |
S_AXI_BVALID : out std_logic; |
S_AXI_BREADY : in std_logic; |
-- AWPROT and ARPROT - required by Altera |
--S_AXI_ARPROT : in std_logic_vector(2 downto 0); |
--S_AXI_AWPROT : in std_logic_vector(2 downto 0); |
-- Here we have the WB ports |
-- The clock and reset are comming from AXI! |
wb_clk_o : out std_logic; |
/trunk/rtl/axil2ipb.vhd
86,6 → 86,9
S_AXI_BRESP : out std_logic_vector(1 downto 0); |
S_AXI_BVALID : out std_logic; |
S_AXI_BREADY : in std_logic; |
-- AWPROT and ARPROT - required by Altera |
--S_AXI_ARPROT : in std_logic_vector(2 downto 0); |
--S_AXI_AWPROT : in std_logic_vector(2 downto 0); |
-- Here we have the IPbus ports |
ipb_clk : out std_logic; |
ipb_rst : out std_logic; |