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    /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
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Rev 25 → Rev 42

/tester.vhdl
34,7 → 34,7
Public License along with this source; if not, download it
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all, ieee.math_real.all;
--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
 
/* TODO remove once generic packages are supported. */
41,7 → 41,7
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
 
/* synthesis translate_off */
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
library osvvm; use osvvm.RandomPkg.all, osvvm.CoveragePkg.all;
/* synthesis translate_on */
 
library altera; use altera.stp;
63,8 → 63,7
irq_write:buffer std_ulogic; -- clock gating.
symbolsPerTransfer:buffer t_cnt;
outstandingTransactions:buffer t_cnt;
lastTransaction:buffer boolean;
/* Debug ports. */
-- dataIn:in t_msg;
71,314 → 70,3
selTxn:in unsigned(3 downto 0)
);
end entity tester;
 
architecture rtl of tester is
-- signal reset:std_ulogic:='0';
signal locked:std_ulogic;
signal porCnt:unsigned(3 downto 0);
signal trigger:boolean;
/* Global counters. */
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
-- signal symbolsPerTransfer:t_cnt;
-- signal outstandingTransactions:t_cnt;
-- /* BFM signalling. */
-- signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
-- signal readResponse,writeResponse:t_bfm;
type txStates is (idle,transmitting);
signal txFSM,i_txFSM:txStates;
/* Tester signals. */
/* synthesis translate_off */
signal clk,nReset:std_ulogic:='0';
attribute period:time; attribute period of clk:signal is 10 ps;
/* synthesis translate_on */
signal testerClk:std_ulogic;
signal dbg_axiTxFSM:axiBfmStatesTx;
signal anlysr_dataIn:std_logic_vector(127 downto 0);
signal anlysr_trigger:std_ulogic;
-- signal axiMaster_in:t_axi4StreamTransactor_s2m;
-- signal irq_write:std_ulogic; -- clock gating.
signal prbs:t_msg;
begin
/* PLL to generate tester's clock. */
f100MHz: entity altera.pll(syn) port map(
areset=>'0', --not nReset,
inclk0=>clk,
c0=>testerClk,
locked=>locked
);
/* Interrupt-request generator. */
trigger<=txFSM/=i_txFSM or writeResponse.trigger;
irq_write<=clk when not reset else '0';
/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
--anlysr_trigger<='1' when writeRequest.trigger else '0';
anlysr_trigger<='1' when reset else '0';
/* Disable this for synthesis as this is not currently synthesisable.
Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
*/
/* synthesis translate_off */
--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
/* synthesis translate_on */
anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
anlysr_dataIn(18)<='1' when clk else '0';
anlysr_dataIn(19)<='1' when reset else '0';
anlysr_dataIn(20)<='1' when irq_write else '0';
anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData);
anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs);
anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt);
-- anlysr_dataIn(102)<='1' when locked else '0';
-- anlysr_dataIn(102)<=locked;
anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0');
/* Simulate only if you have compiled Altera's simulation libraries. */
i_bist_logicAnalyser: entity altera.stp(syn) port map(
acq_clk=>testerClk,
acq_data_in=>anlysr_dataIn,
acq_trigger_in=>"1",
trigger_in=>anlysr_trigger
);
/* Stimuli sequencer. TODO move to tester/stimuli.
This emulates the AXI4-Stream Slave.
*/
/* Simulation-only stimuli sequencer. */
/* synthesis translate_off */
process is begin
report "Performing fast read..." severity note;
/* Fast read. */
while not axiMaster_out.tLast loop
/* Wait for tValid to assert. */
while not axiMaster_out.tValid loop
wait until falling_edge(clk);
end loop;
axiMaster_in.tReady<=true;
wait until falling_edge(clk);
axiMaster_in.tReady<=false;
end loop;
wait until falling_edge(clk);
report "Performing normal read..." severity note;
/* Normal read. */
while not axiMaster_out.tLast loop
/* Wait for tValid to assert. */
while not axiMaster_out.tValid loop
wait until falling_edge(clk);
end loop;
wait until falling_edge(clk);
wait until falling_edge(clk);
axiMaster_in.tReady<=true;
wait until falling_edge(clk);
axiMaster_in.tReady<=false;
wait until falling_edge(clk);
end loop;
report "Completed normal read." severity note;
for i in 0 to 10 loop
wait until falling_edge(clk);
end loop;
/* One-shot read. */
axiMaster_in.tReady<=true;
wait until falling_edge(clk);
axiMaster_in.tReady<=false;
report "Completed one-shot read." severity note;
wait;
end process;
/* synthesis translate_on */
/* Synthesisable stimuli sequencer. */
process(clk) is begin
if falling_edge(clk) then
axiMaster_in.tReady<=false;
--if axiMaster_out.tValid and not axiMaster_out.tLast then
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
axiMaster_in.tReady<=true;
end if;
end if;
end process;
/* Data transmitter. */
i_prbs: entity tauhop.prbs31(rtl)
generic map(
isParallelLoad=>true,
tapVector=>(
/* Example polynomial from Wikipedia:
http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
*/
0|3|31=>true, 1|2|30 downto 4=>false
)
)
port map(
/* Comment-out for simulation. */
clk=>irq_write, reset=>reset,
en=>trigger,
seed=>32x"ace1", --9x"57",
prbs=>prbs
);
sequencer_ns: process(all) is begin
txFSM<=i_txFSM;
if reset then txFSM<=idle;
else
case i_txFSM is
when idle=>
if outstandingTransactions>0 then txFSM<=transmitting; end if;
when transmitting=>
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=> null;
end case;
end if;
end process sequencer_ns;
sequencer_op: process(reset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in t_addr) is begin
read(readRequest,address);
end procedure read;
procedure write(data:in t_msg) is begin
write(request=>writeRequest, address=>(others=>'-'), data=>data);
end procedure write;
variable isPktError:boolean;
/* Tester variables. */
/* Synthesis-only randomisation. */
/* Simulation-only randomisation. */
/* synthesis translate_off */
variable rv0:RandomPType;
/* synthesis translate_on */
-- variable trigger:boolean;
begin
-- if reset then
/* simulation only. */
/* synthesis translate_off */
-- rv0.InitSeed(rv0'instance_name);
/* synthesis translate_on */
if falling_edge(irq_write) then
case txFSM is
when transmitting=>
if trigger then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
--write(prbs);
case selTxn is
when x"1"=> write(32x"12ab34cd");
when x"2"=> write(32x"12345678");
when x"3"=> write(32x"87654321");
when x"4"=> write(32x"abcd1234");
when others=> write(prbs);
end case;
end if;
when others=>null;
end case;
end if;
end process sequencer_op;
sequencer_regs: process(irq_write) is begin
if falling_edge(irq_write) then
i_txFSM<=txFSM;
end if;
end process sequencer_regs;
/* Transaction counter. */
process(reset,symbolsPerTransfer,irq_write) is begin
/* TODO close timing for asynchronous reset. */
if reset then outstandingTransactions<=symbolsPerTransfer;
elsif rising_edge(irq_write) then
if not axiMaster_out.tLast then
if outstandingTransactions<1 then
outstandingTransactions<=symbolsPerTransfer;
report "No more pending transactions." severity note;
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
if reset then outstandingTransactions<=symbolsPerTransfer; end if;
end if;
end process;
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
process(reset,irq_write) is
/* synthesis translate_off */
variable rv0:RandomPType;
/* synthesis translate_on */
begin
if reset then
/* synthesis translate_off */
rv0.InitSeed(rv0'instance_name);
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
/* synthesis translate_on */
symbolsPerTransfer<=128x"fc";
elsif rising_edge(irq_write) then
if axiMaster_out.tLast then
/* synthesis only. */
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
--symbolsPerTransfer<=(others=>'0');
/* Testcase 2: number of symbols per transfer is randomised. */
--uniform(seed0,seed1,rand0);
--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
/* synthesis translate_off */
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
/* synthesis translate_on */
symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
end if;
end if;
end process;
 
-- outstandingTransactions<=128x"fc"; --symbolsPerTransfer;
end architecture rtl;
/axi4-stream-bfm-master.vhdl
55,8 → 55,7
-- axiSlave_in:in tAxi4Transactor_m2s;
-- axiSlave_out:buffer tAxi4Transactor_s2m;
symbolsPerTransfer:in t_cnt;
outstandingTransactions:in t_cnt;
lastTransaction:in boolean;
/* Debug ports. */
-- dbg_cnt:out unsigned(9 downto 0);
91,7 → 90,7
when idle=>
if i_trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
if lastTransaction then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
103,26 → 102,30
axi_bfmTx_op: process(all) is begin
i_writeResponse<=writeResponse;
i_axiMaster_out.tValid<=false;
i_axiMaster_out<=axiMaster_out;
i_axiMaster_out.tLast<=false;
i_axiMaster_out.tData<=(others=>'Z');
i_writeResponse.trigger<=false;
case next_axiTxState is
when idle=>
i_axiMaster_out.tValid<=false;
i_axiMaster_out.tData<=(others=>'Z');
if i_trigger then
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
end if;
when payload=>
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
when payload | endOfTx =>
if i_trigger then
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
end if;
if axiMaster_in.tReady then
i_writeResponse.trigger<=true;
end if;
if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
if lastTransaction then i_axiMaster_out.tLast<=true; end if;
when others=> null;
end case;
end process axi_bfmTx_op;
/user.vhdl
49,14 → 49,14
 
entity user is port(
/* Comment-out for simulation. */
clk,reset:in std_ulogic;
clk,nReset:in std_ulogic;
/* AXI Master interface */
-- axiMaster_in:in t_axi4StreamTransactor_s2m;
axiMaster_out:buffer t_axi4StreamTransactor_m2s;
axiMaster_out:buffer t_axi4StreamTransactor_m2s
/* Debug ports. */
selTxn:in unsigned(3 downto 0):=x"0"
-- selTxn:in unsigned(3 downto 0):=x"5" -- select PRBS by default.
);
end entity user;
 
66,9 → 66,9
/* Global counters. */
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
signal symbolsPerTransfer:t_cnt;
signal outstandingTransactions:t_cnt;
signal lastTransaction:boolean;
/* BFM signalling. */
signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
signal readResponse,writeResponse:t_bfm;
75,7 → 75,7
/* Tester signals. */
/* synthesis translate_off */
signal clk,reset:std_ulogic:='0';
signal clk,nReset:std_ulogic:='0';
attribute period:time; attribute period of clk:signal is 10 ps;
/* synthesis translate_on */
86,6 → 86,8
signal axiMaster_in:t_axi4StreamTransactor_s2m;
signal irq_write:std_ulogic; -- clock gating.
signal selTxn:unsigned(3 downto 0):=4x"0"; -- select PRBS by default.
begin
/* Bus functional models. */
axiMaster: entity tauhop.axiBfmMaster(rtl)
97,15 → 99,14
axiMaster_in=>axiMaster_in,
axiMaster_out=>axiMaster_out,
symbolsPerTransfer=>symbolsPerTransfer,
outstandingTransactions=>outstandingTransactions,
lastTransaction=>lastTransaction,
dbg_axiTxFSM=>dbg_axiTxFSM
);
/* Clocks and reset. */
/* Power-on Reset circuitry. */
por: process(reset,clk) is begin
if reset then i_reset<='1'; porCnt<=(others=>'1');
por: process(nReset,clk) is begin
if not nReset then i_reset<='1'; porCnt<=(others=>'1');
elsif rising_edge(clk) then
i_reset<='0';
116,9 → 117,9
/* synthesis translate_off */
clk<=not clk after clk'period/2;
process is begin
reset<='0'; wait for 1 ps;
reset<='1'; wait for 500 ps;
reset<='0';
nReset<='0'; wait for 1 ps;
nReset<='1'; wait for 500 ps;
nReset<='0';
wait;
end process;
/* synthesis translate_on */
126,7 → 127,7
/* Simulation Tester. */
/* Hardware tester. */
bist: entity work.tester(rtl) port map(
bist: entity work.tester(cdcrv) port map(
clk=>clk, reset=>i_reset,
axiMaster_in=>axiMaster_in,
axiMaster_out=>axiMaster_out,
133,8 → 134,7
readRequest=>readRequest, writeRequest=>writeRequest,
readResponse=>readResponse, writeResponse=>writeResponse,
irq_write=>irq_write,
symbolsPerTransfer=>symbolsPerTransfer,
outstandingTransactions=>outstandingTransactions,
lastTransaction=>lastTransaction,
selTxn=>selTxn
);
end architecture rtl;

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