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Subversion Repositories axi4_tlm_bfm

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  • This comparison shows the changes necessary to convert path 
    /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
    from Rev 42 to Rev 44
    ↔ Reverse comparison
  •

Rev 42 → Rev 44

/axi4-stream-bfm-master.vhdl
39,7 → 39,7
--library tauhop; use tauhop.axiTransactor.all;
 
/* TODO remove once generic packages are supported. */
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
library tauhop; use tauhop.fsm.all, tauhop.tlm.all, tauhop.axiTLM.all;
 
entity axiBfmMaster is
port(aclk,n_areset:in std_ulogic;
67,7 → 67,7
architecture rtl of axiBfmMaster is
/* Finite-state Machines. */
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
 
signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
signal i_trigger,trigger:boolean;
77,6 → 77,13
signal i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
signal i_writeResponse:t_bfm;
/* DDR Pipelines. */
signal next_axiTxState_rise,next_axiTxState_fall:axiBfmStatesTx;
signal i_writeRequest_rise,i_writeRequest_fall:t_bfm;
signal writeResponse_rise,writeResponse_fall:t_bfm;
signal axiMaster_out_rise,axiMaster_out_fall:t_axi4StreamTransactor_m2s;
signal trigger_rise,trigger_fall:boolean;
begin
i_trigger<=writeRequest.trigger xor i_writeRequest.trigger;
92,7 → 99,7
when payload=>
if lastTransaction then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
if axiMaster_in.tReady then axiTxState<=idle; end if;
when others=>axiTxState<=idle;
end case;
end if;
132,7 → 139,19
/* state registers and pipelines for AXI4-Stream Tx BFM. */
process(aclk) is begin
if falling_edge(aclk) then
if not n_areset then
next_axiTxState<=idle;
i_writeRequest<=(address=>(others=>'0'),message=>(others=>'0'),trigger=>false);
writeResponse<=(address=>(others=>'0'),message=>(others=>'0'),trigger=>false);
--axiMaster_out<=(others=>'0');
trigger<=false;
-- elsif rising_edge(aclk) then
-- next_axiTxState<=axiTxState;
-- i_writeRequest<=writeRequest;
-- writeResponse<=i_writeResponse;
-- axiMaster_out<=i_axiMaster_out;
-- trigger<=i_trigger;
elsif falling_edge(aclk) then
next_axiTxState<=axiTxState;
i_writeRequest<=writeRequest;
writeResponse<=i_writeResponse;
141,5 → 160,101
end if;
end process;
/*
process(n_areset,aclk) is begin
if not n_areset then
next_axiTxState_rise<=idle;
elsif rising_edge(aclk) then
next_axiTxState_rise<=axiTxState;
i_writeRequest_rise<=writeRequest;
writeResponse_rise<=i_writeResponse;
axiMaster_out_rise<=i_axiMaster_out;
trigger_rise<=i_trigger;
end if;
end process;
process(n_areset,aclk) is begin
if not n_areset then
next_axiTxState_fall<=idle;
elsif falling_edge(aclk) then
next_axiTxState_fall<=axiTxState;
i_writeRequest_fall<=writeRequest;
writeResponse_fall<=i_writeResponse;
axiMaster_out_fall<=i_axiMaster_out;
trigger_fall<=i_trigger;
end if;
end process;
next_axiTxState<=idle when not n_areset else next_axiTxState_rise xor next_axiTxState_fall;
*/
-- pseudo dual-edge-triggered D-Flip-Flop (Refer Ralf Hildebrant's paper: http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf).
/*
process(async_clr,clk)
begin
if impl_rp=0 and async_clr='0' then ff_rise<='0';
elsif impl_rp=1 and async_clr='0' then ff_rise<='1';
elsif rising_edge(clk) then
if d='1' then ff_rise<=not ff_fall;
else ff_rise<=ff_fall;
end if;
end if;
end process;
process(async_clr,clk)
begin
if impl_rp=0 and async_clr='0' then ff_fall<='0';
elsif impl_rp=1 and async_clr='0' then ff_fall<='1';
elsif falling_edge(clk) then
if d='1' then ff_fall<=not ff_rise;
else ff_fall<=ff_rise;
end if;
end if;
end process;
q<='0' when impl_rp=0 and async_clr='0' else
'1' when impl_rp=1 and async_clr='0' else
ff_rise xor ff_fall;
*/
-- end pseudo dual-edge-triggered DFF
/*
-- process(n_areset,aclk) is
process(aclk) is
-- variable q1,q2:std_ulogic_vector(q'length-1 downto 0);
variable q_a1,q_a2:axiBfmStatesTx; --std_ulogic_vector(axiTxState'range);
variable q_b1,q_b2:t_bfm; --std_ulogic_vector(writeRequest'range);
variable q_c1,q_c2:t_bfm;
variable q_d1,q_d2:t_axi4StreamTransactor_m2s;
variable q_e1,q_e2:boolean;
begin
-- if not n_areset then
-- q_a1:=idle; q_a2:=idle;
-- q_b1:=(others=>'0'); q_b2:=(others=>'0');
-- q_c1:=(others=>'0'); q_c2:=(others=>'0');
-- q_d1:=(others=>'0'); q_d2:=(others=>'0');
-- q_e1:=(others=>'0'); q_e2:=(others=>'0');
if rising_edge(aclk) then
q_a1:=axiTxState xor q_a2;
q_b1:=writeRequest xor q_b2;
q_c1:=i_writeResponse xor q_c2;
q_d1:=i_axiMaster_out xor q_d2;
q_e1:=i_trigger xor q_e2;
elsif falling_edge(aclk) then
q_a2:=axiTxState xor q_a1;
q_b2:=writeRequest xor q_b1;
q_c2:=i_writeResponse xor q_c1;
q_d2:=i_axiMaster_out xor q_d1;
q_e2:=i_trigger xor q_e1;
end if;
next_axiTxState<=q_a1 xor q_a2;
i_writeRequest<=q_b1 xor q_b2;
writeResponse<=q_c1 xor q_c2;
axiMaster_out<=q_d1 xor q_d2;
trigger<=q_e1 xor q_e2;
end process;
*/
dbg_axiTxFSM<=axiTxState;
end architecture rtl;
/pkg-axi-tlm.vhdl
2,7 → 2,7
This file is part of the AXI4 Transactor and Bus Functional Model
(axi4_tlm_bfm) project:
http://www.opencores.org/project,axi4_tlm_bfm
 
Description
Implementation of AXI4 transactor data structures and high-level API.
159,29 → 159,9
-- cSysAck:
-- cActive:
-- end record tAxiTransactor_lp;
type t_fsm is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
type axiBfmStatesTx is (idle,payload,endOfTx);
type axiBfmStatesRx is (idle,checkAddr,startOfPacket,payload);
attribute enum_encoding:string;
attribute enum_encoding of axiBfmStatesTx:type is "00 01 10";
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector;
end package axiTLM;
 
package body axiTLM is
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector is
variable r:std_logic_vector(1 downto 0);
begin
case fsm is
when idle=> r:=2x"0";
when payload=> r:=2x"1";
when endOfTx=> r:=2x"2";
when others=> null;
end case;
return r;
end function to_std_logic_vector;
end package body axiTLM;
 
 
/user.vhdl
38,7 → 38,7
--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
 
/* TODO remove once generic packages are supported. */
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
library tauhop; use tauhop.fsm.all, tauhop.tlm.all, tauhop.axiTLM.all;
 
/* synthesis translate_off */
library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
86,7 → 86,8
signal axiMaster_in:t_axi4StreamTransactor_s2m;
signal irq_write:std_ulogic; -- clock gating.
signal selTxn:unsigned(3 downto 0):=4x"0"; -- select PRBS by default.
signal selTxn:unsigned(3 downto 0):=4x"5"; -- select PRBS by default.
--signal selTxn:unsigned(3 downto 0):=4x"0";
begin
/* Bus functional models. */
117,9 → 118,9
/* synthesis translate_off */
clk<=not clk after clk'period/2;
process is begin
nReset<='0'; wait for 1 ps;
nReset<='1'; wait for 500 ps;
nReset<='0';
nReset<='1'; wait for 1 ps;
nReset<='0'; wait for 500 ps;
nReset<='1';
wait;
end process;
/* synthesis translate_on */

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