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Subversion Repositories axi4_tlm_bfm

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    /axi4_tlm_bfm/trunk/rtl
    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/axi4-stream-bfm-master.vhdl
71,6 → 71,8
/* Finite-state Machines. */
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
/* BFM signalling. */
signal i_readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
88,6 → 90,19
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
/* debug only. */
/*if falling_edge(aclk) then
if not n_areset then outstandingTransactions<=symbolsPerTransfer;
else
if outstandingTransactions<1 then
outstandingTransactions<=symbolsPerTransfer;
report "No more pending transactions." severity note;
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
end if;
*/
end process;
/* next-state logic for AXI4-Stream Master Tx BFM. */
94,17 → 109,18
axi_bfmTx_ns: process(all) is begin
axiTxState<=next_axiTxState;
if not n_areset then axiTxState<=idle; end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
if not n_areset then axiTxState<=idle;
else
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
end if;
end process axi_bfmTx_ns;
/* output logic for AXI4-Stream Master Tx BFM. */
111,20 → 127,27
axi_bfmTx_op: process(all) is begin
i_writeResponse<=writeResponse;
axiMaster_out.tValid<=false;
axiMaster_out.tLast<=false;
axiMaster_out.tData<=(others=>'Z');
i_axiMaster_out.tValid<=false;
i_axiMaster_out.tLast<=false;
i_axiMaster_out.tData<=(others=>'Z');
i_writeResponse.trigger<=false;
if writeRequest.trigger xor i_writeRequest.trigger then
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
/* if writeRequest.trigger xor i_writeRequest.trigger then
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
end if;
*/
null;
when payload=>
axiMaster_out.tValid<=true;
axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
if axiMaster_in.tReady then
i_writeResponse.trigger<=true;
131,18 → 154,20
end if;
/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
when others=> null;
end case;
end process axi_bfmTx_op;
axiMaster_out<=i_axiMaster_out;
/* state registers and pipelines for AXI4-Stream Tx BFM. */
process(n_areset,aclk) is begin
if not n_areset then next_axiTxState<=idle;
elsif falling_edge(aclk) then
--if not n_areset then next_axiTxState<=idle;
if falling_edge(aclk) then
next_axiTxState<=axiTxState;
i_writeRequest<=writeRequest;
--axiMaster_out<=i_axiMaster_out;
end if;
end process;
/user.vhdl
164,7 → 164,23
/* Data transmitter. */
sequencer: process(nReset,irq_write) is
sequencer_ns: process(all) is begin
txFSM<=i_txFSM;
if not nReset then txFSM<=idle;
else
case i_txFSM is
when idle=>
if outstandingTransactions>0 then txFSM<=transmitting; end if;
when transmitting=>
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=> null;
end case;
end if;
end process sequencer_ns;
sequencer_op: process(nReset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in i_transactor.t_addr) is begin
i_transactor.read(readRequest,address);
190,32 → 206,25
/* synthesis translate_off */
rv0.InitSeed(rv0'instance_name);
/* synthesis translate_on */
txFSM<=idle;
elsif falling_edge(irq_write) then
case txFSM is
when idle=>
if outstandingTransactions>0 then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
txFSM<=transmitting;
end if;
when transmitting=>
if writeResponse.trigger then
if txFSM/=i_txFSM or writeResponse.trigger then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
end if;
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=>null;
end case;
end if;
end process sequencer;
end process sequencer_op;
sequencer_regs: process(irq_write) is begin
if falling_edge(irq_write) then
i_txFSM<=txFSM;
end if;
end process sequencer_regs;
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
process(nReset,irq_write) is
/* synthesis translate_off */
/quartus-synthesis/axi4-stream-bfm-master.vhdl
36,15 → 36,15
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;
--library tauhop; use tauhop.axiTransactor.all;
 
--/* TODO remove once generic packages are supported. */
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
 
entity axiBfmMaster is --generic(constant maxTransactions:positive);
entity axiBfmMaster is
port(aclk,n_areset:in std_ulogic;
/* BFM signalling. */
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false); -- this is tauhop.transactor.t_bfm.
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false);
readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
/* AXI Master interface */
56,12 → 56,12
-- axiSlave_out:buffer tAxi4Transactor_s2m;
symbolsPerTransfer:in t_cnt;
outstandingTransactions:buffer t_cnt
outstandingTransactions:buffer t_cnt;
/* Debug ports. */
-- dbg_cnt:out unsigned(9 downto 0);
-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
-- dbg_axiTxFsm:out axiBfmStatesTx:=idle
dbg_axiTxFsm:out axiBfmStatesTx:=idle
);
end entity axiBfmMaster;
 
78,6 → 78,11
begin
/* Transaction counter. */
process(n_areset,symbolsPerTransfer,aclk) is begin
/* Using synchronous reset will meet timing. However, because outstandingTransactions is a huge
register set, using asynchronous reset will violate timing.
FIXME Try and close timing even with asynchronous reset applied on outstandingTransactions.
Using asynchronous reset will help to lower power.
*/
if not n_areset then outstandingTransactions<=symbolsPerTransfer;
elsif falling_edge(aclk) then
if outstandingTransactions<1 then
92,17 → 97,18
axi_bfmTx_ns: process(all) is begin
axiTxState<=next_axiTxState;
if not n_areset then axiTxState<=idle; end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
if not n_areset then axiTxState<=idle;
else
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
end if;
end process axi_bfmTx_ns;
/* output logic for AXI4-Stream Master Tx BFM. */
114,15 → 120,15
axiMaster_out.tData<=(others=>'Z');
i_writeResponse.trigger<=false;
if writeRequest.trigger xor i_writeRequest.trigger then
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
end if;
when payload=>
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
axiMaster_out.tData<=writeRequest.message;
if axiMaster_in.tReady then
i_writeResponse.trigger<=true;
134,11 → 140,9
end case;
end process axi_bfmTx_op;
/* state registers and pipelines for AXI4-Stream Tx BFM. */
process(n_areset,aclk) is begin
if not n_areset then next_axiTxState<=idle;
elsif falling_edge(aclk) then
if falling_edge(aclk) then
next_axiTxState<=axiTxState;
i_writeRequest<=writeRequest;
end if;
149,4 → 153,6
writeResponse<=i_writeResponse;
end if;
end process;
dbg_axiTxFSM<=axiTxState;
end architecture rtl;
/quartus-synthesis/pkg-axi-tlm.vhdl
160,11 → 160,28
-- cActive:
-- end record tAxiTransactor_lp;
type axiBfmStatesTx is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
type t_fsm is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
type axiBfmStatesTx is (idle,payload,endOfTx);
type axiBfmStatesRx is (idle,checkAddr,startOfPacket,payload);
attribute enum_encoding:string;
attribute enum_encoding of axiBfmStatesTx:type is "00 01 10";
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector;
end package axiTLM;
 
package body axiTLM is
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector is
variable r:std_logic_vector(1 downto 0);
begin
case fsm is
when idle=> r:=2x"0";
when payload=> r:=2x"1";
when endOfTx=> r:=2x"2";
when others=> null;
end case;
return r;
end function to_std_logic_vector;
end package body axiTLM;
 
 
/quartus-synthesis/stp.vhd
94,8 → 94,8
sld_enable_advanced_trigger => 0,
sld_mem_address_bits => 12,
sld_node_crc_bits => 32,
sld_node_crc_hiword => 28809,
sld_node_crc_loword => 11476,
sld_node_crc_hiword => 41428,
sld_node_crc_loword => 21204,
sld_node_info => 1076736,
sld_ram_block_type => "Auto",
sld_sample_depth => 4096,
130,13 → 130,13
-- Retrieval info: PRIVATE: TRIGGER_WIDTH_SPIN STRING ""
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: SLD_ADVANCED_TRIGGER_ENTITY STRING "basic,1,"
-- Retrieval info: CONSTANT: SLD_DATA_BITS NUMERIC "128"
-- Retrieval info: CONSTANT: SLD_DATA_BITS NUMERIC "80"
-- Retrieval info: CONSTANT: SLD_DATA_BIT_CNTR_BITS NUMERIC "8"
-- Retrieval info: CONSTANT: SLD_ENABLE_ADVANCED_TRIGGER NUMERIC "0"
-- Retrieval info: CONSTANT: SLD_MEM_ADDRESS_BITS NUMERIC "12"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_BITS NUMERIC "32"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_HIWORD NUMERIC "28809"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_LOWORD NUMERIC "11476"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_HIWORD NUMERIC "41428"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_LOWORD NUMERIC "21204"
-- Retrieval info: CONSTANT: SLD_NODE_INFO NUMERIC "1076736"
-- Retrieval info: CONSTANT: SLD_RAM_BLOCK_TYPE STRING "Auto"
-- Retrieval info: CONSTANT: SLD_SAMPLE_DEPTH NUMERIC "4096"
147,11 → 147,11
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL NUMERIC "1"
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL_PIPELINE NUMERIC "1"
-- Retrieval info: USED_PORT: acq_clk 0 0 0 0 INPUT NODEFVAL "acq_clk"
-- Retrieval info: USED_PORT: acq_data_in 0 0 128 0 INPUT NODEFVAL "acq_data_in[127..0]"
-- Retrieval info: USED_PORT: acq_data_in 0 0 80 0 INPUT NODEFVAL "acq_data_in[79..0]"
-- Retrieval info: USED_PORT: acq_trigger_in 0 0 1 0 INPUT NODEFVAL "acq_trigger_in[0..0]"
-- Retrieval info: USED_PORT: trigger_in 0 0 0 0 INPUT NODEFVAL "trigger_in"
-- Retrieval info: CONNECT: @acq_clk 0 0 0 0 acq_clk 0 0 0 0
-- Retrieval info: CONNECT: @acq_data_in 0 0 128 0 acq_data_in 0 0 128 0
-- Retrieval info: CONNECT: @acq_data_in 0 0 80 0 acq_data_in 0 0 80 0
-- Retrieval info: CONNECT: @acq_trigger_in 0 0 1 0 acq_trigger_in 0 0 1 0
-- Retrieval info: CONNECT: @trigger_in 0 0 0 0 trigger_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp.vhd TRUE
/quartus-synthesis/user.vhdl
78,7 → 78,10
/* synthesis translate_off */
signal clk,nReset:std_ulogic:='0';
/* synthesis translate_on */
signal testerClk:std_ulogic;
--signal trigger:boolean;
signal dbg_axiTxFSM:axiBfmStatesTx;
signal anlysr_dataIn:std_logic_vector(127 downto 0);
signal anlysr_trigger:std_ulogic;
101,7 → 104,8
axiMaster_out=>axiMaster_out,
symbolsPerTransfer=>symbolsPerTransfer,
outstandingTransactions=>outstandingTransactions
outstandingTransactions=>outstandingTransactions,
dbg_axiTxFSM=>dbg_axiTxFSM
);
/* Interrupt-request generator. */
108,6 → 112,14
irq_write<=clk when nReset else '0';
/* Simulation Tester. */
/* PLL to generate tester's clock. */
f100MHz: entity altera.pll(syn) port map(
areset=>not nReset,
inclk0=>clk,
c0=>testerClk,
locked=>open
);
/* synthesis translate_off */
clk<=not clk after 10 ps;
process is begin
118,24 → 130,24
end process;
/* synthesis translate_on */
/* Hardware tester. */
/* directly instantiated if configurations is not used.
component-instantiated if configurations are used.
/*
por: process(reset,clk) is
variable cnt:unsigned(7 downto 0):=x"ff";
begin
if not reset then cnt<=(others=>'1');
elsif rising_edge(clk) then
nReset<='1';
if cnt>x"8" then nReset<='0'; end if;
if cnt>0 then cnt:=cnt-1; end if;
end if;
end process por;
*/
-- i_bist: entity work.framer_bist(tc1)
/*i_bist: entity work.framer_bist(tc2_randomised)
generic map(interPktGap=>3, pktSize=>pktSize)
port map(nReset=>nReset, clk=>clk,
trigger=>trigger,
txDataIn=>txDataIn,
txOut=>data(0),
dataFault=>dataFault, crcFault=>crcFault
);
*/
/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
--trigger<=clk='1';
--anlysr_trigger<='1' when trigger else '0';
anlysr_trigger<='1' when writeRequest.trigger else '0';
/* Disable this for synthesis as this is not currently synthesisable.
145,23 → 157,29
--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
/* synthesis translate_on */
anlysr_dataIn(0)<='1' when nReset else '0';
anlysr_dataIn(1)<='1' when irq_write else '0';
anlysr_dataIn(2)<='1' when axiMaster_in.tReady else '0';
anlysr_dataIn(3)<='1' when axiMaster_out.tValid else '0';
anlysr_dataIn(67 downto 4)<=std_logic_vector(axiMaster_out.tData);
anlysr_dataIn(71 downto 68)<=std_logic_vector(axiMaster_out.tStrb);
anlysr_dataIn(75 downto 72)<=std_logic_vector(axiMaster_out.tKeep);
anlysr_dataIn(76)<='1' when axiMaster_out.tLast else '0';
--anlysr_dataIn(2)<='1' when axiMaster_out.tValid else '0';
anlysr_dataIn(77)<='1' when writeRequest.trigger else '0';
anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
anlysr_dataIn(18)<='1' when clk else '0';
anlysr_dataIn(19)<='1' when nReset else '0';
anlysr_dataIn(20)<='1' when irq_write else '0';
anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
anlysr_dataIn(anlysr_dataIn'high downto 78)<=(others=>'0');
anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
/* Simulate only if you have compiled Altera's simulation libraries. */
i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
acq_clk=>clk,
acq_clk=>testerClk,
acq_data_in=>anlysr_dataIn,
acq_trigger_in=>"1",
trigger_in=>anlysr_trigger
219,10 → 237,36
/* synthesis translate_on */
/* Synthesisable stimuli sequencer. */
axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
process(clk) is begin
if falling_edge(clk) then
axiMaster_in.tReady<=false;
--if axiMaster_out.tValid and not axiMaster_out.tLast then
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
axiMaster_in.tReady<=true;
end if;
end if;
end process;
/* Data transmitter. */
sequencer: process(nReset,irq_write) is
sequencer_ns: process(all) is begin
txFSM<=i_txFSM;
if not nReset then txFSM<=idle;
else
case i_txFSM is
when idle=>
if outstandingTransactions>0 then txFSM<=transmitting; end if;
when transmitting=>
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=> null;
end case;
end if;
end process sequencer_ns;
/* Data transmitter. */
sequencer_op: process(nReset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in t_addr) is begin
read(readRequest,address);
252,20 → 296,11
rv0.InitSeed(rv0'instance_name);
/* synthesis translate_on */
txFSM<=idle;
--txFSM<=idle;
elsif falling_edge(irq_write) then
case txFSM is
when idle=>
if outstandingTransactions>0 then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
write(rand0);
txFSM<=transmitting;
end if;
when transmitting=>
if writeResponse.trigger then
if txFSM/=i_txFSM or writeResponse.trigger then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
272,15 → 307,18
write(rand0);
rand0:=rand0+1;
end if;
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=>null;
end case;
end if;
end process sequencer;
end process sequencer_op;
sequencer_regs: process(irq_write) is begin
if falling_edge(irq_write) then
i_txFSM<=txFSM;
end if;
end process sequencer_regs;
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
process(nReset,irq_write) is
/* synthesis translate_off */
312,7 → 350,7
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
/* synthesis translate_on */
symbolsPerTransfer<=128x"8";
symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
end if;
end if;
end process;

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