OpenCores
URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

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  • This comparison shows the changes necessary to convert path 
    /axi4_tlm_bfm/trunk
    from Rev 18 to Rev 19
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  •

Rev 18 → Rev 19

/workspace/quartus/axi4-tlm.qsf
36,9 → 36,10
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25F324C8
set_global_assignment -name TOP_LEVEL_ENTITY user
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C7
set_global_assignment -name TOP_LEVEL_ENTITY "user"
#set_global_assignment -name TOP_LEVEL_ENTITY "user"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:27:13 SEPTEMBER 06, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION 12.1
45,25 → 46,37
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 324
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
 
#set_location_assignment PIN_M23 -to nReset
#set_location_assignment PIN_Y2 -to clk
set_location_assignment PIN_R7 -to reset
set_location_assignment PIN_E1 -to clk
 
 
#set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user-hw-tlm-paper.vhdl"
 
 
 
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/pkg-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/user.vhdl"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/stp.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/pll.vhd"
set_location_assignment PIN_N2 -to nReset
set_location_assignment PIN_V9 -to clk
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-types.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/pll.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/stp.vhd"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/prbs-31.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/galois-lfsr.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/tester.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/axi4-interface.vhdl"
set_global_assignment -name VHDL_FILE "../../../rtl/quartus-synthesis/user.vhdl"
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/workspace/quartus/axi4-tlm.sdc
1,5 → 1,10
create_clock -period 100MHz -name clk [get_ports {clk}]
derive_pll_clocks -create_base_clock
#derive_pll_clocks -create_base_clock
derive_clock_uncertainty
 
set_false_path -from [get_keepers *por*] -to [get_keepers *por*]
set_false_path -from [get_keepers *reset*]
 
#if {$::quartus(nameofexecutable) == "quartus_fit"} {
#set_max_delay -from *symbolsPerTransfer* -to *i1_outstandingTransactions* -10.000
#set_min_delay -from *symbolsPerTransfer* -to *i1_outstandingTransactions* -10.000
/workspace/quartus/synthesise.sh
37,7 → 37,7
then echo "Build error(s) exist. Refer to report files in the output_files directory for more details. Exiting."; exit;
else
echo $(date "+[%Y-%m-%d %H:%M:%S]: Configuring device...");
quartus_pgm -c 'USB-Blaster [1-1.6]' -m jtag -o 'p;./output_files/axi4-tlm.sof';
quartus_pgm -c 'USB-Blaster [1-1.1]' -m jtag -o 'p;./output_files/axi4-tlm.sof';
fi
 
/workspace/quartus/waves.stp
1,446 → 1,453
<session jtag_chain="USB-Blaster [1-1.6]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="">
<session jtag_chain="USB-Blaster [1-1.1.1.2]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="output_files/axi4-tlm.sof">
<display_tree gui_logging_enabled="0">
<display_branch instance="signaltap_megafunction_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<instance entity_name="sld_signaltap" is_expanded="true" name="signaltap_megafunction_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="2" version="6"/>
<signal_set is_expanded="true" name="signal_set: 2013/09/25 02:14:11 #0">
<clock name="stp:i_bistFramer_stp_analyser|acq_clk" polarity="posedge" tap_mode="classic"/>
<config ram_type="AUTO" reserved_data_nodes="128" reserved_trigger_nodes="1" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="stp:i_bistFramer_stp_analyser|trigger_in" trigger_in_tap_mode="classic" trigger_out_enable="no" trigger_out_node=""/>
<signal_set is_expanded="true" name="signal_set: 2014/01/17 17:27:53 #0">
<clock name="tester:bist|stp:i_bist_logicAnalyser|acq_clk" polarity="posedge" tap_mode="classic"/>
<config ram_type="AUTO" reserved_data_nodes="128" reserved_trigger_nodes="1" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="tester:bist|stp:i_bist_logicAnalyser|trigger_in" trigger_in_tap_mode="classic" trigger_out_enable="no" trigger_out_node=""/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire alias="stp:i_bistFramer_stp_analyser|acq_trigger_in[0]" name="acq_trigger_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_trigger_in[0]" name="acq_trigger_in[0]" tap_mode="classic"/>
</trigger_input_vec>
<data_input_vec>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[0]" name="acq_data_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[1]" name="acq_data_in[1]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[2]" name="acq_data_in[2]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[3]" name="acq_data_in[3]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[4]" name="acq_data_in[4]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[5]" name="acq_data_in[5]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[6]" name="acq_data_in[6]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[7]" name="acq_data_in[7]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[8]" name="acq_data_in[8]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[9]" name="acq_data_in[9]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[10]" name="acq_data_in[10]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[11]" name="acq_data_in[11]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[12]" name="acq_data_in[12]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[13]" name="acq_data_in[13]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[14]" name="acq_data_in[14]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[15]" name="acq_data_in[15]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[16]" name="acq_data_in[16]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[17]" name="acq_data_in[17]" tap_mode="classic" type="unknown"/>
<wire alias="clk" name="acq_data_in[18]" tap_mode="classic" type="unknown"/>
<wire alias="nReset" name="acq_data_in[19]" tap_mode="classic" type="unknown"/>
<wire alias="irq_write" name="acq_data_in[20]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_in.tReady" name="acq_data_in[21]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tValid" name="acq_data_in[22]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[23]" name="acq_data_in[23]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[24]" name="acq_data_in[24]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[25]" name="acq_data_in[25]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[26]" name="acq_data_in[26]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[27]" name="acq_data_in[27]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[28]" name="acq_data_in[28]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[29]" name="acq_data_in[29]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[30]" name="acq_data_in[30]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[31]" name="acq_data_in[31]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[32]" name="acq_data_in[32]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[33]" name="acq_data_in[33]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[34]" name="acq_data_in[34]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[35]" name="acq_data_in[35]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[36]" name="acq_data_in[36]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[37]" name="acq_data_in[37]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[38]" name="acq_data_in[38]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[39]" name="acq_data_in[39]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[40]" name="acq_data_in[40]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[41]" name="acq_data_in[41]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[42]" name="acq_data_in[42]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[43]" name="acq_data_in[43]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[44]" name="acq_data_in[44]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[45]" name="acq_data_in[45]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[46]" name="acq_data_in[46]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[47]" name="acq_data_in[47]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[48]" name="acq_data_in[48]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[49]" name="acq_data_in[49]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[50]" name="acq_data_in[50]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[51]" name="acq_data_in[51]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[52]" name="acq_data_in[52]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[53]" name="acq_data_in[53]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[54]" name="acq_data_in[54]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[55]" name="acq_data_in[55]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[56]" name="acq_data_in[56]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[57]" name="acq_data_in[57]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[58]" name="acq_data_in[58]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[59]" name="acq_data_in[59]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[60]" name="acq_data_in[60]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[61]" name="acq_data_in[61]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[62]" name="acq_data_in[62]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[63]" name="acq_data_in[63]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[64]" name="acq_data_in[64]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[65]" name="acq_data_in[65]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[66]" name="acq_data_in[66]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[67]" name="acq_data_in[67]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[68]" name="acq_data_in[68]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[69]" name="acq_data_in[69]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[70]" name="acq_data_in[70]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[71]" name="acq_data_in[71]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[72]" name="acq_data_in[72]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[73]" name="acq_data_in[73]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[74]" name="acq_data_in[74]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[75]" name="acq_data_in[75]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[76]" name="acq_data_in[76]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[77]" name="acq_data_in[77]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[78]" name="acq_data_in[78]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[79]" name="acq_data_in[79]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[80]" name="acq_data_in[80]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[81]" name="acq_data_in[81]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[82]" name="acq_data_in[82]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[83]" name="acq_data_in[83]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[84]" name="acq_data_in[84]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[85]" name="acq_data_in[85]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[86]" name="acq_data_in[86]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[87]" name="acq_data_in[87]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[88]" name="acq_data_in[88]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[89]" name="acq_data_in[89]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[90]" name="acq_data_in[90]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[91]" name="acq_data_in[91]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[92]" name="acq_data_in[92]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[93]" name="acq_data_in[93]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[94]" name="acq_data_in[94]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tLast" name="acq_data_in[95]" tap_mode="classic" type="unknown"/>
<wire alias="writeRequest.trigger" name="acq_data_in[96]" tap_mode="classic" type="unknown"/>
<wire alias="writeResponse.trigger" name="acq_data_in[97]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[98]" name="acq_data_in[98]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[99]" name="acq_data_in[99]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[100]" name="acq_data_in[100]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[101]" name="acq_data_in[101]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[102]" name="acq_data_in[102]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[103]" name="acq_data_in[103]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[104]" name="acq_data_in[104]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[105]" name="acq_data_in[105]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[106]" name="acq_data_in[106]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[107]" name="acq_data_in[107]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[108]" name="acq_data_in[108]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[109]" name="acq_data_in[109]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[110]" name="acq_data_in[110]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[111]" name="acq_data_in[111]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[112]" name="acq_data_in[112]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[113]" name="acq_data_in[113]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[114]" name="acq_data_in[114]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[115]" name="acq_data_in[115]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[116]" name="acq_data_in[116]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[117]" name="acq_data_in[117]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[118]" name="acq_data_in[118]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[119]" name="acq_data_in[119]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[120]" name="acq_data_in[120]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[121]" name="acq_data_in[121]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[122]" name="acq_data_in[122]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[123]" name="acq_data_in[123]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[124]" name="acq_data_in[124]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[125]" name="acq_data_in[125]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[126]" name="acq_data_in[126]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[127]" name="acq_data_in[127]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[0]" name="acq_data_in[0]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[1]" name="acq_data_in[1]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[2]" name="acq_data_in[2]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[3]" name="acq_data_in[3]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[4]" name="acq_data_in[4]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[5]" name="acq_data_in[5]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[6]" name="acq_data_in[6]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[7]" name="acq_data_in[7]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[8]" name="acq_data_in[8]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[9]" name="acq_data_in[9]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[10]" name="acq_data_in[10]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[11]" name="acq_data_in[11]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[12]" name="acq_data_in[12]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[13]" name="acq_data_in[13]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[14]" name="acq_data_in[14]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[15]" name="acq_data_in[15]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[16]" name="acq_data_in[16]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[17]" name="acq_data_in[17]" tap_mode="classic"/>
<wire alias="clk" name="acq_data_in[18]" tap_mode="classic"/>
<wire alias="reset" name="acq_data_in[19]" tap_mode="classic"/>
<wire alias="irq_write" name="acq_data_in[20]" tap_mode="classic"/>
<wire alias="axiMaster_in.tReady" name="acq_data_in[21]" tap_mode="classic"/>
<wire alias="axiMaster_out.tValid" name="acq_data_in[22]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[23]" name="acq_data_in[23]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[24]" name="acq_data_in[24]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[25]" name="acq_data_in[25]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[26]" name="acq_data_in[26]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[27]" name="acq_data_in[27]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[28]" name="acq_data_in[28]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[29]" name="acq_data_in[29]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[30]" name="acq_data_in[30]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[31]" name="acq_data_in[31]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[32]" name="acq_data_in[32]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[33]" name="acq_data_in[33]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[34]" name="acq_data_in[34]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[35]" name="acq_data_in[35]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[36]" name="acq_data_in[36]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[37]" name="acq_data_in[37]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[38]" name="acq_data_in[38]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[39]" name="acq_data_in[39]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[40]" name="acq_data_in[40]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[41]" name="acq_data_in[41]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[42]" name="acq_data_in[42]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[43]" name="acq_data_in[43]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[44]" name="acq_data_in[44]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[45]" name="acq_data_in[45]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[46]" name="acq_data_in[46]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[47]" name="acq_data_in[47]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[48]" name="acq_data_in[48]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[49]" name="acq_data_in[49]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[50]" name="acq_data_in[50]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[51]" name="acq_data_in[51]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[52]" name="acq_data_in[52]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[53]" name="acq_data_in[53]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[54]" name="acq_data_in[54]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[55]" name="acq_data_in[55]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[56]" name="acq_data_in[56]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[57]" name="acq_data_in[57]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[58]" name="acq_data_in[58]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[59]" name="acq_data_in[59]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[60]" name="acq_data_in[60]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[61]" name="acq_data_in[61]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[62]" name="acq_data_in[62]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[63]" name="acq_data_in[63]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[64]" name="acq_data_in[64]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[65]" name="acq_data_in[65]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[66]" name="acq_data_in[66]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[67]" name="acq_data_in[67]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[68]" name="acq_data_in[68]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[69]" name="acq_data_in[69]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[70]" name="acq_data_in[70]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[71]" name="acq_data_in[71]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[72]" name="acq_data_in[72]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[73]" name="acq_data_in[73]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[74]" name="acq_data_in[74]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[75]" name="acq_data_in[75]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[76]" name="acq_data_in[76]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[77]" name="acq_data_in[77]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[78]" name="acq_data_in[78]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[79]" name="acq_data_in[79]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[80]" name="acq_data_in[80]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[81]" name="acq_data_in[81]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[82]" name="acq_data_in[82]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[83]" name="acq_data_in[83]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[84]" name="acq_data_in[84]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[85]" name="acq_data_in[85]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[86]" name="acq_data_in[86]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[87]" name="acq_data_in[87]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[88]" name="acq_data_in[88]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[89]" name="acq_data_in[89]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[90]" name="acq_data_in[90]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[91]" name="acq_data_in[91]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[92]" name="acq_data_in[92]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[93]" name="acq_data_in[93]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[94]" name="acq_data_in[94]" tap_mode="classic"/>
<wire alias="axiMaster_out.tLast" name="acq_data_in[95]" tap_mode="classic"/>
<wire alias="writeRequest.trigger" name="acq_data_in[96]" tap_mode="classic"/>
<wire alias="writeResponse.trigger" name="acq_data_in[97]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[98]" name="acq_data_in[98]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[99]" name="acq_data_in[99]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[100]" name="acq_data_in[100]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[101]" name="acq_data_in[101]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[102]" name="acq_data_in[102]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[103]" name="acq_data_in[103]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[104]" name="acq_data_in[104]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[105]" name="acq_data_in[105]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[106]" name="acq_data_in[106]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[107]" name="acq_data_in[107]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[108]" name="acq_data_in[108]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[109]" name="acq_data_in[109]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[110]" name="acq_data_in[110]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[111]" name="acq_data_in[111]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[112]" name="acq_data_in[112]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[113]" name="acq_data_in[113]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[114]" name="acq_data_in[114]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[115]" name="acq_data_in[115]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[116]" name="acq_data_in[116]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[117]" name="acq_data_in[117]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[118]" name="acq_data_in[118]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[119]" name="acq_data_in[119]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[120]" name="acq_data_in[120]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[121]" name="acq_data_in[121]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[122]" name="acq_data_in[122]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[123]" name="acq_data_in[123]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[124]" name="acq_data_in[124]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[125]" name="acq_data_in[125]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[126]" name="acq_data_in[126]" tap_mode="classic"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[127]" name="acq_data_in[127]" tap_mode="classic"/>
</data_input_vec>
<storage_qualifier_input_vec/>
</signal_vec>
<presentation>
<data_view>
<bus alias="symbolsPerTransfer" is_signal_inverted="no" link="all" name="acq_data_in[0..7]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<net is_signal_inverted="no" name="acq_data_in[4]"/>
<net is_signal_inverted="no" name="acq_data_in[5]"/>
<net is_signal_inverted="no" name="acq_data_in[6]"/>
<net is_signal_inverted="no" name="acq_data_in[7]"/>
<bus alias="symbolsPerTransfer" mnemonics="" name="acq_data_in[0..7]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[0]"/>
<net name="acq_data_in[1]"/>
<net name="acq_data_in[2]"/>
<net name="acq_data_in[3]"/>
<net name="acq_data_in[4]"/>
<net name="acq_data_in[5]"/>
<net name="acq_data_in[6]"/>
<net name="acq_data_in[7]"/>
</bus>
<bus alias="outstandingTransactions" is_signal_inverted="no" link="all" name="acq_data_in[8..15]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[8]"/>
<net is_signal_inverted="no" name="acq_data_in[9]"/>
<net is_signal_inverted="no" name="acq_data_in[10]"/>
<net is_signal_inverted="no" name="acq_data_in[11]"/>
<net is_signal_inverted="no" name="acq_data_in[12]"/>
<net is_signal_inverted="no" name="acq_data_in[13]"/>
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
<bus alias="outstandingTransactions" mnemonics="" name="acq_data_in[8..15]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[8]"/>
<net name="acq_data_in[9]"/>
<net name="acq_data_in[10]"/>
<net name="acq_data_in[11]"/>
<net name="acq_data_in[12]"/>
<net name="acq_data_in[13]"/>
<net name="acq_data_in[14]"/>
<net name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
<bus alias="axiTxFSM" mnemonics="" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[16]"/>
<net name="acq_data_in[17]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
<net is_signal_inverted="no" name="acq_data_in[26]"/>
<net is_signal_inverted="no" name="acq_data_in[27]"/>
<net is_signal_inverted="no" name="acq_data_in[28]"/>
<net is_signal_inverted="no" name="acq_data_in[29]"/>
<net is_signal_inverted="no" name="acq_data_in[30]"/>
<net is_signal_inverted="no" name="acq_data_in[31]"/>
<net is_signal_inverted="no" name="acq_data_in[32]"/>
<net is_signal_inverted="no" name="acq_data_in[33]"/>
<net is_signal_inverted="no" name="acq_data_in[34]"/>
<net is_signal_inverted="no" name="acq_data_in[35]"/>
<net is_signal_inverted="no" name="acq_data_in[36]"/>
<net is_signal_inverted="no" name="acq_data_in[37]"/>
<net is_signal_inverted="no" name="acq_data_in[38]"/>
<net is_signal_inverted="no" name="acq_data_in[39]"/>
<net is_signal_inverted="no" name="acq_data_in[40]"/>
<net is_signal_inverted="no" name="acq_data_in[41]"/>
<net is_signal_inverted="no" name="acq_data_in[42]"/>
<net is_signal_inverted="no" name="acq_data_in[43]"/>
<net is_signal_inverted="no" name="acq_data_in[44]"/>
<net is_signal_inverted="no" name="acq_data_in[45]"/>
<net is_signal_inverted="no" name="acq_data_in[46]"/>
<net is_signal_inverted="no" name="acq_data_in[47]"/>
<net is_signal_inverted="no" name="acq_data_in[48]"/>
<net is_signal_inverted="no" name="acq_data_in[49]"/>
<net is_signal_inverted="no" name="acq_data_in[50]"/>
<net is_signal_inverted="no" name="acq_data_in[51]"/>
<net is_signal_inverted="no" name="acq_data_in[52]"/>
<net is_signal_inverted="no" name="acq_data_in[53]"/>
<net is_signal_inverted="no" name="acq_data_in[54]"/>
<net is_signal_inverted="no" name="acq_data_in[55]"/>
<net is_signal_inverted="no" name="acq_data_in[56]"/>
<net is_signal_inverted="no" name="acq_data_in[57]"/>
<net is_signal_inverted="no" name="acq_data_in[58]"/>
<net is_signal_inverted="no" name="acq_data_in[59]"/>
<net is_signal_inverted="no" name="acq_data_in[60]"/>
<net is_signal_inverted="no" name="acq_data_in[61]"/>
<net is_signal_inverted="no" name="acq_data_in[62]"/>
<net is_signal_inverted="no" name="acq_data_in[63]"/>
<net is_signal_inverted="no" name="acq_data_in[64]"/>
<net is_signal_inverted="no" name="acq_data_in[65]"/>
<net is_signal_inverted="no" name="acq_data_in[66]"/>
<net is_signal_inverted="no" name="acq_data_in[67]"/>
<net is_signal_inverted="no" name="acq_data_in[68]"/>
<net is_signal_inverted="no" name="acq_data_in[69]"/>
<net is_signal_inverted="no" name="acq_data_in[70]"/>
<net is_signal_inverted="no" name="acq_data_in[71]"/>
<net is_signal_inverted="no" name="acq_data_in[72]"/>
<net is_signal_inverted="no" name="acq_data_in[73]"/>
<net is_signal_inverted="no" name="acq_data_in[74]"/>
<net is_signal_inverted="no" name="acq_data_in[75]"/>
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<net is_signal_inverted="no" name="acq_data_in[77]"/>
<net is_signal_inverted="no" name="acq_data_in[78]"/>
<net is_signal_inverted="no" name="acq_data_in[79]"/>
<net is_signal_inverted="no" name="acq_data_in[80]"/>
<net is_signal_inverted="no" name="acq_data_in[81]"/>
<net is_signal_inverted="no" name="acq_data_in[82]"/>
<net is_signal_inverted="no" name="acq_data_in[83]"/>
<net is_signal_inverted="no" name="acq_data_in[84]"/>
<net is_signal_inverted="no" name="acq_data_in[85]"/>
<net is_signal_inverted="no" name="acq_data_in[86]"/>
<net name="acq_data_in[18]"/>
<net name="acq_data_in[19]"/>
<net name="acq_data_in[20]"/>
<net name="acq_data_in[21]"/>
<net name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" mnemonics="" name="acq_data_in[23..54]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[23]"/>
<net name="acq_data_in[24]"/>
<net name="acq_data_in[25]"/>
<net name="acq_data_in[26]"/>
<net name="acq_data_in[27]"/>
<net name="acq_data_in[28]"/>
<net name="acq_data_in[29]"/>
<net name="acq_data_in[30]"/>
<net name="acq_data_in[31]"/>
<net name="acq_data_in[32]"/>
<net name="acq_data_in[33]"/>
<net name="acq_data_in[34]"/>
<net name="acq_data_in[35]"/>
<net name="acq_data_in[36]"/>
<net name="acq_data_in[37]"/>
<net name="acq_data_in[38]"/>
<net name="acq_data_in[39]"/>
<net name="acq_data_in[40]"/>
<net name="acq_data_in[41]"/>
<net name="acq_data_in[42]"/>
<net name="acq_data_in[43]"/>
<net name="acq_data_in[44]"/>
<net name="acq_data_in[45]"/>
<net name="acq_data_in[46]"/>
<net name="acq_data_in[47]"/>
<net name="acq_data_in[48]"/>
<net name="acq_data_in[49]"/>
<net name="acq_data_in[50]"/>
<net name="acq_data_in[51]"/>
<net name="acq_data_in[52]"/>
<net name="acq_data_in[53]"/>
<net name="acq_data_in[54]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[87..90]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[87]"/>
<net is_signal_inverted="no" name="acq_data_in[88]"/>
<net is_signal_inverted="no" name="acq_data_in[89]"/>
<net is_signal_inverted="no" name="acq_data_in[90]"/>
<bus alias="prbs" mnemonics="" name="acq_data_in[55..86]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[55]"/>
<net name="acq_data_in[56]"/>
<net name="acq_data_in[57]"/>
<net name="acq_data_in[58]"/>
<net name="acq_data_in[59]"/>
<net name="acq_data_in[60]"/>
<net name="acq_data_in[61]"/>
<net name="acq_data_in[62]"/>
<net name="acq_data_in[63]"/>
<net name="acq_data_in[64]"/>
<net name="acq_data_in[65]"/>
<net name="acq_data_in[66]"/>
<net name="acq_data_in[67]"/>
<net name="acq_data_in[68]"/>
<net name="acq_data_in[69]"/>
<net name="acq_data_in[70]"/>
<net name="acq_data_in[71]"/>
<net name="acq_data_in[72]"/>
<net name="acq_data_in[73]"/>
<net name="acq_data_in[74]"/>
<net name="acq_data_in[75]"/>
<net name="acq_data_in[76]"/>
<net name="acq_data_in[77]"/>
<net name="acq_data_in[78]"/>
<net name="acq_data_in[79]"/>
<net name="acq_data_in[80]"/>
<net name="acq_data_in[81]"/>
<net name="acq_data_in[82]"/>
<net name="acq_data_in[83]"/>
<net name="acq_data_in[84]"/>
<net name="acq_data_in[85]"/>
<net name="acq_data_in[86]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[91..94]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[91]"/>
<net is_signal_inverted="no" name="acq_data_in[92]"/>
<net is_signal_inverted="no" name="acq_data_in[93]"/>
<net is_signal_inverted="no" name="acq_data_in[94]"/>
<bus alias="axiMaster_out.tStrb" mnemonics="" name="acq_data_in[87..90]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[87]"/>
<net name="acq_data_in[88]"/>
<net name="acq_data_in[89]"/>
<net name="acq_data_in[90]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
<net is_signal_inverted="no" name="acq_data_in[101]"/>
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
<bus alias="axiMaster_out.tKeep" mnemonics="" name="acq_data_in[91..94]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[91]"/>
<net name="acq_data_in[92]"/>
<net name="acq_data_in[93]"/>
<net name="acq_data_in[94]"/>
</bus>
<net name="acq_data_in[95]"/>
<net name="acq_data_in[96]"/>
<net name="acq_data_in[97]"/>
<bus alias="porCnt" mnemonics="" name="acq_data_in[98..101]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[98]"/>
<net name="acq_data_in[99]"/>
<net name="acq_data_in[100]"/>
<net name="acq_data_in[101]"/>
</bus>
<bus mnemonics="" name="acq_data_in[102..127]" order="lsb_to_msb" state="collapse" type="unknown">
<net name="acq_data_in[102]"/>
<net name="acq_data_in[103]"/>
<net name="acq_data_in[104]"/>
<net name="acq_data_in[105]"/>
<net name="acq_data_in[106]"/>
<net name="acq_data_in[107]"/>
<net name="acq_data_in[108]"/>
<net name="acq_data_in[109]"/>
<net name="acq_data_in[110]"/>
<net name="acq_data_in[111]"/>
<net name="acq_data_in[112]"/>
<net name="acq_data_in[113]"/>
<net name="acq_data_in[114]"/>
<net name="acq_data_in[115]"/>
<net name="acq_data_in[116]"/>
<net name="acq_data_in[117]"/>
<net name="acq_data_in[118]"/>
<net name="acq_data_in[119]"/>
<net name="acq_data_in[120]"/>
<net name="acq_data_in[121]"/>
<net name="acq_data_in[122]"/>
<net name="acq_data_in[123]"/>
<net name="acq_data_in[124]"/>
<net name="acq_data_in[125]"/>
<net name="acq_data_in[126]"/>
<net name="acq_data_in[127]"/>
</bus>
</data_view>
<setup_view>
<bus alias="symbolsPerTransfer" is_signal_inverted="no" link="all" name="acq_data_in[0..7]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<net is_signal_inverted="no" name="acq_data_in[4]"/>
<net is_signal_inverted="no" name="acq_data_in[5]"/>
<net is_signal_inverted="no" name="acq_data_in[6]"/>
<net is_signal_inverted="no" name="acq_data_in[7]"/>
<bus alias="symbolsPerTransfer" name="acq_data_in[0..7]" state="collapse" type="unknown">
<net name="acq_data_in[0]"/>
<net name="acq_data_in[1]"/>
<net name="acq_data_in[2]"/>
<net name="acq_data_in[3]"/>
<net name="acq_data_in[4]"/>
<net name="acq_data_in[5]"/>
<net name="acq_data_in[6]"/>
<net name="acq_data_in[7]"/>
</bus>
<bus alias="outstandingTransactions" is_signal_inverted="no" link="all" name="acq_data_in[8..15]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[8]"/>
<net is_signal_inverted="no" name="acq_data_in[9]"/>
<net is_signal_inverted="no" name="acq_data_in[10]"/>
<net is_signal_inverted="no" name="acq_data_in[11]"/>
<net is_signal_inverted="no" name="acq_data_in[12]"/>
<net is_signal_inverted="no" name="acq_data_in[13]"/>
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
<bus alias="outstandingTransactions" name="acq_data_in[8..15]" state="collapse" type="unknown">
<net name="acq_data_in[8]"/>
<net name="acq_data_in[9]"/>
<net name="acq_data_in[10]"/>
<net name="acq_data_in[11]"/>
<net name="acq_data_in[12]"/>
<net name="acq_data_in[13]"/>
<net name="acq_data_in[14]"/>
<net name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
<bus alias="axiTxFSM" name="acq_data_in[16..17]" state="collapse" type="unknown">
<net name="acq_data_in[16]"/>
<net name="acq_data_in[17]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
<net is_signal_inverted="no" name="acq_data_in[26]"/>
<net is_signal_inverted="no" name="acq_data_in[27]"/>
<net is_signal_inverted="no" name="acq_data_in[28]"/>
<net is_signal_inverted="no" name="acq_data_in[29]"/>
<net is_signal_inverted="no" name="acq_data_in[30]"/>
<net is_signal_inverted="no" name="acq_data_in[31]"/>
<net is_signal_inverted="no" name="acq_data_in[32]"/>
<net is_signal_inverted="no" name="acq_data_in[33]"/>
<net is_signal_inverted="no" name="acq_data_in[34]"/>
<net is_signal_inverted="no" name="acq_data_in[35]"/>
<net is_signal_inverted="no" name="acq_data_in[36]"/>
<net is_signal_inverted="no" name="acq_data_in[37]"/>
<net is_signal_inverted="no" name="acq_data_in[38]"/>
<net is_signal_inverted="no" name="acq_data_in[39]"/>
<net is_signal_inverted="no" name="acq_data_in[40]"/>
<net is_signal_inverted="no" name="acq_data_in[41]"/>
<net is_signal_inverted="no" name="acq_data_in[42]"/>
<net is_signal_inverted="no" name="acq_data_in[43]"/>
<net is_signal_inverted="no" name="acq_data_in[44]"/>
<net is_signal_inverted="no" name="acq_data_in[45]"/>
<net is_signal_inverted="no" name="acq_data_in[46]"/>
<net is_signal_inverted="no" name="acq_data_in[47]"/>
<net is_signal_inverted="no" name="acq_data_in[48]"/>
<net is_signal_inverted="no" name="acq_data_in[49]"/>
<net is_signal_inverted="no" name="acq_data_in[50]"/>
<net is_signal_inverted="no" name="acq_data_in[51]"/>
<net is_signal_inverted="no" name="acq_data_in[52]"/>
<net is_signal_inverted="no" name="acq_data_in[53]"/>
<net is_signal_inverted="no" name="acq_data_in[54]"/>
<net is_signal_inverted="no" name="acq_data_in[55]"/>
<net is_signal_inverted="no" name="acq_data_in[56]"/>
<net is_signal_inverted="no" name="acq_data_in[57]"/>
<net is_signal_inverted="no" name="acq_data_in[58]"/>
<net is_signal_inverted="no" name="acq_data_in[59]"/>
<net is_signal_inverted="no" name="acq_data_in[60]"/>
<net is_signal_inverted="no" name="acq_data_in[61]"/>
<net is_signal_inverted="no" name="acq_data_in[62]"/>
<net is_signal_inverted="no" name="acq_data_in[63]"/>
<net is_signal_inverted="no" name="acq_data_in[64]"/>
<net is_signal_inverted="no" name="acq_data_in[65]"/>
<net is_signal_inverted="no" name="acq_data_in[66]"/>
<net is_signal_inverted="no" name="acq_data_in[67]"/>
<net is_signal_inverted="no" name="acq_data_in[68]"/>
<net is_signal_inverted="no" name="acq_data_in[69]"/>
<net is_signal_inverted="no" name="acq_data_in[70]"/>
<net is_signal_inverted="no" name="acq_data_in[71]"/>
<net is_signal_inverted="no" name="acq_data_in[72]"/>
<net is_signal_inverted="no" name="acq_data_in[73]"/>
<net is_signal_inverted="no" name="acq_data_in[74]"/>
<net is_signal_inverted="no" name="acq_data_in[75]"/>
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<net is_signal_inverted="no" name="acq_data_in[77]"/>
<net is_signal_inverted="no" name="acq_data_in[78]"/>
<net is_signal_inverted="no" name="acq_data_in[79]"/>
<net is_signal_inverted="no" name="acq_data_in[80]"/>
<net is_signal_inverted="no" name="acq_data_in[81]"/>
<net is_signal_inverted="no" name="acq_data_in[82]"/>
<net is_signal_inverted="no" name="acq_data_in[83]"/>
<net is_signal_inverted="no" name="acq_data_in[84]"/>
<net is_signal_inverted="no" name="acq_data_in[85]"/>
<net is_signal_inverted="no" name="acq_data_in[86]"/>
<net name="acq_data_in[18]"/>
<net name="acq_data_in[19]"/>
<net name="acq_data_in[20]"/>
<net name="acq_data_in[21]"/>
<net name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" name="acq_data_in[23..54]" state="collapse" type="unknown">
<net name="acq_data_in[23]"/>
<net name="acq_data_in[24]"/>
<net name="acq_data_in[25]"/>
<net name="acq_data_in[26]"/>
<net name="acq_data_in[27]"/>
<net name="acq_data_in[28]"/>
<net name="acq_data_in[29]"/>
<net name="acq_data_in[30]"/>
<net name="acq_data_in[31]"/>
<net name="acq_data_in[32]"/>
<net name="acq_data_in[33]"/>
<net name="acq_data_in[34]"/>
<net name="acq_data_in[35]"/>
<net name="acq_data_in[36]"/>
<net name="acq_data_in[37]"/>
<net name="acq_data_in[38]"/>
<net name="acq_data_in[39]"/>
<net name="acq_data_in[40]"/>
<net name="acq_data_in[41]"/>
<net name="acq_data_in[42]"/>
<net name="acq_data_in[43]"/>
<net name="acq_data_in[44]"/>
<net name="acq_data_in[45]"/>
<net name="acq_data_in[46]"/>
<net name="acq_data_in[47]"/>
<net name="acq_data_in[48]"/>
<net name="acq_data_in[49]"/>
<net name="acq_data_in[50]"/>
<net name="acq_data_in[51]"/>
<net name="acq_data_in[52]"/>
<net name="acq_data_in[53]"/>
<net name="acq_data_in[54]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[87..90]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[87]"/>
<net is_signal_inverted="no" name="acq_data_in[88]"/>
<net is_signal_inverted="no" name="acq_data_in[89]"/>
<net is_signal_inverted="no" name="acq_data_in[90]"/>
<bus alias="prbs" name="acq_data_in[55..86]" state="collapse" type="unknown">
<net name="acq_data_in[55]"/>
<net name="acq_data_in[56]"/>
<net name="acq_data_in[57]"/>
<net name="acq_data_in[58]"/>
<net name="acq_data_in[59]"/>
<net name="acq_data_in[60]"/>
<net name="acq_data_in[61]"/>
<net name="acq_data_in[62]"/>
<net name="acq_data_in[63]"/>
<net name="acq_data_in[64]"/>
<net name="acq_data_in[65]"/>
<net name="acq_data_in[66]"/>
<net name="acq_data_in[67]"/>
<net name="acq_data_in[68]"/>
<net name="acq_data_in[69]"/>
<net name="acq_data_in[70]"/>
<net name="acq_data_in[71]"/>
<net name="acq_data_in[72]"/>
<net name="acq_data_in[73]"/>
<net name="acq_data_in[74]"/>
<net name="acq_data_in[75]"/>
<net name="acq_data_in[76]"/>
<net name="acq_data_in[77]"/>
<net name="acq_data_in[78]"/>
<net name="acq_data_in[79]"/>
<net name="acq_data_in[80]"/>
<net name="acq_data_in[81]"/>
<net name="acq_data_in[82]"/>
<net name="acq_data_in[83]"/>
<net name="acq_data_in[84]"/>
<net name="acq_data_in[85]"/>
<net name="acq_data_in[86]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[91..94]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[91]"/>
<net is_signal_inverted="no" name="acq_data_in[92]"/>
<net is_signal_inverted="no" name="acq_data_in[93]"/>
<net is_signal_inverted="no" name="acq_data_in[94]"/>
<bus alias="axiMaster_out.tStrb" name="acq_data_in[87..90]" state="collapse" type="unknown">
<net name="acq_data_in[87]"/>
<net name="acq_data_in[88]"/>
<net name="acq_data_in[89]"/>
<net name="acq_data_in[90]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
<net is_signal_inverted="no" name="acq_data_in[101]"/>
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
<bus alias="axiMaster_out.tKeep" name="acq_data_in[91..94]" state="collapse" type="unknown">
<net name="acq_data_in[91]"/>
<net name="acq_data_in[92]"/>
<net name="acq_data_in[93]"/>
<net name="acq_data_in[94]"/>
</bus>
<net is_signal_inverted="no" name="acq_trigger_in[0]"/>
<net name="acq_data_in[95]"/>
<net name="acq_data_in[96]"/>
<net name="acq_data_in[97]"/>
<bus alias="porCnt" name="acq_data_in[98..101]" state="collapse" type="unknown">
<net name="acq_data_in[98]"/>
<net name="acq_data_in[99]"/>
<net name="acq_data_in[100]"/>
<net name="acq_data_in[101]"/>
</bus>
<bus name="acq_data_in[102..127]" state="collapse" type="unknown">
<net name="acq_data_in[102]"/>
<net name="acq_data_in[103]"/>
<net name="acq_data_in[104]"/>
<net name="acq_data_in[105]"/>
<net name="acq_data_in[106]"/>
<net name="acq_data_in[107]"/>
<net name="acq_data_in[108]"/>
<net name="acq_data_in[109]"/>
<net name="acq_data_in[110]"/>
<net name="acq_data_in[111]"/>
<net name="acq_data_in[112]"/>
<net name="acq_data_in[113]"/>
<net name="acq_data_in[114]"/>
<net name="acq_data_in[115]"/>
<net name="acq_data_in[116]"/>
<net name="acq_data_in[117]"/>
<net name="acq_data_in[118]"/>
<net name="acq_data_in[119]"/>
<net name="acq_data_in[120]"/>
<net name="acq_data_in[121]"/>
<net name="acq_data_in[122]"/>
<net name="acq_data_in[123]"/>
<net name="acq_data_in[124]"/>
<net name="acq_data_in[125]"/>
<net name="acq_data_in[126]"/>
<net name="acq_data_in[127]"/>
</bus>
<net name="acq_trigger_in[0]"/>
</setup_view>
</presentation>
<trigger CRC="A1D452D4" gap_record="true" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_port_is_pin="false" storage_qualifier_port_tap_mode="classic" trigger_in="falling edge" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
<events use_custom_flow_control="no">
<trigger CRC="1EAEA6CB" gap_record="true" is_expanded="true" name="trigger: 2014/01/17 17:27:53 #1" record_data_gap="true" storage_mode="off" storage_qualifier_port_is_pin="false" storage_qualifier_port_tap_mode="classic">
<power_up_trigger/>
<events>
<level type="basic"><power_up>
</power_up>
<op_node/>
</level>
</events>
<storage_qualifier>
451,165 → 458,158
<storage_qualifier_level>
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level>
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level>
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<transitional>
<pwr_up_transitional/>
</transitional>
</storage_qualifier_events>
<log>
<data name="log: 2013/09/28 19:27:15 #0" power_up_mode="false" sample_depth="0" trigger_position="-1"/>
<extradata/>
</log>
</trigger>
</signal_set>
<signal_set global_temp="1" is_expanded="true" name="signal_set: 2013/09/25 02:14:11 #0">
<clock name="stp:i_bistFramer_stp_analyser|acq_clk" polarity="posedge" tap_mode="classic"/>
<config ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="stp:i_bistFramer_stp_analyser|trigger_in" trigger_in_tap_mode="classic" trigger_out_enable="no"/>
<signal_set global_temp="1" is_expanded="true" name="signal_set: 2014/01/17 17:27:53 #0">
<clock name="tester:bist|stp:i_bist_logicAnalyser|acq_clk" polarity="posedge" tap_mode="classic"/>
<config ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="tester:bist|stp:i_bist_logicAnalyser|trigger_in" trigger_in_tap_mode="classic" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire alias="stp:i_bistFramer_stp_analyser|acq_trigger_in[0]" name="acq_trigger_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_trigger_in[0]" name="acq_trigger_in[0]" tap_mode="classic" type="unknown"/>
</trigger_input_vec>
<data_input_vec>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[0]" name="acq_data_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[1]" name="acq_data_in[1]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[2]" name="acq_data_in[2]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[3]" name="acq_data_in[3]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[4]" name="acq_data_in[4]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[5]" name="acq_data_in[5]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[6]" name="acq_data_in[6]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[7]" name="acq_data_in[7]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[8]" name="acq_data_in[8]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[9]" name="acq_data_in[9]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[10]" name="acq_data_in[10]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[11]" name="acq_data_in[11]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[12]" name="acq_data_in[12]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[13]" name="acq_data_in[13]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[14]" name="acq_data_in[14]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[15]" name="acq_data_in[15]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[16]" name="acq_data_in[16]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[17]" name="acq_data_in[17]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[0]" name="acq_data_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[1]" name="acq_data_in[1]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[2]" name="acq_data_in[2]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[3]" name="acq_data_in[3]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[4]" name="acq_data_in[4]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[5]" name="acq_data_in[5]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[6]" name="acq_data_in[6]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[7]" name="acq_data_in[7]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[8]" name="acq_data_in[8]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[9]" name="acq_data_in[9]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[10]" name="acq_data_in[10]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[11]" name="acq_data_in[11]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[12]" name="acq_data_in[12]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[13]" name="acq_data_in[13]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[14]" name="acq_data_in[14]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[15]" name="acq_data_in[15]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[16]" name="acq_data_in[16]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[17]" name="acq_data_in[17]" tap_mode="classic" type="unknown"/>
<wire alias="clk" name="acq_data_in[18]" tap_mode="classic" type="unknown"/>
<wire alias="reset" name="acq_data_in[19]" tap_mode="classic" type="unknown"/>
<wire alias="irq_write" name="acq_data_in[20]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_in.tReady" name="acq_data_in[21]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tValid" name="acq_data_in[22]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[23]" name="acq_data_in[23]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[24]" name="acq_data_in[24]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[25]" name="acq_data_in[25]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[26]" name="acq_data_in[26]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[27]" name="acq_data_in[27]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[28]" name="acq_data_in[28]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[29]" name="acq_data_in[29]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[30]" name="acq_data_in[30]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[31]" name="acq_data_in[31]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[32]" name="acq_data_in[32]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[33]" name="acq_data_in[33]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[34]" name="acq_data_in[34]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[35]" name="acq_data_in[35]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[36]" name="acq_data_in[36]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[37]" name="acq_data_in[37]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[38]" name="acq_data_in[38]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[39]" name="acq_data_in[39]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[40]" name="acq_data_in[40]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[41]" name="acq_data_in[41]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[42]" name="acq_data_in[42]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[43]" name="acq_data_in[43]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[44]" name="acq_data_in[44]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[45]" name="acq_data_in[45]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[46]" name="acq_data_in[46]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[47]" name="acq_data_in[47]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[48]" name="acq_data_in[48]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[49]" name="acq_data_in[49]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[50]" name="acq_data_in[50]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[51]" name="acq_data_in[51]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[52]" name="acq_data_in[52]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[53]" name="acq_data_in[53]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[54]" name="acq_data_in[54]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[55]" name="acq_data_in[55]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[56]" name="acq_data_in[56]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[57]" name="acq_data_in[57]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[58]" name="acq_data_in[58]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[59]" name="acq_data_in[59]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[60]" name="acq_data_in[60]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[61]" name="acq_data_in[61]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[62]" name="acq_data_in[62]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[63]" name="acq_data_in[63]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[64]" name="acq_data_in[64]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[65]" name="acq_data_in[65]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[66]" name="acq_data_in[66]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[67]" name="acq_data_in[67]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[68]" name="acq_data_in[68]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[69]" name="acq_data_in[69]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[70]" name="acq_data_in[70]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[71]" name="acq_data_in[71]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[72]" name="acq_data_in[72]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[73]" name="acq_data_in[73]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[74]" name="acq_data_in[74]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[75]" name="acq_data_in[75]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[76]" name="acq_data_in[76]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[77]" name="acq_data_in[77]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[78]" name="acq_data_in[78]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[79]" name="acq_data_in[79]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[80]" name="acq_data_in[80]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[81]" name="acq_data_in[81]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[82]" name="acq_data_in[82]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[83]" name="acq_data_in[83]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[84]" name="acq_data_in[84]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[85]" name="acq_data_in[85]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[86]" name="acq_data_in[86]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[87]" name="acq_data_in[87]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[88]" name="acq_data_in[88]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[89]" name="acq_data_in[89]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[90]" name="acq_data_in[90]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[91]" name="acq_data_in[91]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[92]" name="acq_data_in[92]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[93]" name="acq_data_in[93]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[94]" name="acq_data_in[94]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[23]" name="acq_data_in[23]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[24]" name="acq_data_in[24]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[25]" name="acq_data_in[25]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[26]" name="acq_data_in[26]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[27]" name="acq_data_in[27]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[28]" name="acq_data_in[28]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[29]" name="acq_data_in[29]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[30]" name="acq_data_in[30]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[31]" name="acq_data_in[31]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[32]" name="acq_data_in[32]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[33]" name="acq_data_in[33]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[34]" name="acq_data_in[34]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[35]" name="acq_data_in[35]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[36]" name="acq_data_in[36]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[37]" name="acq_data_in[37]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[38]" name="acq_data_in[38]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[39]" name="acq_data_in[39]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[40]" name="acq_data_in[40]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[41]" name="acq_data_in[41]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[42]" name="acq_data_in[42]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[43]" name="acq_data_in[43]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[44]" name="acq_data_in[44]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[45]" name="acq_data_in[45]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[46]" name="acq_data_in[46]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[47]" name="acq_data_in[47]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[48]" name="acq_data_in[48]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[49]" name="acq_data_in[49]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[50]" name="acq_data_in[50]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[51]" name="acq_data_in[51]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[52]" name="acq_data_in[52]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[53]" name="acq_data_in[53]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[54]" name="acq_data_in[54]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[55]" name="acq_data_in[55]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[56]" name="acq_data_in[56]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[57]" name="acq_data_in[57]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[58]" name="acq_data_in[58]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[59]" name="acq_data_in[59]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[60]" name="acq_data_in[60]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[61]" name="acq_data_in[61]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[62]" name="acq_data_in[62]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[63]" name="acq_data_in[63]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[64]" name="acq_data_in[64]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[65]" name="acq_data_in[65]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[66]" name="acq_data_in[66]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[67]" name="acq_data_in[67]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[68]" name="acq_data_in[68]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[69]" name="acq_data_in[69]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[70]" name="acq_data_in[70]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[71]" name="acq_data_in[71]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[72]" name="acq_data_in[72]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[73]" name="acq_data_in[73]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[74]" name="acq_data_in[74]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[75]" name="acq_data_in[75]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[76]" name="acq_data_in[76]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[77]" name="acq_data_in[77]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[78]" name="acq_data_in[78]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[79]" name="acq_data_in[79]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[80]" name="acq_data_in[80]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[81]" name="acq_data_in[81]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[82]" name="acq_data_in[82]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[83]" name="acq_data_in[83]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[84]" name="acq_data_in[84]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[85]" name="acq_data_in[85]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[86]" name="acq_data_in[86]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[87]" name="acq_data_in[87]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[88]" name="acq_data_in[88]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[89]" name="acq_data_in[89]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[90]" name="acq_data_in[90]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[91]" name="acq_data_in[91]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[92]" name="acq_data_in[92]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[93]" name="acq_data_in[93]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[94]" name="acq_data_in[94]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tLast" name="acq_data_in[95]" tap_mode="classic" type="unknown"/>
<wire alias="writeRequest.trigger" name="acq_data_in[96]" tap_mode="classic" type="unknown"/>
<wire alias="writeResponse.trigger" name="acq_data_in[97]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[98]" name="acq_data_in[98]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[99]" name="acq_data_in[99]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[100]" name="acq_data_in[100]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[101]" name="acq_data_in[101]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[102]" name="acq_data_in[102]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[103]" name="acq_data_in[103]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[104]" name="acq_data_in[104]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[105]" name="acq_data_in[105]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[106]" name="acq_data_in[106]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[107]" name="acq_data_in[107]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[108]" name="acq_data_in[108]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[109]" name="acq_data_in[109]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[110]" name="acq_data_in[110]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[111]" name="acq_data_in[111]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[112]" name="acq_data_in[112]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[113]" name="acq_data_in[113]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[114]" name="acq_data_in[114]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[115]" name="acq_data_in[115]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[116]" name="acq_data_in[116]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[117]" name="acq_data_in[117]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[118]" name="acq_data_in[118]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[119]" name="acq_data_in[119]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[120]" name="acq_data_in[120]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[121]" name="acq_data_in[121]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[122]" name="acq_data_in[122]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[123]" name="acq_data_in[123]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[124]" name="acq_data_in[124]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[125]" name="acq_data_in[125]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[126]" name="acq_data_in[126]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[127]" name="acq_data_in[127]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[98]" name="acq_data_in[98]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[99]" name="acq_data_in[99]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[100]" name="acq_data_in[100]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[101]" name="acq_data_in[101]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[102]" name="acq_data_in[102]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[103]" name="acq_data_in[103]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[104]" name="acq_data_in[104]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[105]" name="acq_data_in[105]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[106]" name="acq_data_in[106]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[107]" name="acq_data_in[107]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[108]" name="acq_data_in[108]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[109]" name="acq_data_in[109]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[110]" name="acq_data_in[110]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[111]" name="acq_data_in[111]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[112]" name="acq_data_in[112]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[113]" name="acq_data_in[113]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[114]" name="acq_data_in[114]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[115]" name="acq_data_in[115]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[116]" name="acq_data_in[116]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[117]" name="acq_data_in[117]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[118]" name="acq_data_in[118]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[119]" name="acq_data_in[119]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[120]" name="acq_data_in[120]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[121]" name="acq_data_in[121]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[122]" name="acq_data_in[122]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[123]" name="acq_data_in[123]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[124]" name="acq_data_in[124]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[125]" name="acq_data_in[125]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[126]" name="acq_data_in[126]" tap_mode="classic" type="unknown"/>
<wire alias="tester:bist|stp:i_bist_logicAnalyser|acq_data_in[127]" name="acq_data_in[127]" tap_mode="classic" type="unknown"/>
</data_input_vec>
<storage_qualifier_input_vec/>
</signal_vec>
635,7 → 635,7
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<bus alias="axiTxFSM" is_signal_inverted="no" link="all" name="acq_data_in[16..17]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
</bus>
644,7 → 644,7
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..54]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
677,6 → 677,8
<net is_signal_inverted="no" name="acq_data_in[52]"/>
<net is_signal_inverted="no" name="acq_data_in[53]"/>
<net is_signal_inverted="no" name="acq_data_in[54]"/>
</bus>
<bus alias="prbs" is_signal_inverted="no" link="all" name="acq_data_in[55..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[55]"/>
<net is_signal_inverted="no" name="acq_data_in[56]"/>
<net is_signal_inverted="no" name="acq_data_in[57]"/>
781,7 → 783,7
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<bus alias="axiTxFSM" is_signal_inverted="no" link="all" name="acq_data_in[16..17]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
</bus>
790,7 → 792,7
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..54]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
823,6 → 825,8
<net is_signal_inverted="no" name="acq_data_in[52]"/>
<net is_signal_inverted="no" name="acq_data_in[53]"/>
<net is_signal_inverted="no" name="acq_data_in[54]"/>
</bus>
<bus alias="prbs" is_signal_inverted="no" link="all" name="acq_data_in[55..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[55]"/>
<net is_signal_inverted="no" name="acq_data_in[56]"/>
<net is_signal_inverted="no" name="acq_data_in[57]"/>
908,15 → 912,17
<net is_signal_inverted="no" name="acq_trigger_in[0]"/>
</setup_view>
</presentation>
<trigger CRC="A1D452D4" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="false" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="rising edge" trigger_out="active high" trigger_type="circular">
<trigger CRC="1EAEA6CB" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2014/01/17 17:27:53 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="falling edge" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/>
<events use_custom_flow_control="no">
<level enabled="yes" name="condition1" type="basic"><power_up enabled="yes">
<level enabled="yes" name="condition1" type="basic">
<power_up enabled="yes">
</power_up><op_node/>
</level>
</events>
<storage_qualifier>
<transitional><pwr_up_transitional/>
<transitional>
<pwr_up_transitional/>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
934,6 → 940,10
<op_node/>
</storage_qualifier_level>
</storage_qualifier>
<log>
<data global_temp="1" name="log: 2014/01/17 17:32:31 #0" power_up_mode="false" sample_depth="0" trigger_position="-1"/>
<extradata/>
</log>
<storage_qualifier_events>
<storage_qualifier_level>
<power_up>
950,14 → 960,9
</power_up>
<op_node/>
</storage_qualifier_level>
<transitional>
<pwr_up_transitional/>
<transitional><pwr_up_transitional/>
</transitional>
</storage_qualifier_events>
<log>
<data global_temp="1" name="log: 2013/09/28 20:22:15 #0" power_up_mode="false" sample_depth="0" trigger_position="-1"/>
<extradata/>
</log>
</trigger>
</signal_set>
<position_info>
964,13 → 969,7
<single attribute="active tab" value="0"/>
</position_info>
</instance>
<mnemonics>
<table name="next_axiTxState_table" width="2">
<symbol name="idle" value="00"/>
<symbol name="payload" value="01"/>
<symbol name="endOfTx" value="10"/>
</table>
</mnemonics>
<mnemonics/>
<static_plugin_mnemonics/>
<global_info>
<single attribute="active instance" value="0"/>
980,8 → 979,8
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="jtag widget visible" value="1"/>
<multi attribute="column width" size="23" value="34,147,236,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
<multi attribute="frame size" size="2" value="1600,1178"/>
<multi attribute="column width" size="23" value="34,137,20,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
<multi attribute="frame size" size="2" value="1366,715"/>
<multi attribute="jtag widget size" size="2" value="398,145"/>
</global_info>
</session>

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