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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

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  • This comparison shows the changes necessary to convert path 
    /axi4_tlm_bfm/trunk
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/testbench/questa/waves.do
16,7 → 16,7
add wave -position end -expand -decimal sim:/user/writeRequest
add wave -position end -decimal sim:/user/readResponse
add wave -position end -decimal sim:/user/writeResponse
add wave -position end -format analog-step -height 80 -scale 0.00000003 sim:/user/axiMaster_out.tData
add wave -position end -unsigned -format analog-step -height 80 -scale 0.00000003 sim:/user/axiMaster_out.tData
 
run 80 ns;
 
/testbench/questa/simulate.sh
52,7 → 52,7
 
errorStr=`grep "\*\* Error: " ./simulate.log`
if [ `echo ${#errorStr}` -gt 0 ]
then echo "Errors exist. Exiting."; exit;
then echo "Errors exist. Refer simulate.log for more details. Exiting."; exit;
else vsim -t ps -do ./waves.do -voptargs="+acc" "work.user(rtl)";
fi
 
/rtl/axi4-stream-bfm-master.vhdl
59,12 → 59,12
-- axiSlave_out:buffer tAxi4Transactor_s2m;
symbolsPerTransfer:in t_cnt;
outstandingTransactions:out t_cnt;
outstandingTransactions:out t_cnt
/* Debug ports. */
dbg_cnt:out unsigned(9 downto 0);
dbg_axiRxFsm:out axiBfmStatesRx:=idle;
dbg_axiTxFsm:out axiBfmStatesTx:=idle
-- dbg_cnt:out unsigned(9 downto 0);
-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
-- dbg_axiTxFsm:out axiBfmStatesTx:=idle
);
end entity axiBfmMaster;
 
135,5 → 135,5
end if;
end process;
dbg_axiTxFsm<=axiTxState;
-- dbg_axiTxFsm<=axiTxState;
end architecture rtl;
/rtl/user.vhdl
98,11 → 98,7
axiMaster_out=>axiMaster_out,
symbolsPerTransfer=>symbolsPerTransfer,
outstandingTransactions=>outstandingTransactions,
dbg_cnt=>open,
dbg_axiRxFsm=>open,
dbg_axiTxFsm=>open
outstandingTransactions=>outstandingTransactions
);
/* Simulation Tester. */
126,22 → 122,19
/* Stimuli sequencer. */
sequencer: process(reset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in unsigned(31 downto 0)) is begin
procedure read(address:in t_addr) is begin
read(readRequest,address);
end procedure read;
procedure write(
address:in t_addr;
data:in t_msg
) is begin
write(writeRequest,address,data);
procedure write(data:in t_msg) is begin
write(request=>writeRequest, address=>(others=>'-'), data=>data);
end procedure write;
procedure writeStream(
data:in t_msg
) is begin
writeStream(writeRequest,data);
end procedure writeStream;
-- procedure writeStream(
-- data:in t_msg
-- ) is begin
-- writeStream(writeRequest,data);
-- end procedure writeStream;
variable isPktError:boolean;
158,7 → 151,7
elsif falling_edge(irq_write) then
if outstandingTransactions>0 then
uniform(seed0,seed1,rand0);
writeStream(to_unsigned(integer(rand0 * 2.0**31),64));
write(to_unsigned(integer(rand0 * 2.0**31),64));
else
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
/rtl/packages/pkg-axi-tlm.vhdl
180,7 → 180,7
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
library tauhop;
package transactor is new tauhop.tlm generic map(
t_addr=>unsigned(31 downto 0),
t_addr=>unsigned(31 downto 0), -- default assignment. Used only for non-stream interfaces.
t_msg=>unsigned(63 downto 0),
t_cnt=>unsigned(127 downto 0)
);
/rtl/packages/pkg-tlm.vhdl
60,18 → 60,13
procedure write(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr;
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
);
procedure writeStream(
signal request:inout t_bfm;
data:in t_msg
);
procedure read(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr
address:in t_addr -- used only for non-stream interfaces.
);
end package tlm;
 
78,7 → 73,7
package body tlm is
procedure write(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr;
address:in t_addr; -- used only for non-stream interfaces.
data:in t_msg
) is begin
request.address<=address;
86,17 → 81,9
request.trigger<=not request.trigger;
end procedure write;
procedure writeStream(
signal request:inout t_bfm;
data:in t_msg
) is begin
request.message<=data;
request.trigger<=not request.trigger;
end procedure writeStream;
procedure read(
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr
address:in t_addr -- used only for non-stream interfaces.
) is begin
request.address<=address;
request.trigger<=not request.trigger;

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