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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

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    /axi4_tlm_bfm
    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/trunk/rtl/axi4-stream-bfm-master.vhdl
71,6 → 71,8
/* Finite-state Machines. */
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
/* BFM signalling. */
signal i_readRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:i_transactor.t_bfm:=((others=>'0'),(others=>'0'),false);
88,6 → 90,19
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
/* debug only. */
/*if falling_edge(aclk) then
if not n_areset then outstandingTransactions<=symbolsPerTransfer;
else
if outstandingTransactions<1 then
outstandingTransactions<=symbolsPerTransfer;
report "No more pending transactions." severity note;
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
end if;
end if;
end if;
*/
end process;
/* next-state logic for AXI4-Stream Master Tx BFM. */
94,17 → 109,18
axi_bfmTx_ns: process(all) is begin
axiTxState<=next_axiTxState;
if not n_areset then axiTxState<=idle; end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
if not n_areset then axiTxState<=idle;
else
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
end if;
end process axi_bfmTx_ns;
/* output logic for AXI4-Stream Master Tx BFM. */
111,20 → 127,27
axi_bfmTx_op: process(all) is begin
i_writeResponse<=writeResponse;
axiMaster_out.tValid<=false;
axiMaster_out.tLast<=false;
axiMaster_out.tData<=(others=>'Z');
i_axiMaster_out.tValid<=false;
i_axiMaster_out.tLast<=false;
i_axiMaster_out.tData<=(others=>'Z');
i_writeResponse.trigger<=false;
if writeRequest.trigger xor i_writeRequest.trigger then
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
/* if writeRequest.trigger xor i_writeRequest.trigger then
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
end if;
*/
null;
when payload=>
axiMaster_out.tValid<=true;
axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tData<=writeRequest.message;
i_axiMaster_out.tValid<=true;
if axiMaster_in.tReady then
i_writeResponse.trigger<=true;
131,18 → 154,20
end if;
/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */
if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if;
if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if;
when others=> null;
end case;
end process axi_bfmTx_op;
axiMaster_out<=i_axiMaster_out;
/* state registers and pipelines for AXI4-Stream Tx BFM. */
process(n_areset,aclk) is begin
if not n_areset then next_axiTxState<=idle;
elsif falling_edge(aclk) then
--if not n_areset then next_axiTxState<=idle;
if falling_edge(aclk) then
next_axiTxState<=axiTxState;
i_writeRequest<=writeRequest;
--axiMaster_out<=i_axiMaster_out;
end if;
end process;
/trunk/rtl/user.vhdl
164,7 → 164,23
/* Data transmitter. */
sequencer: process(nReset,irq_write) is
sequencer_ns: process(all) is begin
txFSM<=i_txFSM;
if not nReset then txFSM<=idle;
else
case i_txFSM is
when idle=>
if outstandingTransactions>0 then txFSM<=transmitting; end if;
when transmitting=>
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=> null;
end case;
end if;
end process sequencer_ns;
sequencer_op: process(nReset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in i_transactor.t_addr) is begin
i_transactor.read(readRequest,address);
190,32 → 206,25
/* synthesis translate_off */
rv0.InitSeed(rv0'instance_name);
/* synthesis translate_on */
txFSM<=idle;
elsif falling_edge(irq_write) then
case txFSM is
when idle=>
if outstandingTransactions>0 then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
txFSM<=transmitting;
end if;
when transmitting=>
if writeResponse.trigger then
if txFSM/=i_txFSM or writeResponse.trigger then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
end if;
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=>null;
end case;
end if;
end process sequencer;
end process sequencer_op;
sequencer_regs: process(irq_write) is begin
if falling_edge(irq_write) then
i_txFSM<=txFSM;
end if;
end process sequencer_regs;
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
process(nReset,irq_write) is
/* synthesis translate_off */
/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
36,15 → 36,15
from http://www.opencores.org/lgpl.shtml.
*/
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;
--library tauhop; use tauhop.axiTransactor.all;
 
--/* TODO remove once generic packages are supported. */
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
 
entity axiBfmMaster is --generic(constant maxTransactions:positive);
entity axiBfmMaster is
port(aclk,n_areset:in std_ulogic;
/* BFM signalling. */
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false); -- this is tauhop.transactor.t_bfm.
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false);
readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
/* AXI Master interface */
56,12 → 56,12
-- axiSlave_out:buffer tAxi4Transactor_s2m;
symbolsPerTransfer:in t_cnt;
outstandingTransactions:buffer t_cnt
outstandingTransactions:buffer t_cnt;
/* Debug ports. */
-- dbg_cnt:out unsigned(9 downto 0);
-- dbg_axiRxFsm:out axiBfmStatesRx:=idle;
-- dbg_axiTxFsm:out axiBfmStatesTx:=idle
dbg_axiTxFsm:out axiBfmStatesTx:=idle
);
end entity axiBfmMaster;
 
78,6 → 78,11
begin
/* Transaction counter. */
process(n_areset,symbolsPerTransfer,aclk) is begin
/* Using synchronous reset will meet timing. However, because outstandingTransactions is a huge
register set, using asynchronous reset will violate timing.
FIXME Try and close timing even with asynchronous reset applied on outstandingTransactions.
Using asynchronous reset will help to lower power.
*/
if not n_areset then outstandingTransactions<=symbolsPerTransfer;
elsif falling_edge(aclk) then
if outstandingTransactions<1 then
92,17 → 97,18
axi_bfmTx_ns: process(all) is begin
axiTxState<=next_axiTxState;
if not n_areset then axiTxState<=idle; end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
if not n_areset then axiTxState<=idle;
else
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if;
when payload=>
if outstandingTransactions<1 then axiTxState<=endOfTx; end if;
when endOfTx=>
axiTxState<=idle;
when others=>axiTxState<=idle;
end case;
end if;
end process axi_bfmTx_ns;
/* output logic for AXI4-Stream Master Tx BFM. */
114,15 → 120,15
axiMaster_out.tData<=(others=>'Z');
i_writeResponse.trigger<=false;
if writeRequest.trigger xor i_writeRequest.trigger then
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
end if;
case next_axiTxState is
when idle=>
if writeRequest.trigger xor i_writeRequest.trigger then
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
end if;
when payload=>
axiMaster_out.tData<=writeRequest.message;
axiMaster_out.tValid<=true;
axiMaster_out.tData<=writeRequest.message;
if axiMaster_in.tReady then
i_writeResponse.trigger<=true;
134,11 → 140,9
end case;
end process axi_bfmTx_op;
/* state registers and pipelines for AXI4-Stream Tx BFM. */
process(n_areset,aclk) is begin
if not n_areset then next_axiTxState<=idle;
elsif falling_edge(aclk) then
if falling_edge(aclk) then
next_axiTxState<=axiTxState;
i_writeRequest<=writeRequest;
end if;
149,4 → 153,6
writeResponse<=i_writeResponse;
end if;
end process;
dbg_axiTxFSM<=axiTxState;
end architecture rtl;
/trunk/rtl/quartus-synthesis/pkg-axi-tlm.vhdl
160,11 → 160,28
-- cActive:
-- end record tAxiTransactor_lp;
type axiBfmStatesTx is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
type t_fsm is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
type axiBfmStatesTx is (idle,payload,endOfTx);
type axiBfmStatesRx is (idle,checkAddr,startOfPacket,payload);
attribute enum_encoding:string;
attribute enum_encoding of axiBfmStatesTx:type is "00 01 10";
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector;
end package axiTLM;
 
package body axiTLM is
function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector is
variable r:std_logic_vector(1 downto 0);
begin
case fsm is
when idle=> r:=2x"0";
when payload=> r:=2x"1";
when endOfTx=> r:=2x"2";
when others=> null;
end case;
return r;
end function to_std_logic_vector;
end package body axiTLM;
 
 
/trunk/rtl/quartus-synthesis/stp.vhd
94,8 → 94,8
sld_enable_advanced_trigger => 0,
sld_mem_address_bits => 12,
sld_node_crc_bits => 32,
sld_node_crc_hiword => 28809,
sld_node_crc_loword => 11476,
sld_node_crc_hiword => 41428,
sld_node_crc_loword => 21204,
sld_node_info => 1076736,
sld_ram_block_type => "Auto",
sld_sample_depth => 4096,
130,13 → 130,13
-- Retrieval info: PRIVATE: TRIGGER_WIDTH_SPIN STRING ""
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: SLD_ADVANCED_TRIGGER_ENTITY STRING "basic,1,"
-- Retrieval info: CONSTANT: SLD_DATA_BITS NUMERIC "128"
-- Retrieval info: CONSTANT: SLD_DATA_BITS NUMERIC "80"
-- Retrieval info: CONSTANT: SLD_DATA_BIT_CNTR_BITS NUMERIC "8"
-- Retrieval info: CONSTANT: SLD_ENABLE_ADVANCED_TRIGGER NUMERIC "0"
-- Retrieval info: CONSTANT: SLD_MEM_ADDRESS_BITS NUMERIC "12"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_BITS NUMERIC "32"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_HIWORD NUMERIC "28809"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_LOWORD NUMERIC "11476"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_HIWORD NUMERIC "41428"
-- Retrieval info: CONSTANT: SLD_NODE_CRC_LOWORD NUMERIC "21204"
-- Retrieval info: CONSTANT: SLD_NODE_INFO NUMERIC "1076736"
-- Retrieval info: CONSTANT: SLD_RAM_BLOCK_TYPE STRING "Auto"
-- Retrieval info: CONSTANT: SLD_SAMPLE_DEPTH NUMERIC "4096"
147,11 → 147,11
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL NUMERIC "1"
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL_PIPELINE NUMERIC "1"
-- Retrieval info: USED_PORT: acq_clk 0 0 0 0 INPUT NODEFVAL "acq_clk"
-- Retrieval info: USED_PORT: acq_data_in 0 0 128 0 INPUT NODEFVAL "acq_data_in[127..0]"
-- Retrieval info: USED_PORT: acq_data_in 0 0 80 0 INPUT NODEFVAL "acq_data_in[79..0]"
-- Retrieval info: USED_PORT: acq_trigger_in 0 0 1 0 INPUT NODEFVAL "acq_trigger_in[0..0]"
-- Retrieval info: USED_PORT: trigger_in 0 0 0 0 INPUT NODEFVAL "trigger_in"
-- Retrieval info: CONNECT: @acq_clk 0 0 0 0 acq_clk 0 0 0 0
-- Retrieval info: CONNECT: @acq_data_in 0 0 128 0 acq_data_in 0 0 128 0
-- Retrieval info: CONNECT: @acq_data_in 0 0 80 0 acq_data_in 0 0 80 0
-- Retrieval info: CONNECT: @acq_trigger_in 0 0 1 0 acq_trigger_in 0 0 1 0
-- Retrieval info: CONNECT: @trigger_in 0 0 0 0 trigger_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp.vhd TRUE
/trunk/rtl/quartus-synthesis/user.vhdl
78,7 → 78,10
/* synthesis translate_off */
signal clk,nReset:std_ulogic:='0';
/* synthesis translate_on */
signal testerClk:std_ulogic;
--signal trigger:boolean;
signal dbg_axiTxFSM:axiBfmStatesTx;
signal anlysr_dataIn:std_logic_vector(127 downto 0);
signal anlysr_trigger:std_ulogic;
101,7 → 104,8
axiMaster_out=>axiMaster_out,
symbolsPerTransfer=>symbolsPerTransfer,
outstandingTransactions=>outstandingTransactions
outstandingTransactions=>outstandingTransactions,
dbg_axiTxFSM=>dbg_axiTxFSM
);
/* Interrupt-request generator. */
108,6 → 112,14
irq_write<=clk when nReset else '0';
/* Simulation Tester. */
/* PLL to generate tester's clock. */
f100MHz: entity altera.pll(syn) port map(
areset=>not nReset,
inclk0=>clk,
c0=>testerClk,
locked=>open
);
/* synthesis translate_off */
clk<=not clk after 10 ps;
process is begin
118,24 → 130,24
end process;
/* synthesis translate_on */
/* Hardware tester. */
/* directly instantiated if configurations is not used.
component-instantiated if configurations are used.
/*
por: process(reset,clk) is
variable cnt:unsigned(7 downto 0):=x"ff";
begin
if not reset then cnt<=(others=>'1');
elsif rising_edge(clk) then
nReset<='1';
if cnt>x"8" then nReset<='0'; end if;
if cnt>0 then cnt:=cnt-1; end if;
end if;
end process por;
*/
-- i_bist: entity work.framer_bist(tc1)
/*i_bist: entity work.framer_bist(tc2_randomised)
generic map(interPktGap=>3, pktSize=>pktSize)
port map(nReset=>nReset, clk=>clk,
trigger=>trigger,
txDataIn=>txDataIn,
txOut=>data(0),
dataFault=>dataFault, crcFault=>crcFault
);
*/
/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
--trigger<=clk='1';
--anlysr_trigger<='1' when trigger else '0';
anlysr_trigger<='1' when writeRequest.trigger else '0';
/* Disable this for synthesis as this is not currently synthesisable.
145,23 → 157,29
--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length);
/* synthesis translate_on */
anlysr_dataIn(0)<='1' when nReset else '0';
anlysr_dataIn(1)<='1' when irq_write else '0';
anlysr_dataIn(2)<='1' when axiMaster_in.tReady else '0';
anlysr_dataIn(3)<='1' when axiMaster_out.tValid else '0';
anlysr_dataIn(67 downto 4)<=std_logic_vector(axiMaster_out.tData);
anlysr_dataIn(71 downto 68)<=std_logic_vector(axiMaster_out.tStrb);
anlysr_dataIn(75 downto 72)<=std_logic_vector(axiMaster_out.tKeep);
anlysr_dataIn(76)<='1' when axiMaster_out.tLast else '0';
--anlysr_dataIn(2)<='1' when axiMaster_out.tValid else '0';
anlysr_dataIn(77)<='1' when writeRequest.trigger else '0';
anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>;
anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
anlysr_dataIn(18)<='1' when clk else '0';
anlysr_dataIn(19)<='1' when nReset else '0';
anlysr_dataIn(20)<='1' when irq_write else '0';
anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
anlysr_dataIn(anlysr_dataIn'high downto 78)<=(others=>'0');
anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
/* Simulate only if you have compiled Altera's simulation libraries. */
i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
acq_clk=>clk,
acq_clk=>testerClk,
acq_data_in=>anlysr_dataIn,
acq_trigger_in=>"1",
trigger_in=>anlysr_trigger
219,10 → 237,36
/* synthesis translate_on */
/* Synthesisable stimuli sequencer. */
axiMaster_in.tReady<=true when axiMaster_out.tValid and falling_edge(clk);
process(clk) is begin
if falling_edge(clk) then
axiMaster_in.tReady<=false;
--if axiMaster_out.tValid and not axiMaster_out.tLast then
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
axiMaster_in.tReady<=true;
end if;
end if;
end process;
/* Data transmitter. */
sequencer: process(nReset,irq_write) is
sequencer_ns: process(all) is begin
txFSM<=i_txFSM;
if not nReset then txFSM<=idle;
else
case i_txFSM is
when idle=>
if outstandingTransactions>0 then txFSM<=transmitting; end if;
when transmitting=>
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=> null;
end case;
end if;
end process sequencer_ns;
/* Data transmitter. */
sequencer_op: process(nReset,irq_write) is
/* Local procedures to map BFM signals with the package procedure. */
procedure read(address:in t_addr) is begin
read(readRequest,address);
252,20 → 296,11
rv0.InitSeed(rv0'instance_name);
/* synthesis translate_on */
txFSM<=idle;
--txFSM<=idle;
elsif falling_edge(irq_write) then
case txFSM is
when idle=>
if outstandingTransactions>0 then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
write(rand0);
txFSM<=transmitting;
end if;
when transmitting=>
if writeResponse.trigger then
if txFSM/=i_txFSM or writeResponse.trigger then
/* synthesis translate_off */
write(rv0.RandSigned(axiMaster_out.tData'length));
/* synthesis translate_on */
272,15 → 307,18
write(rand0);
rand0:=rand0+1;
end if;
if axiMaster_out.tLast then
txFSM<=idle;
end if;
when others=>null;
end case;
end if;
end process sequencer;
end process sequencer_op;
sequencer_regs: process(irq_write) is begin
if falling_edge(irq_write) then
i_txFSM<=txFSM;
end if;
end process sequencer_regs;
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
process(nReset,irq_write) is
/* synthesis translate_off */
312,7 → 350,7
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
/* synthesis translate_on */
symbolsPerTransfer<=128x"8";
symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
end if;
end if;
end process;
/trunk/tester/questa/waves.do
12,6 → 12,7
add wave -position end sim:/user/irq_write
add wave -position end -expand -hexadecimal sim:/user/axiMaster_in
add wave -position end -expand -hexadecimal sim:/user/axiMaster_out
add wave -position end -expand -hexadecimal sim:/user/axiMaster/i_axiMaster_out
add wave -position end -decimal sim:/user/readRequest
add wave -position end -expand -hexadecimal sim:/user/writeRequest
add wave -position end -decimal sim:/user/readResponse
18,6 → 19,7
add wave -position end -expand -hexadecimal sim:/user/axiMaster/i_writeResponse
add wave -position end -expand -hexadecimal sim:/user/writeResponse
add wave -position end sim:/user/txFSM
add wave -position end sim:/user/i_txFSM
add wave -position end -unsigned -format analog-step -height 80 -scale 0.4e-17 sim:/user/axiMaster_out.tData
 
run 80 ns;
/trunk/tester/questa/simulate.sh
2,8 → 2,10
#
# Example bash script for Mentor Graphics QuestaSim/ModelSim simulation.
#
# Author: Daniel C.K. Kho <daniel.kho@tauhop.com>
# Copyright© 2012-2013 Daniel C.K. Kho <daniel.kho@tauhop.com>
# Author(s):
# - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
#
# Copyright (C) 2012-2013 Authors and OPENCORES.ORG
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
40,7 → 42,8
vcom -2008 -work osvvm ../../rtl/packages/os-vvm/SortListPkg_int.vhd \
../../rtl/packages/os-vvm/RandomBasePkg.vhd \
../../rtl/packages/os-vvm/RandomPkg.vhd \
../../rtl/packages/os-vvm/CoveragePkg.vhd;
../../rtl/packages/os-vvm/CoveragePkg.vhd \
| tee -ai ./simulate.log;
 
vcom -2008 -work tauhop ../../rtl/packages/pkg-tlm.vhdl \
../../rtl/packages/pkg-axi-tlm.vhdl \
/trunk/workspace/quartus/axi4-tlm.qsf
54,14 → 54,17
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/pkg-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/pkg-axi-tlm.vhdl"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl"
set_global_assignment -name VHDL_FILE ../../rtl/quartus-synthesis/user.vhdl
set_global_assignment -name VHDL_FILE ../../rtl/quartus-synthesis/stp.vhd
set_location_assignment PIN_N2 -to nReset
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/user.vhdl"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/stp.vhd"
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/pll.vhd"
#set_location_assignment PIN_N2 -to nReset
set_location_assignment PIN_F1 -to reset
set_location_assignment PIN_V9 -to clk
 
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/trunk/workspace/quartus/synthesise.sh
1,4 → 1,50
#!/bin/bash
quartus_sh --flow compile axi4-tlm
quartus_pgm -c 'USB-Blaster [1-1.6]' -m jtag -o 'p;./output_files/axi4-tlm.sof'
quartus_stpw ./waves.stp &
#
# Example bash script for Quartus synthesis, place-and-route, and design
# assembly.
#
# Author(s):
# - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
#
# Copyright (C) 2012-2013 Authors and OPENCORES.ORG
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
# This notice and disclaimer must be retained as part of this text at all times.
#
# @dependencies:
# @designer: Daniel C.K. Kho [daniel.kho@gmail.com] | [daniel.kho@tauhop.com]
# @history: @see Mercurial log for full list of changes.
#
# @Description:
#
 
quartus_sh --flow compile axi4-tlm;
 
errorStr=`grep 'Error (' ./output_files/*.rpt`
if [ `echo ${#errorStr}` -gt 0 ]
then echo "Build error(s) exist. Refer to report files in the output_files directory for more details. Exiting."; exit;
else
echo $(date "+[%Y-%m-%d %H:%M:%S]: Configuring device...");
quartus_pgm -c 'USB-Blaster [1-1.6]' -m jtag -o 'p;./output_files/axi4-tlm.sof';
fi
 
errorStr=`grep 'Error (' ./output_files/*.rpt`
if [ `echo ${#errorStr}` -gt 0 ]
then echo "Configuration error(s) exist. Refer to report files in the output_files directory for more details. Exiting."; exit;
else
echo $(date "+[%Y-%m-%d %H:%M:%S]: Loading waveform session...");
quartus_stpw ./waves.stp &
fi
/trunk/workspace/quartus/waves.stp
1,22 → 1,22
<session jtag_chain="USB-Blaster [1-1.6]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="">
<display_tree gui_logging_enabled="1">
<display_branch instance="signaltap_megafunction_0" signal_set="signal_set: 2013/09/18 00:00:51 #0" trigger="trigger: 2013/09/18 00:00:51 #1"/>
<display_tree gui_logging_enabled="0">
<display_branch instance="signaltap_megafunction_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
</display_tree>
<instance entity_name="sld_signaltap" is_expanded="true" name="signaltap_megafunction_0" source_file="sld_signaltap.vhd">
<node_ip_info instance_id="0" mfg_id="110" node_id="2" version="6"/>
<signal_set is_expanded="true" name="signal_set: 2013/09/18 00:00:51 #0">
<signal_set is_expanded="true" name="signal_set: 2013/09/25 02:14:11 #0">
<clock name="stp:i_bistFramer_stp_analyser|acq_clk" polarity="posedge" tap_mode="classic"/>
<config ram_type="AUTO" reserved_data_nodes="128" reserved_trigger_nodes="1" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="stp:i_bistFramer_stp_analyser|trigger_in" trigger_in_tap_mode="classic" trigger_out_enable="no" trigger_out_node=""/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire alias="writeRequest.trigger" name="acq_trigger_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_trigger_in[0]" name="acq_trigger_in[0]" tap_mode="classic" type="unknown"/>
</trigger_input_vec>
<data_input_vec>
<wire alias="nReset" name="acq_data_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="irq_write" name="acq_data_in[1]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_in.tReady" name="acq_data_in[2]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tValid" name="acq_data_in[3]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[0]" name="acq_data_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[1]" name="acq_data_in[1]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[2]" name="acq_data_in[2]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[3]" name="acq_data_in[3]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[4]" name="acq_data_in[4]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[5]" name="acq_data_in[5]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[6]" name="acq_data_in[6]" tap_mode="classic" type="unknown"/>
31,11 → 31,11
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[15]" name="acq_data_in[15]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[16]" name="acq_data_in[16]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[17]" name="acq_data_in[17]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[18]" name="acq_data_in[18]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[19]" name="acq_data_in[19]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[20]" name="acq_data_in[20]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[21]" name="acq_data_in[21]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[22]" name="acq_data_in[22]" tap_mode="classic" type="unknown"/>
<wire alias="clk" name="acq_data_in[18]" tap_mode="classic" type="unknown"/>
<wire alias="nReset" name="acq_data_in[19]" tap_mode="classic" type="unknown"/>
<wire alias="irq_write" name="acq_data_in[20]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_in.tReady" name="acq_data_in[21]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tValid" name="acq_data_in[22]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[23]" name="acq_data_in[23]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[24]" name="acq_data_in[24]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[25]" name="acq_data_in[25]" tap_mode="classic" type="unknown"/>
89,7 → 89,7
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[73]" name="acq_data_in[73]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[74]" name="acq_data_in[74]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[75]" name="acq_data_in[75]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tLast" name="acq_data_in[76]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[76]" name="acq_data_in[76]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[77]" name="acq_data_in[77]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[78]" name="acq_data_in[78]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[79]" name="acq_data_in[79]" tap_mode="classic" type="unknown"/>
108,9 → 108,9
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[92]" name="acq_data_in[92]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[93]" name="acq_data_in[93]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[94]" name="acq_data_in[94]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[95]" name="acq_data_in[95]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[96]" name="acq_data_in[96]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[97]" name="acq_data_in[97]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tLast" name="acq_data_in[95]" tap_mode="classic" type="unknown"/>
<wire alias="writeRequest.trigger" name="acq_data_in[96]" tap_mode="classic" type="unknown"/>
<wire alias="writeResponse.trigger" name="acq_data_in[97]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[98]" name="acq_data_in[98]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[99]" name="acq_data_in[99]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[100]" name="acq_data_in[100]" tap_mode="classic" type="unknown"/>
146,15 → 146,17
</signal_vec>
<presentation>
<data_view>
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[4..67]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<bus alias="symbolsPerTransfer" is_signal_inverted="no" link="all" name="acq_data_in[0..7]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<net is_signal_inverted="no" name="acq_data_in[4]"/>
<net is_signal_inverted="no" name="acq_data_in[5]"/>
<net is_signal_inverted="no" name="acq_data_in[6]"/>
<net is_signal_inverted="no" name="acq_data_in[7]"/>
</bus>
<bus alias="outstandingTransactions" is_signal_inverted="no" link="all" name="acq_data_in[8..15]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[8]"/>
<net is_signal_inverted="no" name="acq_data_in[9]"/>
<net is_signal_inverted="no" name="acq_data_in[10]"/>
163,13 → 165,17
<net is_signal_inverted="no" name="acq_data_in[13]"/>
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
215,21 → 221,15
<net is_signal_inverted="no" name="acq_data_in[65]"/>
<net is_signal_inverted="no" name="acq_data_in[66]"/>
<net is_signal_inverted="no" name="acq_data_in[67]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[68..71]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[68]"/>
<net is_signal_inverted="no" name="acq_data_in[69]"/>
<net is_signal_inverted="no" name="acq_data_in[70]"/>
<net is_signal_inverted="no" name="acq_data_in[71]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[72..75]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[72]"/>
<net is_signal_inverted="no" name="acq_data_in[73]"/>
<net is_signal_inverted="no" name="acq_data_in[74]"/>
<net is_signal_inverted="no" name="acq_data_in[75]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[77..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<net is_signal_inverted="no" name="acq_data_in[77]"/>
<net is_signal_inverted="no" name="acq_data_in[78]"/>
<net is_signal_inverted="no" name="acq_data_in[79]"/>
240,17 → 240,23
<net is_signal_inverted="no" name="acq_data_in[84]"/>
<net is_signal_inverted="no" name="acq_data_in[85]"/>
<net is_signal_inverted="no" name="acq_data_in[86]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[87..90]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[87]"/>
<net is_signal_inverted="no" name="acq_data_in[88]"/>
<net is_signal_inverted="no" name="acq_data_in[89]"/>
<net is_signal_inverted="no" name="acq_data_in[90]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[91..94]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[91]"/>
<net is_signal_inverted="no" name="acq_data_in[92]"/>
<net is_signal_inverted="no" name="acq_data_in[93]"/>
<net is_signal_inverted="no" name="acq_data_in[94]"/>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
284,15 → 290,17
</bus>
</data_view>
<setup_view>
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[4..67]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<bus alias="symbolsPerTransfer" is_signal_inverted="no" link="all" name="acq_data_in[0..7]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<net is_signal_inverted="no" name="acq_data_in[4]"/>
<net is_signal_inverted="no" name="acq_data_in[5]"/>
<net is_signal_inverted="no" name="acq_data_in[6]"/>
<net is_signal_inverted="no" name="acq_data_in[7]"/>
</bus>
<bus alias="outstandingTransactions" is_signal_inverted="no" link="all" name="acq_data_in[8..15]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[8]"/>
<net is_signal_inverted="no" name="acq_data_in[9]"/>
<net is_signal_inverted="no" name="acq_data_in[10]"/>
301,13 → 309,17
<net is_signal_inverted="no" name="acq_data_in[13]"/>
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
353,21 → 365,15
<net is_signal_inverted="no" name="acq_data_in[65]"/>
<net is_signal_inverted="no" name="acq_data_in[66]"/>
<net is_signal_inverted="no" name="acq_data_in[67]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[68..71]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[68]"/>
<net is_signal_inverted="no" name="acq_data_in[69]"/>
<net is_signal_inverted="no" name="acq_data_in[70]"/>
<net is_signal_inverted="no" name="acq_data_in[71]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[72..75]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[72]"/>
<net is_signal_inverted="no" name="acq_data_in[73]"/>
<net is_signal_inverted="no" name="acq_data_in[74]"/>
<net is_signal_inverted="no" name="acq_data_in[75]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[77..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<net is_signal_inverted="no" name="acq_data_in[77]"/>
<net is_signal_inverted="no" name="acq_data_in[78]"/>
<net is_signal_inverted="no" name="acq_data_in[79]"/>
378,17 → 384,23
<net is_signal_inverted="no" name="acq_data_in[84]"/>
<net is_signal_inverted="no" name="acq_data_in[85]"/>
<net is_signal_inverted="no" name="acq_data_in[86]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[87..90]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[87]"/>
<net is_signal_inverted="no" name="acq_data_in[88]"/>
<net is_signal_inverted="no" name="acq_data_in[89]"/>
<net is_signal_inverted="no" name="acq_data_in[90]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[91..94]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[91]"/>
<net is_signal_inverted="no" name="acq_data_in[92]"/>
<net is_signal_inverted="no" name="acq_data_in[93]"/>
<net is_signal_inverted="no" name="acq_data_in[94]"/>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..127]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
423,15 → 435,17
<net is_signal_inverted="no" name="acq_trigger_in[0]"/>
</setup_view>
</presentation>
<trigger CRC="70892CD4" gap_record="true" is_expanded="true" name="trigger: 2013/09/18 00:00:51 #1" position="pre" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_port_is_pin="false" storage_qualifier_port_tap_mode="classic" trigger_in="either edge" trigger_out="active high" trigger_type="circular">
<trigger CRC="A1D452D4" gap_record="true" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_port_is_pin="true" storage_qualifier_port_tap_mode="classic" trigger_in="falling edge" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" trigger_in="dont_care" trigger_out="active high"/>
<events use_custom_flow_control="no">
<level type="basic"><power_up>
<level type="basic">
<power_up>
</power_up><op_node/>
</level>
</events>
<storage_qualifier>
<transitional><pwr_up_transitional/>
<transitional>
<pwr_up_transitional/>
</transitional>
</storage_qualifier>
<storage_qualifier_events>
450,26 → 464,521
</power_up>
<op_node/>
</storage_qualifier_level>
<transitional><pwr_up_transitional/>
</transitional>
</storage_qualifier_events>
<log>
<data name="log: 2013/09/28 19:27:15 #0" power_up_mode="false" sample_depth="0" trigger_position="-1"/>
<extradata/>
</log>
</trigger>
</signal_set>
<signal_set global_temp="1" is_expanded="true" name="signal_set: 2013/09/25 02:14:11 #0">
<clock name="stp:i_bistFramer_stp_analyser|acq_clk" polarity="posedge" tap_mode="classic"/>
<config ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="4096" trigger_in_enable="yes" trigger_in_node="stp:i_bistFramer_stp_analyser|trigger_in" trigger_in_tap_mode="classic" trigger_out_enable="no"/>
<top_entity/>
<signal_vec>
<trigger_input_vec>
<wire alias="stp:i_bistFramer_stp_analyser|acq_trigger_in[0]" name="acq_trigger_in[0]" tap_mode="classic" type="unknown"/>
</trigger_input_vec>
<data_input_vec>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[0]" name="acq_data_in[0]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[1]" name="acq_data_in[1]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[2]" name="acq_data_in[2]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[3]" name="acq_data_in[3]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[4]" name="acq_data_in[4]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[5]" name="acq_data_in[5]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[6]" name="acq_data_in[6]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[7]" name="acq_data_in[7]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[8]" name="acq_data_in[8]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[9]" name="acq_data_in[9]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[10]" name="acq_data_in[10]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[11]" name="acq_data_in[11]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[12]" name="acq_data_in[12]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[13]" name="acq_data_in[13]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[14]" name="acq_data_in[14]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[15]" name="acq_data_in[15]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[16]" name="acq_data_in[16]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[17]" name="acq_data_in[17]" tap_mode="classic" type="unknown"/>
<wire alias="clk" name="acq_data_in[18]" tap_mode="classic" type="unknown"/>
<wire alias="nReset" name="acq_data_in[19]" tap_mode="classic" type="unknown"/>
<wire alias="irq_write" name="acq_data_in[20]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_in.tReady" name="acq_data_in[21]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tValid" name="acq_data_in[22]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[23]" name="acq_data_in[23]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[24]" name="acq_data_in[24]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[25]" name="acq_data_in[25]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[26]" name="acq_data_in[26]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[27]" name="acq_data_in[27]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[28]" name="acq_data_in[28]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[29]" name="acq_data_in[29]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[30]" name="acq_data_in[30]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[31]" name="acq_data_in[31]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[32]" name="acq_data_in[32]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[33]" name="acq_data_in[33]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[34]" name="acq_data_in[34]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[35]" name="acq_data_in[35]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[36]" name="acq_data_in[36]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[37]" name="acq_data_in[37]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[38]" name="acq_data_in[38]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[39]" name="acq_data_in[39]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[40]" name="acq_data_in[40]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[41]" name="acq_data_in[41]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[42]" name="acq_data_in[42]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[43]" name="acq_data_in[43]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[44]" name="acq_data_in[44]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[45]" name="acq_data_in[45]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[46]" name="acq_data_in[46]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[47]" name="acq_data_in[47]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[48]" name="acq_data_in[48]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[49]" name="acq_data_in[49]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[50]" name="acq_data_in[50]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[51]" name="acq_data_in[51]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[52]" name="acq_data_in[52]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[53]" name="acq_data_in[53]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[54]" name="acq_data_in[54]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[55]" name="acq_data_in[55]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[56]" name="acq_data_in[56]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[57]" name="acq_data_in[57]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[58]" name="acq_data_in[58]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[59]" name="acq_data_in[59]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[60]" name="acq_data_in[60]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[61]" name="acq_data_in[61]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[62]" name="acq_data_in[62]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[63]" name="acq_data_in[63]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[64]" name="acq_data_in[64]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[65]" name="acq_data_in[65]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[66]" name="acq_data_in[66]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[67]" name="acq_data_in[67]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[68]" name="acq_data_in[68]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[69]" name="acq_data_in[69]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[70]" name="acq_data_in[70]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[71]" name="acq_data_in[71]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[72]" name="acq_data_in[72]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[73]" name="acq_data_in[73]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[74]" name="acq_data_in[74]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[75]" name="acq_data_in[75]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[76]" name="acq_data_in[76]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[77]" name="acq_data_in[77]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[78]" name="acq_data_in[78]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[79]" name="acq_data_in[79]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[80]" name="acq_data_in[80]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[81]" name="acq_data_in[81]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[82]" name="acq_data_in[82]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[83]" name="acq_data_in[83]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[84]" name="acq_data_in[84]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[85]" name="acq_data_in[85]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[86]" name="acq_data_in[86]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[87]" name="acq_data_in[87]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[88]" name="acq_data_in[88]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[89]" name="acq_data_in[89]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[90]" name="acq_data_in[90]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[91]" name="acq_data_in[91]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[92]" name="acq_data_in[92]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[93]" name="acq_data_in[93]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[94]" name="acq_data_in[94]" tap_mode="classic" type="unknown"/>
<wire alias="axiMaster_out.tLast" name="acq_data_in[95]" tap_mode="classic" type="unknown"/>
<wire alias="writeRequest.trigger" name="acq_data_in[96]" tap_mode="classic" type="unknown"/>
<wire alias="writeResponse.trigger" name="acq_data_in[97]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[98]" name="acq_data_in[98]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[99]" name="acq_data_in[99]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[100]" name="acq_data_in[100]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[101]" name="acq_data_in[101]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[102]" name="acq_data_in[102]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[103]" name="acq_data_in[103]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[104]" name="acq_data_in[104]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[105]" name="acq_data_in[105]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[106]" name="acq_data_in[106]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[107]" name="acq_data_in[107]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[108]" name="acq_data_in[108]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[109]" name="acq_data_in[109]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[110]" name="acq_data_in[110]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[111]" name="acq_data_in[111]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[112]" name="acq_data_in[112]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[113]" name="acq_data_in[113]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[114]" name="acq_data_in[114]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[115]" name="acq_data_in[115]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[116]" name="acq_data_in[116]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[117]" name="acq_data_in[117]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[118]" name="acq_data_in[118]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[119]" name="acq_data_in[119]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[120]" name="acq_data_in[120]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[121]" name="acq_data_in[121]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[122]" name="acq_data_in[122]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[123]" name="acq_data_in[123]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[124]" name="acq_data_in[124]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[125]" name="acq_data_in[125]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[126]" name="acq_data_in[126]" tap_mode="classic" type="unknown"/>
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[127]" name="acq_data_in[127]" tap_mode="classic" type="unknown"/>
</data_input_vec>
<storage_qualifier_input_vec/>
</signal_vec>
<presentation>
<data_view>
<bus alias="symbolsPerTransfer" is_signal_inverted="no" link="all" name="acq_data_in[0..7]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<net is_signal_inverted="no" name="acq_data_in[4]"/>
<net is_signal_inverted="no" name="acq_data_in[5]"/>
<net is_signal_inverted="no" name="acq_data_in[6]"/>
<net is_signal_inverted="no" name="acq_data_in[7]"/>
</bus>
<bus alias="outstandingTransactions" is_signal_inverted="no" link="all" name="acq_data_in[8..15]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[8]"/>
<net is_signal_inverted="no" name="acq_data_in[9]"/>
<net is_signal_inverted="no" name="acq_data_in[10]"/>
<net is_signal_inverted="no" name="acq_data_in[11]"/>
<net is_signal_inverted="no" name="acq_data_in[12]"/>
<net is_signal_inverted="no" name="acq_data_in[13]"/>
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
<net is_signal_inverted="no" name="acq_data_in[26]"/>
<net is_signal_inverted="no" name="acq_data_in[27]"/>
<net is_signal_inverted="no" name="acq_data_in[28]"/>
<net is_signal_inverted="no" name="acq_data_in[29]"/>
<net is_signal_inverted="no" name="acq_data_in[30]"/>
<net is_signal_inverted="no" name="acq_data_in[31]"/>
<net is_signal_inverted="no" name="acq_data_in[32]"/>
<net is_signal_inverted="no" name="acq_data_in[33]"/>
<net is_signal_inverted="no" name="acq_data_in[34]"/>
<net is_signal_inverted="no" name="acq_data_in[35]"/>
<net is_signal_inverted="no" name="acq_data_in[36]"/>
<net is_signal_inverted="no" name="acq_data_in[37]"/>
<net is_signal_inverted="no" name="acq_data_in[38]"/>
<net is_signal_inverted="no" name="acq_data_in[39]"/>
<net is_signal_inverted="no" name="acq_data_in[40]"/>
<net is_signal_inverted="no" name="acq_data_in[41]"/>
<net is_signal_inverted="no" name="acq_data_in[42]"/>
<net is_signal_inverted="no" name="acq_data_in[43]"/>
<net is_signal_inverted="no" name="acq_data_in[44]"/>
<net is_signal_inverted="no" name="acq_data_in[45]"/>
<net is_signal_inverted="no" name="acq_data_in[46]"/>
<net is_signal_inverted="no" name="acq_data_in[47]"/>
<net is_signal_inverted="no" name="acq_data_in[48]"/>
<net is_signal_inverted="no" name="acq_data_in[49]"/>
<net is_signal_inverted="no" name="acq_data_in[50]"/>
<net is_signal_inverted="no" name="acq_data_in[51]"/>
<net is_signal_inverted="no" name="acq_data_in[52]"/>
<net is_signal_inverted="no" name="acq_data_in[53]"/>
<net is_signal_inverted="no" name="acq_data_in[54]"/>
<net is_signal_inverted="no" name="acq_data_in[55]"/>
<net is_signal_inverted="no" name="acq_data_in[56]"/>
<net is_signal_inverted="no" name="acq_data_in[57]"/>
<net is_signal_inverted="no" name="acq_data_in[58]"/>
<net is_signal_inverted="no" name="acq_data_in[59]"/>
<net is_signal_inverted="no" name="acq_data_in[60]"/>
<net is_signal_inverted="no" name="acq_data_in[61]"/>
<net is_signal_inverted="no" name="acq_data_in[62]"/>
<net is_signal_inverted="no" name="acq_data_in[63]"/>
<net is_signal_inverted="no" name="acq_data_in[64]"/>
<net is_signal_inverted="no" name="acq_data_in[65]"/>
<net is_signal_inverted="no" name="acq_data_in[66]"/>
<net is_signal_inverted="no" name="acq_data_in[67]"/>
<net is_signal_inverted="no" name="acq_data_in[68]"/>
<net is_signal_inverted="no" name="acq_data_in[69]"/>
<net is_signal_inverted="no" name="acq_data_in[70]"/>
<net is_signal_inverted="no" name="acq_data_in[71]"/>
<net is_signal_inverted="no" name="acq_data_in[72]"/>
<net is_signal_inverted="no" name="acq_data_in[73]"/>
<net is_signal_inverted="no" name="acq_data_in[74]"/>
<net is_signal_inverted="no" name="acq_data_in[75]"/>
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<net is_signal_inverted="no" name="acq_data_in[77]"/>
<net is_signal_inverted="no" name="acq_data_in[78]"/>
<net is_signal_inverted="no" name="acq_data_in[79]"/>
<net is_signal_inverted="no" name="acq_data_in[80]"/>
<net is_signal_inverted="no" name="acq_data_in[81]"/>
<net is_signal_inverted="no" name="acq_data_in[82]"/>
<net is_signal_inverted="no" name="acq_data_in[83]"/>
<net is_signal_inverted="no" name="acq_data_in[84]"/>
<net is_signal_inverted="no" name="acq_data_in[85]"/>
<net is_signal_inverted="no" name="acq_data_in[86]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[87..90]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[87]"/>
<net is_signal_inverted="no" name="acq_data_in[88]"/>
<net is_signal_inverted="no" name="acq_data_in[89]"/>
<net is_signal_inverted="no" name="acq_data_in[90]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[91..94]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[91]"/>
<net is_signal_inverted="no" name="acq_data_in[92]"/>
<net is_signal_inverted="no" name="acq_data_in[93]"/>
<net is_signal_inverted="no" name="acq_data_in[94]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..101]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
<net is_signal_inverted="no" name="acq_data_in[101]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
</data_view>
<setup_view>
<bus alias="symbolsPerTransfer" is_signal_inverted="no" link="all" name="acq_data_in[0..7]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[0]"/>
<net is_signal_inverted="no" name="acq_data_in[1]"/>
<net is_signal_inverted="no" name="acq_data_in[2]"/>
<net is_signal_inverted="no" name="acq_data_in[3]"/>
<net is_signal_inverted="no" name="acq_data_in[4]"/>
<net is_signal_inverted="no" name="acq_data_in[5]"/>
<net is_signal_inverted="no" name="acq_data_in[6]"/>
<net is_signal_inverted="no" name="acq_data_in[7]"/>
</bus>
<bus alias="outstandingTransactions" is_signal_inverted="no" link="all" name="acq_data_in[8..15]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[8]"/>
<net is_signal_inverted="no" name="acq_data_in[9]"/>
<net is_signal_inverted="no" name="acq_data_in[10]"/>
<net is_signal_inverted="no" name="acq_data_in[11]"/>
<net is_signal_inverted="no" name="acq_data_in[12]"/>
<net is_signal_inverted="no" name="acq_data_in[13]"/>
<net is_signal_inverted="no" name="acq_data_in[14]"/>
<net is_signal_inverted="no" name="acq_data_in[15]"/>
</bus>
<bus alias="axiTxState" is_signal_inverted="no" link="all" mnemonics="next_axiTxState_table" name="acq_data_in[16..17]" order="lsb_to_msb" state="collapse" type="state machine">
<net is_signal_inverted="no" name="acq_data_in[16]"/>
<net is_signal_inverted="no" name="acq_data_in[17]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[18]"/>
<net is_signal_inverted="no" name="acq_data_in[19]"/>
<net is_signal_inverted="no" name="acq_data_in[20]"/>
<net is_signal_inverted="no" name="acq_data_in[21]"/>
<net is_signal_inverted="no" name="acq_data_in[22]"/>
<bus alias="axiMaster_out.tData" is_signal_inverted="no" link="all" name="acq_data_in[23..86]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[23]"/>
<net is_signal_inverted="no" name="acq_data_in[24]"/>
<net is_signal_inverted="no" name="acq_data_in[25]"/>
<net is_signal_inverted="no" name="acq_data_in[26]"/>
<net is_signal_inverted="no" name="acq_data_in[27]"/>
<net is_signal_inverted="no" name="acq_data_in[28]"/>
<net is_signal_inverted="no" name="acq_data_in[29]"/>
<net is_signal_inverted="no" name="acq_data_in[30]"/>
<net is_signal_inverted="no" name="acq_data_in[31]"/>
<net is_signal_inverted="no" name="acq_data_in[32]"/>
<net is_signal_inverted="no" name="acq_data_in[33]"/>
<net is_signal_inverted="no" name="acq_data_in[34]"/>
<net is_signal_inverted="no" name="acq_data_in[35]"/>
<net is_signal_inverted="no" name="acq_data_in[36]"/>
<net is_signal_inverted="no" name="acq_data_in[37]"/>
<net is_signal_inverted="no" name="acq_data_in[38]"/>
<net is_signal_inverted="no" name="acq_data_in[39]"/>
<net is_signal_inverted="no" name="acq_data_in[40]"/>
<net is_signal_inverted="no" name="acq_data_in[41]"/>
<net is_signal_inverted="no" name="acq_data_in[42]"/>
<net is_signal_inverted="no" name="acq_data_in[43]"/>
<net is_signal_inverted="no" name="acq_data_in[44]"/>
<net is_signal_inverted="no" name="acq_data_in[45]"/>
<net is_signal_inverted="no" name="acq_data_in[46]"/>
<net is_signal_inverted="no" name="acq_data_in[47]"/>
<net is_signal_inverted="no" name="acq_data_in[48]"/>
<net is_signal_inverted="no" name="acq_data_in[49]"/>
<net is_signal_inverted="no" name="acq_data_in[50]"/>
<net is_signal_inverted="no" name="acq_data_in[51]"/>
<net is_signal_inverted="no" name="acq_data_in[52]"/>
<net is_signal_inverted="no" name="acq_data_in[53]"/>
<net is_signal_inverted="no" name="acq_data_in[54]"/>
<net is_signal_inverted="no" name="acq_data_in[55]"/>
<net is_signal_inverted="no" name="acq_data_in[56]"/>
<net is_signal_inverted="no" name="acq_data_in[57]"/>
<net is_signal_inverted="no" name="acq_data_in[58]"/>
<net is_signal_inverted="no" name="acq_data_in[59]"/>
<net is_signal_inverted="no" name="acq_data_in[60]"/>
<net is_signal_inverted="no" name="acq_data_in[61]"/>
<net is_signal_inverted="no" name="acq_data_in[62]"/>
<net is_signal_inverted="no" name="acq_data_in[63]"/>
<net is_signal_inverted="no" name="acq_data_in[64]"/>
<net is_signal_inverted="no" name="acq_data_in[65]"/>
<net is_signal_inverted="no" name="acq_data_in[66]"/>
<net is_signal_inverted="no" name="acq_data_in[67]"/>
<net is_signal_inverted="no" name="acq_data_in[68]"/>
<net is_signal_inverted="no" name="acq_data_in[69]"/>
<net is_signal_inverted="no" name="acq_data_in[70]"/>
<net is_signal_inverted="no" name="acq_data_in[71]"/>
<net is_signal_inverted="no" name="acq_data_in[72]"/>
<net is_signal_inverted="no" name="acq_data_in[73]"/>
<net is_signal_inverted="no" name="acq_data_in[74]"/>
<net is_signal_inverted="no" name="acq_data_in[75]"/>
<net is_signal_inverted="no" name="acq_data_in[76]"/>
<net is_signal_inverted="no" name="acq_data_in[77]"/>
<net is_signal_inverted="no" name="acq_data_in[78]"/>
<net is_signal_inverted="no" name="acq_data_in[79]"/>
<net is_signal_inverted="no" name="acq_data_in[80]"/>
<net is_signal_inverted="no" name="acq_data_in[81]"/>
<net is_signal_inverted="no" name="acq_data_in[82]"/>
<net is_signal_inverted="no" name="acq_data_in[83]"/>
<net is_signal_inverted="no" name="acq_data_in[84]"/>
<net is_signal_inverted="no" name="acq_data_in[85]"/>
<net is_signal_inverted="no" name="acq_data_in[86]"/>
</bus>
<bus alias="axiMaster_out.tStrb" is_signal_inverted="no" link="all" name="acq_data_in[87..90]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[87]"/>
<net is_signal_inverted="no" name="acq_data_in[88]"/>
<net is_signal_inverted="no" name="acq_data_in[89]"/>
<net is_signal_inverted="no" name="acq_data_in[90]"/>
</bus>
<bus alias="axiMaster_out.tKeep" is_signal_inverted="no" link="all" name="acq_data_in[91..94]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[91]"/>
<net is_signal_inverted="no" name="acq_data_in[92]"/>
<net is_signal_inverted="no" name="acq_data_in[93]"/>
<net is_signal_inverted="no" name="acq_data_in[94]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[95]"/>
<net is_signal_inverted="no" name="acq_data_in[96]"/>
<net is_signal_inverted="no" name="acq_data_in[97]"/>
<bus is_signal_inverted="no" link="all" name="acq_data_in[98..101]" order="lsb_to_msb" radix="hex" state="collapse" type="unknown">
<net is_signal_inverted="no" name="acq_data_in[98]"/>
<net is_signal_inverted="no" name="acq_data_in[99]"/>
<net is_signal_inverted="no" name="acq_data_in[100]"/>
<net is_signal_inverted="no" name="acq_data_in[101]"/>
</bus>
<net is_signal_inverted="no" name="acq_data_in[102]"/>
<net is_signal_inverted="no" name="acq_data_in[103]"/>
<net is_signal_inverted="no" name="acq_data_in[104]"/>
<net is_signal_inverted="no" name="acq_data_in[105]"/>
<net is_signal_inverted="no" name="acq_data_in[106]"/>
<net is_signal_inverted="no" name="acq_data_in[107]"/>
<net is_signal_inverted="no" name="acq_data_in[108]"/>
<net is_signal_inverted="no" name="acq_data_in[109]"/>
<net is_signal_inverted="no" name="acq_data_in[110]"/>
<net is_signal_inverted="no" name="acq_data_in[111]"/>
<net is_signal_inverted="no" name="acq_data_in[112]"/>
<net is_signal_inverted="no" name="acq_data_in[113]"/>
<net is_signal_inverted="no" name="acq_data_in[114]"/>
<net is_signal_inverted="no" name="acq_data_in[115]"/>
<net is_signal_inverted="no" name="acq_data_in[116]"/>
<net is_signal_inverted="no" name="acq_data_in[117]"/>
<net is_signal_inverted="no" name="acq_data_in[118]"/>
<net is_signal_inverted="no" name="acq_data_in[119]"/>
<net is_signal_inverted="no" name="acq_data_in[120]"/>
<net is_signal_inverted="no" name="acq_data_in[121]"/>
<net is_signal_inverted="no" name="acq_data_in[122]"/>
<net is_signal_inverted="no" name="acq_data_in[123]"/>
<net is_signal_inverted="no" name="acq_data_in[124]"/>
<net is_signal_inverted="no" name="acq_data_in[125]"/>
<net is_signal_inverted="no" name="acq_data_in[126]"/>
<net is_signal_inverted="no" name="acq_data_in[127]"/>
<net is_signal_inverted="no" name="acq_trigger_in[0]"/>
</setup_view>
</presentation>
<trigger CRC="A1D452D4" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="either edge" trigger_out="active high" trigger_type="circular">
<power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/>
<events use_custom_flow_control="no">
<level enabled="yes" name="condition1" type="basic">
<power_up enabled="yes">
</power_up><op_node/>
</level>
</events>
<storage_qualifier>
<transitional>
<pwr_up_transitional/>
</transitional>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level type="basic">
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
</storage_qualifier>
<storage_qualifier_events>
<storage_qualifier_level>
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level>
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<storage_qualifier_level>
<power_up>
</power_up>
<op_node/>
</storage_qualifier_level>
<transitional><pwr_up_transitional/>
</transitional>
</storage_qualifier_events>
<log>
<data global_temp="1" name="log: 2013/09/28 20:22:15 #0" power_up_mode="false" sample_depth="0" trigger_position="-1"/>
<extradata/>
</log>
</trigger>
</signal_set>
<position_info>
<single attribute="active tab" value="1"/>
<single attribute="active tab" value="0"/>
</position_info>
</instance>
<mnemonics>
<table name="next_axiTxState_table" width="2">
<symbol name="idle" value="00"/>
<symbol name="payload" value="01"/>
<symbol name="endOfTx" value="10"/>
</table>
</mnemonics>
<static_plugin_mnemonics/>
<global_info>
<multi attribute="column width" size="23" value="34,223,140,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/>
<single attribute="active instance" value="0"/>
<multi attribute="frame size" size="2" value="1366,715"/>
<single attribute="config widget visible" value="1"/>
<single attribute="data log widget visible" value="1"/>
<single attribute="hierarchy widget height" value="2"/>
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="jtag widget visible" value="1"/>
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<multi attribute="frame size" size="2" value="1600,1178"/>
<multi attribute="jtag widget size" size="2" value="398,145"/>
<single attribute="instance widget visible" value="1"/>
<single attribute="config widget visible" value="1"/>
<single attribute="hierarchy widget visible" value="1"/>
<single attribute="data log widget visible" value="1"/>
</global_info>
<mnemonics/>
</session>

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