URL
https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk
Subversion Repositories axi4_tlm_bfm
Compare Revisions
- This comparison shows the changes necessary to convert path
/axi4_tlm_bfm
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
78,17 → 78,16
begin |
/* Transaction counter. */ |
process(n_areset,symbolsPerTransfer,aclk) is begin |
/* Using synchronous reset will meet timing. However, because outstandingTransactions is a huge |
register set, using asynchronous reset will violate timing. |
FIXME Try and close timing even with asynchronous reset applied on outstandingTransactions. |
Using asynchronous reset will help to lower power. |
*/ |
if not n_areset then outstandingTransactions<=symbolsPerTransfer; |
elsif falling_edge(aclk) then |
if outstandingTransactions<1 then |
outstandingTransactions<=symbolsPerTransfer; |
report "No more pending transactions." severity note; |
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1; |
--if not n_areset then outstandingTransactions<=symbolsPerTransfer; |
if falling_edge(aclk) then |
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */ |
if not n_areset then outstandingTransactions<=symbolsPerTransfer; |
else |
if outstandingTransactions<1 then |
outstandingTransactions<=symbolsPerTransfer; |
report "No more pending transactions." severity note; |
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1; |
end if; |
end if; |
end if; |
end process; |
125,19 → 124,22
axiMaster_out.tValid<=true; |
end if; |
|
case next_axiTxState is |
when payload=> |
axiMaster_out.tData<=writeRequest.message; |
axiMaster_out.tValid<=true; |
|
if axiMaster_in.tReady then |
i_writeResponse.trigger<=true; |
end if; |
|
/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */ |
if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if; |
when others=> null; |
end case; |
if not n_areset then axiMaster_out.tData<=(others=>'Z'); |
else |
case next_axiTxState is |
when payload=> |
axiMaster_out.tData<=writeRequest.message; |
axiMaster_out.tValid<=true; |
|
if axiMaster_in.tReady then |
i_writeResponse.trigger<=true; |
end if; |
|
/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */ |
if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if; |
when others=> null; |
end case; |
end if; |
end process axi_bfmTx_op; |
|
/* state registers and pipelines for AXI4-Stream Tx BFM. */ |
/trunk/rtl/quartus-synthesis/pll.vhd
0,0 → 1,365
-- megafunction wizard: %ALTPLL% |
-- GENERATION: STANDARD |
-- VERSION: WM1.0 |
-- MODULE: altpll |
|
-- ============================================================ |
-- File Name: pll.vhd |
-- Megafunction Name(s): |
-- altpll |
-- |
-- Simulation Library Files(s): |
-- altera_mf |
-- ============================================================ |
-- ************************************************************ |
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
-- |
-- 12.1 Build 177 11/07/2012 SJ Full Version |
-- ************************************************************ |
|
|
--Copyright (C) 1991-2012 Altera Corporation |
--Your use of Altera Corporation's design tools, logic functions |
--and other software and tools, and its AMPP partner logic |
--functions, and any output files from any of the foregoing |
--(including device programming or simulation files), and any |
--associated documentation or information are expressly subject |
--to the terms and conditions of the Altera Program License |
--Subscription Agreement, Altera MegaCore Function License |
--Agreement, or other applicable license agreement, including, |
--without limitation, that your use is for the sole purpose of |
--programming logic devices manufactured by Altera and sold by |
--Altera or its authorized distributors. Please refer to the |
--applicable agreement for further details. |
|
|
LIBRARY ieee; |
USE ieee.std_logic_1164.all; |
|
LIBRARY altera_mf; |
USE altera_mf.all; |
|
ENTITY pll IS |
PORT |
( |
areset : IN STD_LOGIC := '0'; |
inclk0 : IN STD_LOGIC := '0'; |
c0 : OUT STD_LOGIC ; |
locked : OUT STD_LOGIC |
); |
END pll; |
|
|
ARCHITECTURE SYN OF pll IS |
|
SIGNAL sub_wire0 : STD_LOGIC ; |
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (4 DOWNTO 0); |
SIGNAL sub_wire2 : STD_LOGIC ; |
SIGNAL sub_wire3 : STD_LOGIC ; |
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); |
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); |
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); |
|
|
|
COMPONENT altpll |
GENERIC ( |
bandwidth_type : STRING; |
clk0_divide_by : NATURAL; |
clk0_duty_cycle : NATURAL; |
clk0_multiply_by : NATURAL; |
clk0_phase_shift : STRING; |
compensate_clock : STRING; |
inclk0_input_frequency : NATURAL; |
intended_device_family : STRING; |
lpm_hint : STRING; |
lpm_type : STRING; |
operation_mode : STRING; |
pll_type : STRING; |
port_activeclock : STRING; |
port_areset : STRING; |
port_clkbad0 : STRING; |
port_clkbad1 : STRING; |
port_clkloss : STRING; |
port_clkswitch : STRING; |
port_configupdate : STRING; |
port_fbin : STRING; |
port_inclk0 : STRING; |
port_inclk1 : STRING; |
port_locked : STRING; |
port_pfdena : STRING; |
port_phasecounterselect : STRING; |
port_phasedone : STRING; |
port_phasestep : STRING; |
port_phaseupdown : STRING; |
port_pllena : STRING; |
port_scanaclr : STRING; |
port_scanclk : STRING; |
port_scanclkena : STRING; |
port_scandata : STRING; |
port_scandataout : STRING; |
port_scandone : STRING; |
port_scanread : STRING; |
port_scanwrite : STRING; |
port_clk0 : STRING; |
port_clk1 : STRING; |
port_clk2 : STRING; |
port_clk3 : STRING; |
port_clk4 : STRING; |
port_clk5 : STRING; |
port_clkena0 : STRING; |
port_clkena1 : STRING; |
port_clkena2 : STRING; |
port_clkena3 : STRING; |
port_clkena4 : STRING; |
port_clkena5 : STRING; |
port_extclk0 : STRING; |
port_extclk1 : STRING; |
port_extclk2 : STRING; |
port_extclk3 : STRING; |
self_reset_on_loss_lock : STRING; |
width_clock : NATURAL |
); |
PORT ( |
areset : IN STD_LOGIC ; |
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0); |
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); |
locked : OUT STD_LOGIC |
); |
END COMPONENT; |
|
BEGIN |
sub_wire5_bv(0 DOWNTO 0) <= "0"; |
sub_wire5 <= To_stdlogicvector(sub_wire5_bv); |
locked <= sub_wire0; |
sub_wire2 <= sub_wire1(0); |
c0 <= sub_wire2; |
sub_wire3 <= inclk0; |
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; |
|
altpll_component : altpll |
GENERIC MAP ( |
bandwidth_type => "AUTO", |
clk0_divide_by => 1, |
clk0_duty_cycle => 50, |
clk0_multiply_by => 2, |
clk0_phase_shift => "0", |
compensate_clock => "CLK0", |
inclk0_input_frequency => 20000, |
intended_device_family => "Cyclone III", |
lpm_hint => "CBX_MODULE_PREFIX=pll", |
lpm_type => "altpll", |
operation_mode => "NORMAL", |
pll_type => "AUTO", |
port_activeclock => "PORT_UNUSED", |
port_areset => "PORT_USED", |
port_clkbad0 => "PORT_UNUSED", |
port_clkbad1 => "PORT_UNUSED", |
port_clkloss => "PORT_UNUSED", |
port_clkswitch => "PORT_UNUSED", |
port_configupdate => "PORT_UNUSED", |
port_fbin => "PORT_UNUSED", |
port_inclk0 => "PORT_USED", |
port_inclk1 => "PORT_UNUSED", |
port_locked => "PORT_USED", |
port_pfdena => "PORT_UNUSED", |
port_phasecounterselect => "PORT_UNUSED", |
port_phasedone => "PORT_UNUSED", |
port_phasestep => "PORT_UNUSED", |
port_phaseupdown => "PORT_UNUSED", |
port_pllena => "PORT_UNUSED", |
port_scanaclr => "PORT_UNUSED", |
port_scanclk => "PORT_UNUSED", |
port_scanclkena => "PORT_UNUSED", |
port_scandata => "PORT_UNUSED", |
port_scandataout => "PORT_UNUSED", |
port_scandone => "PORT_UNUSED", |
port_scanread => "PORT_UNUSED", |
port_scanwrite => "PORT_UNUSED", |
port_clk0 => "PORT_USED", |
port_clk1 => "PORT_UNUSED", |
port_clk2 => "PORT_UNUSED", |
port_clk3 => "PORT_UNUSED", |
port_clk4 => "PORT_UNUSED", |
port_clk5 => "PORT_UNUSED", |
port_clkena0 => "PORT_UNUSED", |
port_clkena1 => "PORT_UNUSED", |
port_clkena2 => "PORT_UNUSED", |
port_clkena3 => "PORT_UNUSED", |
port_clkena4 => "PORT_UNUSED", |
port_clkena5 => "PORT_UNUSED", |
port_extclk0 => "PORT_UNUSED", |
port_extclk1 => "PORT_UNUSED", |
port_extclk2 => "PORT_UNUSED", |
port_extclk3 => "PORT_UNUSED", |
self_reset_on_loss_lock => "OFF", |
width_clock => 5 |
) |
PORT MAP ( |
areset => areset, |
inclk => sub_wire4, |
locked => sub_wire0, |
clk => sub_wire1 |
); |
|
|
|
END SYN; |
|
-- ============================================================ |
-- CNX file retrieval info |
-- ============================================================ |
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" |
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" |
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" |
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" |
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" |
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" |
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" |
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" |
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" |
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" |
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" |
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" |
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" |
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" |
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" |
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" |
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" |
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" |
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" |
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" |
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" |
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" |
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" |
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" |
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" |
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" |
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" |
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" |
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" |
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" |
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" |
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" |
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" |
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" |
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" |
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" |
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" |
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" |
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" |
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" |
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2" |
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" |
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" |
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" |
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" |
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" |
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" |
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" |
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" |
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" |
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" |
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" |
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" |
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" |
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" |
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" |
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" |
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" |
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" |
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" |
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" |
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" |
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" |
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" |
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" |
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" |
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" |
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" |
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" |
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" |
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" |
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" |
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" |
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" |
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" |
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" |
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" |
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" |
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" |
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" |
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" |
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2" |
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" |
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" |
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" |
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" |
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" |
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" |
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" |
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" |
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" |
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" |
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" |
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" |
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" |
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" |
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" |
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" |
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" |
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" |
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" |
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 |
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 |
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 |
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 |
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 |
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE |
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE |
-- Retrieval info: LIB_FILE: altera_mf |
-- Retrieval info: CBX_MODULE_PREFIX: ON |
/trunk/rtl/quartus-synthesis/user.vhdl
76,9 → 76,11
|
/* Tester signals. */ |
/* synthesis translate_off */ |
signal clk,nReset:std_ulogic:='0'; |
signal clk,reset:std_ulogic:='0'; |
/* synthesis translate_on */ |
|
signal cnt:unsigned(3 downto 0); |
signal reset:std_ulogic:='0'; |
signal testerClk:std_ulogic; |
--signal trigger:boolean; |
signal dbg_axiTxFSM:axiBfmStatesTx; |
85,10 → 87,6
signal anlysr_dataIn:std_logic_vector(127 downto 0); |
signal anlysr_trigger:std_ulogic; |
|
/* Signal preservations for SignalTap II probing. */ |
--attribute keep:boolean; |
--attribute keep of trigger:signal is true; |
|
signal axiMaster_in:t_axi4StreamTransactor_s2m; |
signal irq_write:std_ulogic; -- clock gating. |
|
96,7 → 94,7
/* Bus functional models. */ |
axiMaster: entity work.axiBfmMaster(rtl) |
port map( |
aclk=>irq_write, n_areset=>nReset, |
aclk=>irq_write, n_areset=>not reset, |
|
readRequest=>readRequest, writeRequest=>writeRequest, |
readResponse=>readResponse, writeResponse=>writeResponse, |
109,12 → 107,12
); |
|
/* Interrupt-request generator. */ |
irq_write<=clk when nReset else '0'; |
irq_write<=clk when not reset else '0'; |
|
/* Simulation Tester. */ |
/* PLL to generate tester's clock. */ |
f100MHz: entity altera.pll(syn) port map( |
areset=>not nReset, |
areset=>'0', --not reset, --not nReset, |
inclk0=>clk, |
c0=>testerClk, |
locked=>open |
132,23 → 130,20
|
|
/* Hardware tester. */ |
/* |
por: process(reset,clk) is |
variable cnt:unsigned(7 downto 0):=x"ff"; |
por: process(nReset,clk) is |
--variable cnt:unsigned(7 downto 0):=(others=>'1'); |
begin |
if not reset then cnt<=(others=>'1'); |
if not nReset then cnt<=(others=>'1'); |
elsif rising_edge(clk) then |
nReset<='1'; |
reset<='0'; |
|
if cnt>x"8" then nReset<='0'; end if; |
|
if cnt>0 then cnt:=cnt-1; end if; |
if cnt>0 then reset<='1'; cnt<=cnt-1; end if; |
end if; |
end process por; |
*/ |
|
/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */ |
anlysr_trigger<='1' when writeRequest.trigger else '0'; |
--anlysr_trigger<='1' when reset else '0'; |
|
/* Disable this for synthesis as this is not currently synthesisable. |
Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead. |
162,7 → 157,7
--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>; |
anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM); |
anlysr_dataIn(18)<='1' when clk else '0'; |
anlysr_dataIn(19)<='1' when nReset else '0'; |
anlysr_dataIn(19)<='1' when reset else '0'; |
anlysr_dataIn(20)<='1' when irq_write else '0'; |
anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0'; |
anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0'; |
173,6 → 168,7
anlysr_dataIn(96)<='1' when writeRequest.trigger else '0'; |
anlysr_dataIn(97)<='1' when writeResponse.trigger else '0'; |
--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM); |
anlysr_dataIn(101 downto 98)<=std_logic_vector(cnt); |
|
anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0'); |
|
251,7 → 247,7
/* Data transmitter. */ |
sequencer_ns: process(all) is begin |
txFSM<=i_txFSM; |
if not nReset then txFSM<=idle; |
if reset then txFSM<=idle; |
else |
case i_txFSM is |
when idle=> |
266,7 → 262,7
end process sequencer_ns; |
|
/* Data transmitter. */ |
sequencer_op: process(nReset,irq_write) is |
sequencer_op: process(reset,irq_write) is |
/* Local procedures to map BFM signals with the package procedure. */ |
procedure read(address:in t_addr) is begin |
read(readRequest,address); |
287,7 → 283,7
/* synthesis translate_on */ |
|
begin |
if not nReset then |
if reset then |
/* synthesis only. */ |
rand0:=(others=>'0'); |
|
320,12 → 316,12
|
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */ |
process(nReset,irq_write) is |
process(reset,irq_write) is |
/* synthesis translate_off */ |
variable rv0:RandomPType; |
/* synthesis translate_on */ |
begin |
if not nReset then |
if reset then |
/* synthesis translate_off */ |
rv0.InitSeed(rv0'instance_name); |
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8); |
/trunk/workspace/quartus/axi4-tlm.qsf
63,8 → 63,7
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/user.vhdl" |
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/stp.vhd" |
set_global_assignment -name VHDL_FILE "../../rtl/quartus-synthesis/pll.vhd" |
#set_location_assignment PIN_N2 -to nReset |
set_location_assignment PIN_F1 -to reset |
set_location_assignment PIN_N2 -to nReset |
set_location_assignment PIN_V9 -to clk |
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
/trunk/workspace/quartus/waves.stp
501,7 → 501,7
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[16]" name="acq_data_in[16]" tap_mode="classic" type="unknown"/> |
<wire alias="stp:i_bistFramer_stp_analyser|acq_data_in[17]" name="acq_data_in[17]" tap_mode="classic" type="unknown"/> |
<wire alias="clk" name="acq_data_in[18]" tap_mode="classic" type="unknown"/> |
<wire alias="nReset" name="acq_data_in[19]" tap_mode="classic" type="unknown"/> |
<wire alias="reset" name="acq_data_in[19]" tap_mode="classic" type="unknown"/> |
<wire alias="irq_write" name="acq_data_in[20]" tap_mode="classic" type="unknown"/> |
<wire alias="axiMaster_in.tReady" name="acq_data_in[21]" tap_mode="classic" type="unknown"/> |
<wire alias="axiMaster_out.tValid" name="acq_data_in[22]" tap_mode="classic" type="unknown"/> |
904,7 → 904,7
<net is_signal_inverted="no" name="acq_trigger_in[0]"/> |
</setup_view> |
</presentation> |
<trigger CRC="A1D452D4" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="either edge" trigger_out="active high" trigger_type="circular"> |
<trigger CRC="A1D452D4" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2013/09/25 02:14:11 #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="rising edge" trigger_out="active high" trigger_type="circular"> |
<power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/> |
<events use_custom_flow_control="no"> |
<level enabled="yes" name="condition1" type="basic"> |
977,7 → 977,7
<single attribute="hierarchy widget visible" value="1"/> |
<single attribute="instance widget visible" value="1"/> |
<single attribute="jtag widget visible" value="1"/> |
<multi attribute="column width" size="23" value="34,150,140,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/> |
<multi attribute="column width" size="23" value="34,154,108,74,68,70,88,88,98,98,88,88,110,101,101,101,101,101,101,101,101,107,78"/> |
<multi attribute="frame size" size="2" value="1600,1178"/> |
<multi attribute="jtag widget size" size="2" value="398,145"/> |
</global_info> |