URL
https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk
Subversion Repositories axi4_tlm_bfm
Compare Revisions
- This comparison shows the changes necessary to convert path
/axi4_tlm_bfm
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/trunk/rtl/axi4-stream-bfm-master.vhdl
41,7 → 41,7
--/* TODO remove once generic packages are supported. */ |
--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all; |
|
entity axiBfmMaster is --generic(constant maxTransactions:positive); |
entity axiBfmMaster is |
port(aclk,n_areset:in std_ulogic; |
/* BFM signalling. */ |
readRequest,writeRequest:in i_transactor.t_bfm:=(address=>(others=>'X'), message=>(others=>'X'), trigger=>false); |
70,12 → 70,17
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle; |
|
signal i_axiMaster_out:t_axi4StreamTransactor_m2s; |
signal i_trigger,trigger:boolean; |
|
/* BFM signalling. */ |
signal i_readRequest,i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); |
signal i_readResponse,i_writeResponse:i_transactor.t_bfm; |
-- signal i_readRequest,i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); |
-- signal i_readResponse,i_writeResponse:i_transactor.t_bfm; |
signal i_writeRequest:i_transactor.t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); |
signal i_writeResponse:i_transactor.t_bfm; |
|
begin |
i_trigger<=writeRequest.trigger xor i_writeRequest.trigger; |
|
/* next-state logic for AXI4-Stream Master Tx BFM. */ |
axi_bfmTx_ns: process(all) is begin |
axiTxState<=next_axiTxState; |
84,7 → 89,7
else |
case next_axiTxState is |
when idle=> |
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if; |
if i_trigger then axiTxState<=payload; end if; |
when payload=> |
if outstandingTransactions<1 then axiTxState<=endOfTx; end if; |
when endOfTx=> |
103,13 → 108,12
i_axiMaster_out.tData<=(others=>'Z'); |
i_writeResponse.trigger<=false; |
|
if writeRequest.trigger xor i_writeRequest.trigger then |
i_axiMaster_out.tData<=writeRequest.message; |
i_axiMaster_out.tValid<=true; |
end if; |
|
case next_axiTxState is |
when idle=> null; |
when idle=> |
if i_trigger then |
i_axiMaster_out.tData<=writeRequest.message; |
i_axiMaster_out.tValid<=true; |
end if; |
when payload=> |
i_axiMaster_out.tData<=writeRequest.message; |
i_axiMaster_out.tValid<=true; |
123,20 → 127,15
end case; |
end process axi_bfmTx_op; |
|
axiMaster_out<=i_axiMaster_out; |
|
/* state registers and pipelines for AXI4-Stream Tx BFM. */ |
process(n_areset,aclk) is begin |
process(aclk) is begin |
if falling_edge(aclk) then |
next_axiTxState<=axiTxState; |
i_writeRequest<=writeRequest; |
--axiMaster_out<=i_axiMaster_out; |
writeResponse<=i_writeResponse; |
axiMaster_out<=i_axiMaster_out; |
trigger<=i_trigger; |
end if; |
end process; |
|
process(aclk) is begin |
if rising_edge(aclk) then |
writeResponse<=i_writeResponse; |
end if; |
end process; |
end architecture rtl; |
/trunk/rtl/user.vhdl
57,6 → 57,10
end entity user; |
|
architecture rtl of user is |
signal reset:std_ulogic:='0'; |
signal porCnt:unsigned(3 downto 0); |
signal trigger:boolean; |
|
/* Global counters. */ |
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. |
signal symbolsPerTransfer:i_transactor.t_cnt; |
72,16 → 76,20
/* Tester signals. */ |
/* synthesis translate_off */ |
signal clk,nReset:std_ulogic:='0'; |
attribute period:time; attribute period of clk:signal is 10 ps; |
/* synthesis translate_on */ |
|
signal axiMaster_in:t_axi4StreamTransactor_s2m; |
signal irq_write:std_ulogic; -- clock gating. |
|
signal prbs:i_transactor.t_msg; |
|
begin |
/* Bus functional models. */ |
axiMaster: entity work.axiBfmMaster(rtl) |
axiMaster: entity tauhop.axiBfmMaster(rtl) |
--axiMaster: entity work.axiBfmMaster(simulation) |
port map( |
aclk=>irq_write, n_areset=>nReset, |
aclk=>irq_write, n_areset=>not reset, |
|
readRequest=>readRequest, writeRequest=>writeRequest, |
readResponse=>readResponse, writeResponse=>writeResponse, |
93,11 → 101,12
); |
|
/* Interrupt-request generator. */ |
irq_write<=clk when nReset else '0'; |
trigger<=txFSM/=i_txFSM or writeResponse.trigger; |
irq_write<=clk when not reset else '0'; |
|
/* Simulation Tester. */ |
/* synthesis translate_off */ |
clk<=not clk after 10 ps; |
clk<=not clk after clk'period/2; |
process is begin |
nReset<='1'; wait for 1 ps; |
nReset<='0'; wait for 500 ps; |
106,8 → 115,30
end process; |
/* synthesis translate_on */ |
|
|
/* Hardware tester. */ |
/* Power-on Reset circuitry. */ |
por: process(nReset,clk) is begin |
if not nReset then reset<='1'; porCnt<=(others=>'1'); |
elsif rising_edge(clk) then |
reset<='0'; |
|
if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if; |
end if; |
end process por; |
|
/* |
process is |
alias trigger is <<signal axiMaster.trigger:boolean>>; |
alias axiTxState is <<signal axiMaster.next_axiTxState:axiBfmStatesTx>>; |
begin |
-- Remove this assertion once request queue has been implemented. |
if trigger then |
assert axiTxState=idle or axiTxState=payload report "[Error]: Trigger occurs when FSM is not in IDLE or PAYLOAD state." severity error; |
end if; |
wait for clk'period/10; |
end process; |
*/ |
|
/* Stimuli sequencer. TODO move to tester/stimuli. |
This emulates the AXI4-Stream Slave. |
115,6 → 146,8
/* Simulation-only stimuli sequencer. */ |
/* synthesis translate_off */ |
process is begin |
report "Performing fast read..." severity note; |
|
/* Fast read. */ |
while not axiMaster_out.tLast loop |
/* Wait for tValid to assert. */ |
128,7 → 161,11
axiMaster_in.tReady<=false; |
end loop; |
|
report "Completed fast read..." severity note; |
|
|
wait until falling_edge(clk); |
report "Performing normal read..." severity note; |
|
/* Normal read. */ |
while not axiMaster_out.tLast loop |
142,11 → 179,40
|
wait until falling_edge(clk); |
axiMaster_in.tReady<=false; |
|
wait until falling_edge(clk); |
end loop; |
|
report "Completed normal read." severity note; |
|
|
wait until falling_edge(clk); |
report "Performing slow read..." severity note; |
|
/* Slow read. */ |
while not axiMaster_out.tLast loop |
/* Wait for tValid to assert. */ |
while not axiMaster_out.tValid loop |
wait until falling_edge(clk); |
end loop; |
|
wait until falling_edge(clk); |
wait until falling_edge(clk); |
axiMaster_in.tReady<=true; |
|
wait until falling_edge(clk); |
axiMaster_in.tReady<=false; |
|
wait until falling_edge(clk); |
end loop; |
|
report "Completed slow read." severity note; |
|
|
for i in 0 to 10 loop |
wait until falling_edge(clk); |
end loop; |
report "Performing one-shot read..." severity note; |
|
/* One-shot read. */ |
axiMaster_in.tReady<=true; |
154,6 → 220,8
wait until falling_edge(clk); |
axiMaster_in.tReady<=false; |
|
report "Completed one-shot read." severity note; |
|
wait; |
end process; |
/* synthesis translate_on */ |
162,9 → 230,27
|
|
/* Data transmitter. */ |
i_prbs: entity tauhop.prbs31(rtl) |
generic map( |
isParallelLoad=>true, |
tapVector=>( |
/* Example polynomial from Wikipedia: |
http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks |
*/ |
0|3|31=>true, 1|2|30 downto 4=>false |
) |
) |
port map( |
/* Comment-out for simulation. */ |
clk=>irq_write, reset=>reset, |
en=>trigger, |
seed=>32x"ace1", --9x"57", |
prbs=>prbs |
); |
|
sequencer_ns: process(all) is begin |
txFSM<=i_txFSM; |
if not nReset then txFSM<=idle; |
if reset then txFSM<=idle; |
else |
case i_txFSM is |
when idle=> |
178,7 → 264,7
end if; |
end process sequencer_ns; |
|
sequencer_op: process(nReset,irq_write) is |
sequencer_op: process(reset,irq_write) is |
/* Local procedures to map BFM signals with the package procedure. */ |
procedure read(address:in i_transactor.t_addr) is begin |
i_transactor.read(readRequest,address); |
191,7 → 277,7
variable isPktError:boolean; |
|
/* Tester variables. */ |
/* Synthesis-only randomisation. */ |
/* Synthesis-only randomisation. */ |
|
/* Simulation-only randomisation. */ |
/* synthesis translate_off */ |
199,18 → 285,20
/* synthesis translate_on */ |
|
begin |
if not nReset then |
/*simulation only. */ |
-- if reset then |
/* simulation only. */ |
/* synthesis translate_off */ |
rv0.InitSeed(rv0'instance_name); |
-- rv0.InitSeed(rv0'instance_name); |
/* synthesis translate_on */ |
elsif falling_edge(irq_write) then |
-- elsif falling_edge(irq_write) then |
if falling_edge(irq_write) then |
case txFSM is |
when transmitting=> |
if txFSM/=i_txFSM or writeResponse.trigger then |
if trigger then |
/* synthesis translate_off */ |
write(rv0.RandSigned(axiMaster_out.tData'length)); |
-- write(rv0.RandSigned(axiMaster_out.tData'length)); |
/* synthesis translate_on */ |
write(prbs); |
end if; |
when others=>null; |
end case; |
224,12 → 312,10
end process sequencer_regs; |
|
/* Transaction counter. */ |
process(nReset,symbolsPerTransfer,irq_write) is begin |
if not nReset then outstandingTransactions<=symbolsPerTransfer; |
elsif falling_edge(irq_write) then |
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */ |
if not nReset then outstandingTransactions<=symbolsPerTransfer; |
else |
process(reset,symbolsPerTransfer,irq_write) is begin |
if reset then outstandingTransactions<=symbolsPerTransfer; |
elsif rising_edge(irq_write) then |
if not axiMaster_out.tLast then |
if outstandingTransactions<1 then |
outstandingTransactions<=symbolsPerTransfer; |
report "No more pending transactions." severity note; |
236,26 → 322,29
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1; |
end if; |
end if; |
end if; |
end process; |
|
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */ |
if reset then outstandingTransactions<=symbolsPerTransfer; end if; |
end if; |
end process; |
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */ |
process(nReset,irq_write) is |
process(reset,irq_write) is |
/* synthesis translate_off */ |
variable rv0:RandomPType; |
/* synthesis translate_on */ |
begin |
if not nReset then |
if reset then |
/* synthesis translate_off */ |
rv0.InitSeed(rv0'instance_name); |
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8); |
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)); |
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note; |
/* synthesis translate_on */ |
elsif rising_edge(irq_write) then |
if axiMaster_out.tLast then |
/* synthesis translate_off */ |
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8); |
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)); |
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note; |
/* synthesis translate_on */ |
end if; |
end if; |
/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
38,13 → 38,13
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; |
--library tauhop; use tauhop.axiTransactor.all; |
|
--/* TODO remove once generic packages are supported. */ |
/* TODO remove once generic packages are supported. */ |
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all; |
|
entity axiBfmMaster is |
port(aclk,n_areset:in std_ulogic; |
/* BFM signalling. */ |
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false); |
readRequest,writeRequest:in t_bfm:=(address=>(others=>'X'), message=>(others=>'X'), trigger=>false); |
readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports. |
|
/* AXI Master interface */ |
69,13 → 69,18
/* Finite-state Machines. */ |
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle; |
|
signal i_axiMaster_out:t_axi4StreamTransactor_m2s; |
signal i_trigger,trigger:boolean; |
|
/* BFM signalling. */ |
signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false); |
signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false); |
-- signal i_readRequest,i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); |
-- signal i_readResponse,i_writeResponse:t_bfm; |
signal i_writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); |
signal i_writeResponse:t_bfm; |
|
signal i_readResponse,i_writeResponse:t_bfm; |
begin |
i_trigger<=writeRequest.trigger xor i_writeRequest.trigger; |
|
begin |
/* next-state logic for AXI4-Stream Master Tx BFM. */ |
axi_bfmTx_ns: process(all) is begin |
axiTxState<=next_axiTxState; |
84,7 → 89,7
else |
case next_axiTxState is |
when idle=> |
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if; |
if i_trigger then axiTxState<=payload; end if; |
when payload=> |
if outstandingTransactions<1 then axiTxState<=endOfTx; end if; |
when endOfTx=> |
98,45 → 103,38
axi_bfmTx_op: process(all) is begin |
i_writeResponse<=writeResponse; |
|
axiMaster_out.tValid<=false; |
axiMaster_out.tLast<=false; |
axiMaster_out.tData<=(others=>'Z'); |
i_axiMaster_out.tValid<=false; |
i_axiMaster_out.tLast<=false; |
i_axiMaster_out.tData<=(others=>'Z'); |
i_writeResponse.trigger<=false; |
|
if writeRequest.trigger xor i_writeRequest.trigger then |
axiMaster_out.tData<=writeRequest.message; |
axiMaster_out.tValid<=true; |
end if; |
|
if not n_areset then axiMaster_out.tData<=(others=>'Z'); |
else |
case next_axiTxState is |
when payload=> |
axiMaster_out.tData<=writeRequest.message; |
axiMaster_out.tValid<=true; |
|
if axiMaster_in.tReady then |
i_writeResponse.trigger<=true; |
end if; |
|
/* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */ |
if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if; |
when others=> null; |
end case; |
end if; |
case next_axiTxState is |
when idle=> |
if i_trigger then |
i_axiMaster_out.tData<=writeRequest.message; |
i_axiMaster_out.tValid<=true; |
end if; |
when payload=> |
i_axiMaster_out.tData<=writeRequest.message; |
i_axiMaster_out.tValid<=true; |
|
if axiMaster_in.tReady then |
i_writeResponse.trigger<=true; |
end if; |
|
if outstandingTransactions<1 then i_axiMaster_out.tLast<=true; end if; |
when others=> null; |
end case; |
end process axi_bfmTx_op; |
|
/* state registers and pipelines for AXI4-Stream Tx BFM. */ |
process(n_areset,aclk) is begin |
process(aclk) is begin |
if falling_edge(aclk) then |
next_axiTxState<=axiTxState; |
i_writeRequest<=writeRequest; |
end if; |
end process; |
|
process(aclk) is begin |
if rising_edge(aclk) then |
writeResponse<=i_writeResponse; |
axiMaster_out<=i_axiMaster_out; |
trigger<=i_trigger; |
end if; |
end process; |
|
/trunk/rtl/quartus-synthesis/pkg-axi-tlm.vhdl
43,10 → 43,10
package axiTLM is |
-- generic( |
-- type t_qualifier; type t_id; type t_dest; type t_user; type t_resp; |
-- package transactor is new tauhop.tlm generic map(<>) |
-- package i_transactor is new tauhop.tlm generic map(<>) |
-- ); |
-- /* Makes transactor.t_addr and transactor.t_msg visible. */ |
-- use transactor.all; |
-- /* Makes i_transactor.t_addr, i_transactor.t_msg, and i_transactor.t_cnt visible. */ |
-- use i_transactor.all; |
|
/* TODO remove once generic packages are supported. */ |
use tauhop.tlm.all; |
/trunk/rtl/quartus-synthesis/stp.vhd
94,8 → 94,8
sld_enable_advanced_trigger => 0, |
sld_mem_address_bits => 12, |
sld_node_crc_bits => 32, |
sld_node_crc_hiword => 41428, |
sld_node_crc_loword => 21204, |
sld_node_crc_hiword => 7854, |
sld_node_crc_loword => 42699, |
sld_node_info => 1076736, |
sld_ram_block_type => "Auto", |
sld_sample_depth => 4096, |
130,13 → 130,13
-- Retrieval info: PRIVATE: TRIGGER_WIDTH_SPIN STRING "" |
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
-- Retrieval info: CONSTANT: SLD_ADVANCED_TRIGGER_ENTITY STRING "basic,1," |
-- Retrieval info: CONSTANT: SLD_DATA_BITS NUMERIC "80" |
-- Retrieval info: CONSTANT: SLD_DATA_BITS NUMERIC "128" |
-- Retrieval info: CONSTANT: SLD_DATA_BIT_CNTR_BITS NUMERIC "8" |
-- Retrieval info: CONSTANT: SLD_ENABLE_ADVANCED_TRIGGER NUMERIC "0" |
-- Retrieval info: CONSTANT: SLD_MEM_ADDRESS_BITS NUMERIC "12" |
-- Retrieval info: CONSTANT: SLD_NODE_CRC_BITS NUMERIC "32" |
-- Retrieval info: CONSTANT: SLD_NODE_CRC_HIWORD NUMERIC "41428" |
-- Retrieval info: CONSTANT: SLD_NODE_CRC_LOWORD NUMERIC "21204" |
-- Retrieval info: CONSTANT: SLD_NODE_CRC_HIWORD NUMERIC "7854" |
-- Retrieval info: CONSTANT: SLD_NODE_CRC_LOWORD NUMERIC "42699" |
-- Retrieval info: CONSTANT: SLD_NODE_INFO NUMERIC "1076736" |
-- Retrieval info: CONSTANT: SLD_RAM_BLOCK_TYPE STRING "Auto" |
-- Retrieval info: CONSTANT: SLD_SAMPLE_DEPTH NUMERIC "4096" |
147,11 → 147,11
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL NUMERIC "1" |
-- Retrieval info: CONSTANT: SLD_TRIGGER_LEVEL_PIPELINE NUMERIC "1" |
-- Retrieval info: USED_PORT: acq_clk 0 0 0 0 INPUT NODEFVAL "acq_clk" |
-- Retrieval info: USED_PORT: acq_data_in 0 0 80 0 INPUT NODEFVAL "acq_data_in[79..0]" |
-- Retrieval info: USED_PORT: acq_data_in 0 0 128 0 INPUT NODEFVAL "acq_data_in[127..0]" |
-- Retrieval info: USED_PORT: acq_trigger_in 0 0 1 0 INPUT NODEFVAL "acq_trigger_in[0..0]" |
-- Retrieval info: USED_PORT: trigger_in 0 0 0 0 INPUT NODEFVAL "trigger_in" |
-- Retrieval info: CONNECT: @acq_clk 0 0 0 0 acq_clk 0 0 0 0 |
-- Retrieval info: CONNECT: @acq_data_in 0 0 80 0 acq_data_in 0 0 80 0 |
-- Retrieval info: CONNECT: @acq_data_in 0 0 128 0 acq_data_in 0 0 128 0 |
-- Retrieval info: CONNECT: @acq_trigger_in 0 0 1 0 acq_trigger_in 0 0 1 0 |
-- Retrieval info: CONNECT: @trigger_in 0 0 0 0 trigger_in 0 0 0 0 |
-- Retrieval info: GEN_FILE: TYPE_NORMAL stp.vhd TRUE |
/trunk/rtl/quartus-synthesis/pkg-tlm.vhdl
49,7 → 49,7
|
/* TODO remove once generic packages are supported. */ |
subtype t_addr is unsigned(31 downto 0); |
subtype t_msg is signed(63 downto 0); |
subtype t_msg is signed(31 downto 0); |
subtype t_cnt is unsigned(127 downto 0); |
|
/* BFM control interface. */ |
/trunk/rtl/quartus-synthesis/pll.vhd
146,7 → 146,7
clk0_phase_shift => "0", |
compensate_clock => "CLK0", |
inclk0_input_frequency => 20000, |
intended_device_family => "Cyclone III", |
intended_device_family => "Cyclone IV E", |
lpm_hint => "CBX_MODULE_PREFIX=pll", |
lpm_type => "altpll", |
operation_mode => "NORMAL", |
224,7 → 224,7
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" |
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" |
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" |
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" |
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" |
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" |
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" |
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000" |
241,7 → 241,7
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" |
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" |
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" |
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" |
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" |
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" |
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" |
297,7 → 297,7
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" |
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" |
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" |
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" |
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" |
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" |
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" |
/trunk/rtl/quartus-synthesis/user.vhdl
49,17 → 49,21
|
entity user is port( |
/* Comment-out for simulation. */ |
clk,nReset:in std_ulogic; |
clk,reset:in std_ulogic; |
|
/* AXI Master interface */ |
-- axiMaster_in:in t_axi4StreamTransactor_s2m; |
axiMaster_out:buffer t_axi4StreamTransactor_m2s |
axiMaster_out:buffer t_axi4StreamTransactor_m2s; |
|
/* Debug ports. */ |
selTxn:in unsigned(3 downto 0):=x"0" |
); |
end entity user; |
|
architecture rtl of user is |
signal i_reset:std_ulogic:='0'; |
signal porCnt:unsigned(3 downto 0); |
|
/* Global counters. */ |
constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. |
signal symbolsPerTransfer:t_cnt; |
66,25 → 70,17
signal outstandingTransactions:t_cnt; |
|
/* BFM signalling. */ |
signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false); |
signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false); |
signal readResponse:t_bfm; |
signal writeResponse:t_bfm; |
signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false); |
signal readResponse,writeResponse:t_bfm; |
|
type txStates is (idle,transmitting); |
signal txFSM,i_txFSM:txStates; |
|
/* Tester signals. */ |
/* synthesis translate_off */ |
signal clk,reset:std_ulogic:='0'; |
attribute period:time; attribute period of clk:signal is 10 ps; |
/* synthesis translate_on */ |
|
signal cnt:unsigned(3 downto 0); |
signal reset:std_ulogic:='0'; |
signal testerClk:std_ulogic; |
--signal trigger:boolean; |
signal dbg_axiTxFSM:axiBfmStatesTx; |
signal anlysr_dataIn:std_logic_vector(127 downto 0); |
signal anlysr_dataIn:std_logic_vector(255 downto 0); |
signal anlysr_trigger:std_ulogic; |
|
signal axiMaster_in:t_axi4StreamTransactor_s2m; |
94,7 → 90,7
/* Bus functional models. */ |
axiMaster: entity tauhop.axiBfmMaster(rtl) |
port map( |
aclk=>irq_write, n_areset=>not reset, |
aclk=>irq_write, n_areset=>not i_reset, |
|
readRequest=>readRequest, writeRequest=>writeRequest, |
readResponse=>readResponse, writeResponse=>writeResponse, |
106,263 → 102,39
dbg_axiTxFSM=>dbg_axiTxFSM |
); |
|
/* Interrupt-request generator. */ |
irq_write<=clk when not reset else '0'; |
|
/* Simulation Tester. */ |
/* PLL to generate tester's clock. */ |
f100MHz: entity altera.pll(syn) port map( |
areset=>'0', --not nReset, |
inclk0=>clk, |
c0=>testerClk, |
locked=>open |
); |
|
/* synthesis translate_off */ |
clk<=not clk after 10 ps; |
process is begin |
nReset<='1'; wait for 1 ps; |
nReset<='0'; wait for 500 ps; |
nReset<='1'; |
wait; |
end process; |
/* synthesis translate_on */ |
|
|
/* Hardware tester. */ |
por: process(nReset,clk) is |
--variable cnt:unsigned(7 downto 0):=(others=>'1'); |
begin |
if not nReset then cnt<=(others=>'1'); |
/* Clocks and reset. */ |
/* Power-on Reset circuitry. */ |
por: process(reset,clk) is begin |
if reset then i_reset<='1'; porCnt<=(others=>'1'); |
elsif rising_edge(clk) then |
reset<='0'; |
i_reset<='0'; |
|
if cnt>0 then reset<='1'; cnt<=cnt-1; end if; |
if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if; |
end if; |
end process por; |
|
/* SignalTap II embedded logic analyser. Included as part of BiST architecture. */ |
--anlysr_trigger<='1' when writeRequest.trigger else '0'; |
anlysr_trigger<='1' when reset else '0'; |
|
/* Disable this for synthesis as this is not currently synthesisable. |
Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead. |
*/ |
/* synthesis translate_off */ |
--framerFSM<=to_unsigned(<<signal framers_txs(0).i_framer.framerFSM: framerFsmStates>>,framerFSM'length); |
/* synthesis translate_on */ |
|
anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0)); |
anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0)); |
--anlysr_dataIn(2 downto 0) <= <<signal axiMaster.axiTxState:axiBfmStatesTx>>; |
anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM); |
anlysr_dataIn(18)<='1' when clk else '0'; |
anlysr_dataIn(19)<='1' when reset else '0'; |
anlysr_dataIn(20)<='1' when irq_write else '0'; |
anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0'; |
anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0'; |
anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData); |
anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb); |
anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep); |
anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0'; |
anlysr_dataIn(96)<='1' when writeRequest.trigger else '0'; |
anlysr_dataIn(97)<='1' when writeResponse.trigger else '0'; |
--anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM); |
anlysr_dataIn(101 downto 98)<=std_logic_vector(cnt); |
|
anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0'); |
|
|
/* Simulate only if you have compiled Altera's simulation libraries. */ |
i_bist_logicAnalyser: entity altera.stp(syn) port map( |
acq_clk=>testerClk, |
acq_data_in=>anlysr_dataIn, |
acq_trigger_in=>"1", |
trigger_in=>anlysr_trigger |
); |
|
|
|
/* Stimuli sequencer. TODO move to tester/stimuli. |
This emulates the AXI4-Stream Slave. |
*/ |
/* Simulation-only stimuli sequencer. */ |
/* synthesis translate_off */ |
clk<=not clk after clk'period/2; |
process is begin |
/* Fast read. */ |
while not axiMaster_out.tLast loop |
/* Wait for tValid to assert. */ |
while not axiMaster_out.tValid loop |
wait until falling_edge(clk); |
end loop; |
|
axiMaster_in.tReady<=true; |
|
wait until falling_edge(clk); |
axiMaster_in.tReady<=false; |
end loop; |
|
wait until falling_edge(clk); |
|
/* Normal read. */ |
while not axiMaster_out.tLast loop |
/* Wait for tValid to assert. */ |
while not axiMaster_out.tValid loop |
wait until falling_edge(clk); |
end loop; |
|
wait until falling_edge(clk); |
axiMaster_in.tReady<=true; |
|
wait until falling_edge(clk); |
axiMaster_in.tReady<=false; |
end loop; |
|
for i in 0 to 10 loop |
wait until falling_edge(clk); |
end loop; |
|
/* One-shot read. */ |
axiMaster_in.tReady<=true; |
|
wait until falling_edge(clk); |
axiMaster_in.tReady<=false; |
|
reset<='0'; wait for 1 ps; |
reset<='1'; wait for 500 ps; |
reset<='0'; |
wait; |
end process; |
/* synthesis translate_on */ |
|
/* Synthesisable stimuli sequencer. */ |
process(clk) is begin |
if falling_edge(clk) then |
axiMaster_in.tReady<=false; |
--if axiMaster_out.tValid and not axiMaster_out.tLast then |
if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then |
axiMaster_in.tReady<=true; |
end if; |
end if; |
end process; |
/* Simulation Tester. */ |
|
|
/* Data transmitter. */ |
sequencer_ns: process(all) is begin |
txFSM<=i_txFSM; |
if reset then txFSM<=idle; |
else |
case i_txFSM is |
when idle=> |
if outstandingTransactions>0 then txFSM<=transmitting; end if; |
when transmitting=> |
if axiMaster_out.tLast then |
txFSM<=idle; |
end if; |
when others=> null; |
end case; |
end if; |
end process sequencer_ns; |
|
/* Data transmitter. */ |
sequencer_op: process(reset,irq_write) is |
/* Local procedures to map BFM signals with the package procedure. */ |
procedure read(address:in t_addr) is begin |
read(readRequest,address); |
end procedure read; |
|
procedure write(data:in t_msg) is begin |
write(request=>writeRequest, address=>(others=>'-'), data=>data); |
end procedure write; |
|
variable isPktError:boolean; |
|
/* Tester variables. */ |
/* Synthesis-only randomisation. */ |
variable rand0:signed(axiMaster_out.tData'high downto 0); |
/* Simulation-only randomisation. */ |
/* synthesis translate_off */ |
variable rv0:RandomPType; |
/* synthesis translate_on */ |
|
begin |
if reset then |
/* synthesis only. */ |
rand0:=(others=>'0'); |
|
/* simulation only. */ |
/* synthesis translate_off */ |
rv0.InitSeed(rv0'instance_name); |
/* synthesis translate_on */ |
|
--txFSM<=idle; |
elsif falling_edge(irq_write) then |
case txFSM is |
when transmitting=> |
if txFSM/=i_txFSM or writeResponse.trigger then |
/* synthesis translate_off */ |
write(rv0.RandSigned(axiMaster_out.tData'length)); |
/* synthesis translate_on */ |
write(rand0); |
rand0:=rand0+1; |
end if; |
when others=>null; |
end case; |
end if; |
end process sequencer_op; |
|
sequencer_regs: process(irq_write) is begin |
if falling_edge(irq_write) then |
i_txFSM<=txFSM; |
end if; |
end process sequencer_regs; |
|
/* Transaction counter. */ |
process(nReset,symbolsPerTransfer,irq_write) is begin |
if not nReset then outstandingTransactions<=symbolsPerTransfer; |
elsif falling_edge(irq_write) then |
/* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */ |
if not nReset then outstandingTransactions<=symbolsPerTransfer; |
else |
if outstandingTransactions<1 then |
outstandingTransactions<=symbolsPerTransfer; |
report "No more pending transactions." severity note; |
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1; |
end if; |
end if; |
end if; |
end process; |
|
/* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */ |
process(reset,irq_write) is |
/* synthesis translate_off */ |
variable rv0:RandomPType; |
/* synthesis translate_on */ |
begin |
if reset then |
/* synthesis translate_off */ |
rv0.InitSeed(rv0'instance_name); |
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8); |
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)); |
/* synthesis translate_on */ |
|
symbolsPerTransfer<=128x"8"; |
elsif rising_edge(irq_write) then |
if axiMaster_out.tLast then |
/* synthesis only. */ |
/* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */ |
--symbolsPerTransfer<=(others=>'0'); |
|
/* Testcase 2: number of symbols per transfer is randomised. */ |
--uniform(seed0,seed1,rand0); |
--symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length |
--report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length)); |
|
|
/* synthesis translate_off */ |
symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8); |
report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)); |
/* synthesis translate_on */ |
|
symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff"; |
end if; |
end if; |
end process; |
/* Hardware tester. */ |
bist: entity work.tester(rtl) port map( |
clk=>clk, reset=>i_reset, |
axiMaster_in=>axiMaster_in, |
axiMaster_out=>axiMaster_out, |
readRequest=>readRequest, writeRequest=>writeRequest, |
readResponse=>readResponse, writeResponse=>writeResponse, |
irq_write=>irq_write, |
symbolsPerTransfer=>symbolsPerTransfer, |
outstandingTransactions=>outstandingTransactions, |
selTxn=>selTxn |
); |
end architecture rtl; |
/trunk/rtl/packages/pkg-axi-tlm.vhdl
140,9 → 140,9
tStrb:t_qualifier; |
tKeep:t_qualifier; |
tLast:boolean; |
tId:t_id; |
tDest:t_dest; |
tUser:t_user; |
-- tId:t_id; |
-- tDest:t_dest; |
-- tUser:t_user; |
end record t_axi4StreamTransactor_m2s; |
|
type t_axi4StreamTransactor_s2m is record |
156,7 → 156,8
-- cActive: |
-- end record tAxiTransactor_lp; |
|
type axiBfmStatesTx is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx); |
-- type axiBfmStatesTx is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx); |
type axiBfmStatesTx is (idle,payload,endOfTx); |
type axiBfmStatesRx is (idle,checkAddr,startOfPacket,payload); |
end package axiTLM; |
|
181,7 → 182,8
library tauhop; |
package transactor is new tauhop.tlm generic map( |
t_addr=>unsigned(31 downto 0), -- default assignment. Used only for non-stream interfaces. |
t_msg=>signed(63 downto 0), |
-- t_msg=>signed(63 downto 0), |
t_msg=>signed(31 downto 0), |
t_cnt=>unsigned(127 downto 0) |
); |
|