URL
https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk
Subversion Repositories axi4_tlm_bfm
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/trunk/rtl/vivado-synthesis/axi4-stream-bfm-master.vhdl
0,0 → 1,160
--/* |
-- This file is part of the AXI4 Transactor and Bus Functional Model |
-- (axi4_tlm_bfm) project: |
-- http://www.opencores.org/project,axi4_tlm_bfm |
|
-- Description |
-- Implementation of AXI4 Master BFM core according to AXI4 protocol |
-- specification document. |
|
-- To Do: Implement AXI4-Lite and full AXI4 protocols. |
|
-- Author(s): |
-- - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com |
|
-- Copyright (C) 2012-2013 Authors and OPENCORES.ORG |
|
-- This source file may be used and distributed without |
-- restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains |
-- the original copyright notice and the associated disclaimer. |
|
-- This source file is free software; you can redistribute it |
-- and/or modify it under the terms of the GNU Lesser General |
-- Public License as published by the Free Software Foundation; |
-- either version 2.1 of the License, or (at your option) any |
-- later version. |
|
-- This source is distributed in the hope that it will be |
-- useful, but WITHOUT ANY WARRANTY; without even the implied |
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
-- PURPOSE. See the GNU Lesser General Public License for more |
-- details. |
|
-- You should have received a copy of the GNU Lesser General |
-- Public License along with this source; if not, download it |
-- from http://www.opencores.org/lgpl.shtml. |
--*/ |
library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; |
--library tauhop; use tauhop.axiTransactor.all; |
|
--/* TODO remove once generic packages are supported. */ |
library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all; |
|
entity axiBfmMaster is |
port(aclk,n_areset:in std_ulogic; |
-- /* BFM signalling. */ |
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false); |
readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports. |
|
-- /* AXI Master interface */ |
axiMaster_in:in t_axi4StreamTransactor_s2m; |
axiMaster_out:buffer t_axi4StreamTransactor_m2s; |
|
-- /* AXI Slave interface */ |
-- axiSlave_in:in tAxi4Transactor_m2s; |
-- axiSlave_out:buffer tAxi4Transactor_s2m; |
|
symbolsPerTransfer:in t_cnt; |
outstandingTransactions:buffer t_cnt; |
|
-- /* Debug ports. */ |
-- dbg_cnt:out unsigned(9 downto 0); |
-- dbg_axiRxFsm:out axiBfmStatesRx:=idle; |
dbg_axiTxFsm:out axiBfmStatesTx:=idle |
); |
end entity axiBfmMaster; |
|
architecture rtl of axiBfmMaster is |
-- /* Finite-state Machines. */ |
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle; |
|
-- /* BFM signalling. */ |
signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false); |
signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false); |
|
signal i_readResponse,i_writeResponse:t_bfm; |
|
begin |
-- /* Transaction counter. */ |
process(n_areset,symbolsPerTransfer,aclk) is begin |
--if not n_areset then outstandingTransactions<=symbolsPerTransfer; |
if falling_edge(aclk) then |
-- /* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */ |
if not n_areset then outstandingTransactions<=symbolsPerTransfer; |
else |
if outstandingTransactions<1 then |
outstandingTransactions<=symbolsPerTransfer; |
report "No more pending transactions." severity note; |
elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1; |
end if; |
end if; |
end if; |
end process; |
|
-- /* next-state logic for AXI4-Stream Master Tx BFM. */ |
axi_bfmTx_ns: process(all) is begin |
axiTxState<=next_axiTxState; |
|
if not n_areset then axiTxState<=idle; |
else |
case next_axiTxState is |
when idle=> |
if writeRequest.trigger xor i_writeRequest.trigger then axiTxState<=payload; end if; |
when payload=> |
if outstandingTransactions<1 then axiTxState<=endOfTx; end if; |
when endOfTx=> |
axiTxState<=idle; |
when others=>axiTxState<=idle; |
end case; |
end if; |
end process axi_bfmTx_ns; |
|
-- /* output logic for AXI4-Stream Master Tx BFM. */ |
axi_bfmTx_op: process(all) is begin |
i_writeResponse<=writeResponse; |
|
axiMaster_out.tValid<=false; |
axiMaster_out.tLast<=false; |
axiMaster_out.tData<=(others=>'Z'); |
i_writeResponse.trigger<=false; |
|
if writeRequest.trigger xor i_writeRequest.trigger then |
axiMaster_out.tData<=writeRequest.message; |
axiMaster_out.tValid<=true; |
end if; |
|
if not n_areset then axiMaster_out.tData<=(others=>'Z'); |
else |
case next_axiTxState is |
when payload=> |
axiMaster_out.tData<=writeRequest.message; |
axiMaster_out.tValid<=true; |
|
if axiMaster_in.tReady then |
i_writeResponse.trigger<=true; |
end if; |
|
-- /* TODO change to a flag at user.vhdl. Move outstandingTransactions to user.vhdl. */ |
if outstandingTransactions<1 then axiMaster_out.tLast<=true; end if; |
when others=> null; |
end case; |
end if; |
end process axi_bfmTx_op; |
|
-- /* state registers and pipelines for AXI4-Stream Tx BFM. */ |
process(n_areset,aclk) is begin |
if falling_edge(aclk) then |
next_axiTxState<=axiTxState; |
i_writeRequest<=writeRequest; |
end if; |
end process; |
|
process(aclk) is begin |
if rising_edge(aclk) then |
writeResponse<=i_writeResponse; |
end if; |
end process; |
|
dbg_axiTxFSM<=axiTxState; |
end architecture rtl; |
trunk/rtl/vivado-synthesis/axi4-stream-bfm-master.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/vivado-synthesis/pkg-axi-tlm.vhdl
===================================================================
--- trunk/rtl/vivado-synthesis/pkg-axi-tlm.vhdl (nonexistent)
+++ trunk/rtl/vivado-synthesis/pkg-axi-tlm.vhdl (revision 21)
@@ -0,0 +1,219 @@
+--/*
+-- This file is part of the AXI4 Transactor and Bus Functional Model
+-- (axi4_tlm_bfm) project:
+-- http://www.opencores.org/project,axi4_tlm_bfm
+
+-- Description
+-- Implementation of AXI4 transactor data structures and high-level API.
+
+-- To Do:
+
+-- Author(s):
+-- - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+-- Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+-- This source file may be used and distributed without
+-- restriction provided that this copyright statement is not
+-- removed from the file and that any derivative work contains
+-- the original copyright notice and the associated disclaimer.
+
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.opencores.org/lgpl.shtml.
+--*/
+--/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
+library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
+--use std.textio.all;
+library tauhop;
+
+--/* Record I/O data structures for AXI interface transactor (block interface). */
+package axiTLM is
+-- generic(
+-- type t_qualifier; type t_id; type t_dest; type t_user; type t_resp;
+-- package transactor is new tauhop.tlm generic map(<>)
+-- );
+-- /* Makes transactor.t_addr and transactor.t_msg visible. */
+-- use transactor.all;
+
+-- /* TODO remove once generic packages are supported. */
+ use tauhop.tlm.all;
+ --type boolean_vector is array(natural range<>) of boolean;
+ --subtype t_qualifier is boolean_vector(32/8-1 downto 0);
+ subtype t_qualifier is std_ulogic_vector(32/8-1 downto 0);
+ subtype t_id is unsigned(31 downto 0);
+ subtype t_dest is unsigned(3 downto 0);
+ subtype t_user is unsigned(7 downto 0);
+ subtype t_resp is unsigned(1 downto 0); --2 bits. b"00" = OKAY, b"01" = ExOKAY, b"10" = SLVERR (slave error), b"11" = DECERR (decode error).
+
+-- /* AXI Transactor block interfaces. */
+ type t_axi4Transactor_m2s is record
+-- /* Address must be unresolved, because you need to drive the read address only when read is asserted, and
+-- drive the write address when write is asserted. Resolution functions are not expected to know how to decide this.
+-- */
+-- /* Write address channel. */
+ awId:t_id;
+-- awLen:unsigned(7 downto 0); --8 bits as defined by the standard.
+-- awSize:unsigned(2 downto 0); --3 bits as defined by the standard. Burst size for write transfers.
+-- awBurst:
+-- awLock:
+-- awCache:
+-- awQoS:
+-- awRegion:
+-- awUser:
+ -- AXI4-Lite required signals.
+ awAddr:t_addr;
+ awProt:boolean;
+ awValid:boolean;
+
+-- /* Write data channel. */
+ wId:t_id;
+-- wLast:
+-- wUser:
+ -- AXI4-Lite required signals.
+ wValid:boolean;
+ wData:t_msg;
+-- wStrb:std_ulogic_vector(wData'length/8-1 downto 0); --default is all ones if master always performs full datawidth write transactions.
+ wStrb:t_qualifier; --default is all ones if master always performs full datawidth write transactions.
+
+-- /* Write response channel. */
+ bReady:boolean;
+
+-- /* Read address channel. */
+ arId:t_id;
+-- arLen:unsigned(7 downto 0); --8 bits as defined by the standard.
+-- arSize:unsigned(2 downto 0); --3 bits as defined by the standard.
+-- arBurst:
+-- arLock:
+-- arCache:
+-- arQoS:
+-- arRegion:
+-- arUser:
+ -- AXI4-Lite required signals.
+ arValid:boolean;
+ arAddr:t_addr;
+ arProt:boolean;
+
+-- /* Read data channel. */
+ rReady:boolean;
+ end record t_axi4Transactor_m2s;
+
+ type t_axi4Transactor_s2m is record
+-- /* Write address channel. */
+ awReady:boolean;
+
+-- /* Write data channel. */
+ wReady:boolean;
+
+-- /* Write response channel. */
+ bId:t_id;
+-- bUser:
+ -- AXI4-Lite required signals.
+ bValid:boolean;
+ bResp:t_resp;
+
+-- /* Read address channel. */
+ arReady:boolean;
+
+-- /* Read data channel. */
+ rId:t_id;
+-- rLast:
+-- rUser:
+ -- AXI4-Lite required signals.
+ rValid:boolean;
+ rData:t_msg;
+ rResp:t_resp;
+ end record t_axi4Transactor_s2m;
+
+ type t_axi4StreamTransactor_m2s is record
+-- /* AXI4 streaming interface. */
+ tValid:boolean;
+ tData:t_msg;
+ tStrb:t_qualifier;
+ tKeep:t_qualifier;
+ tLast:boolean;
+ tId:t_id;
+ tDest:t_dest;
+ tUser:t_user;
+ end record t_axi4StreamTransactor_m2s;
+
+ type t_axi4StreamTransactor_s2m is record
+ tReady:boolean;
+ end record t_axi4StreamTransactor_s2m;
+
+-- /* AXI Low-power interface. */
+-- type tAxiTransactor_lp is record
+-- cSysReq:
+-- cSysAck:
+-- cActive:
+-- end record tAxiTransactor_lp;
+
+ type t_fsm is (idle,sendAddr,startOfPacket,payload,endOfPacket,endOfTx);
+ type axiBfmStatesTx is (idle,payload,endOfTx);
+ type axiBfmStatesRx is (idle,checkAddr,startOfPacket,payload);
+
+ attribute enum_encoding:string;
+ attribute enum_encoding of axiBfmStatesTx:type is "00 01 10";
+
+ function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector;
+end package axiTLM;
+
+package body axiTLM is
+ function to_std_logic_vector(fsm:axiBfmStatesTx) return std_logic_vector is
+ variable r:std_logic_vector(1 downto 0);
+ begin
+ case fsm is
+ when idle=> r:=2x"0";
+ when payload=> r:=2x"1";
+ when endOfTx=> r:=2x"2";
+ when others=> null;
+ end case;
+ return r;
+ end function to_std_logic_vector;
+end package body axiTLM;
+
+
+--/* AXI Transactor API.
+-- * Generally, transactors are high-level bus interface models that perform
+-- * read/write transactions to/from the bus. These models are not concerned
+-- * with the low-level implementation of the bus protocol. However, the
+-- * TLM models encapsulate the lower-level models known as the BFM.
+-- * axiTLM uses generic package tauhop.tlm, hence inherits basic TLM types and
+-- * procedures generally used in any messaging system (i.e. address and message
+-- * information, and bus read/write methods). It also extends the tauhop.tlm
+-- * package with application-specific types, such as record structures specific
+-- * to the AXI protocol.
+-- * axiTransactor instantiates the axiTLM, and assigns specific types to the
+-- * transactor model.
+-- */
+--/*library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
+--library tauhop;
+--package transactor is new tauhop.tlm generic map(
+-- t_addr=>unsigned(31 downto 0), -- default assignment. Used only for non-stream interfaces.
+-- t_msg=>signed(63 downto 0),
+-- t_cnt=>unsigned(127 downto 0)
+--);
+
+--library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
+--library tauhop; use tauhop.transactor.all;
+--package axiTransactor is new tauhop.axiTLM generic map(
+-- t_qualifier=>boolean_vector(32/8-1 downto 0),
+-- t_id=>unsigned(7 downto 0),
+-- t_dest=>unsigned(3 downto 0),
+-- t_user=>unsigned(7 downto 0), --unsigned(86*2-1 downto 0),
+-- t_resp=>unsigned(1 downto 0), --only used for AXI4-Lite (non-streaming).
+-- transactor=>tauhop.transactor
+--);
+--*/
\ No newline at end of file
trunk/rtl/vivado-synthesis/pkg-axi-tlm.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/vivado-synthesis/pkg-tlm.vhdl
===================================================================
--- trunk/rtl/vivado-synthesis/pkg-tlm.vhdl (nonexistent)
+++ trunk/rtl/vivado-synthesis/pkg-tlm.vhdl (revision 21)
@@ -0,0 +1,93 @@
+--/*
+-- This file is part of the AXI4 Transactor and Bus Functional Model
+-- (axi4_tlm_bfm) project:
+-- http://www.opencores.org/project,axi4_tlm_bfm
+
+-- Description
+-- This implements a generic interface for transactors, and has a set
+-- of reusable procedures to read and write from / to a bus. This
+-- interface can be used in many different bus protocols, by means of
+-- instantiating this package. An example implementation for the AXI4
+-- protocol can be found at
+-- pkg-axi-tlm.vhdl
+-- under the axi4_tlm_bfm project.
+
+-- To Do:
+
+-- Author(s):
+-- - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+-- Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+-- This source file may be used and distributed without
+-- restriction provided that this copyright statement is not
+-- removed from the file and that any derivative work contains
+-- the original copyright notice and the associated disclaimer.
+
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.opencores.org/lgpl.shtml.
+--*/
+--/* FIXME VHDL-2008 instantiated package. Unsupported by VCS-MX, Quartus, and Vivado. QuestaSim/ModelSim supports well. */
+library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all;
+--use std.textio.all;
+
+package tlm is
+-- generic(type t_addr; type t_msg; type t_cnt);
+
+-- /* TODO remove once generic packages are supported. */
+ subtype t_addr is unsigned(31 downto 0);
+ subtype t_msg is signed(63 downto 0);
+ subtype t_cnt is unsigned(127 downto 0);
+
+-- /* BFM control interface. */
+ type t_bfm is record
+ address:t_addr;
+ message:t_msg;
+ trigger:boolean;
+ end record t_bfm;
+
+ procedure write(
+ signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
+ address:in t_addr; -- used only for non-stream interfaces.
+ data:in t_msg
+ );
+
+ procedure read(
+ signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
+ address:in t_addr -- used only for non-stream interfaces.
+ );
+end package tlm;
+
+package body tlm is
+ procedure write(
+ signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
+ address:in t_addr; -- used only for non-stream interfaces.
+ data:in t_msg
+ ) is begin
+ request.address<=address;
+ request.message<=data;
+ request.trigger<=not request.trigger;
+ end procedure write;
+
+ procedure read(
+ signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
+ address:in t_addr -- used only for non-stream interfaces.
+ ) is begin
+ request.address<=address;
+ request.trigger<=not request.trigger;
+ --report "request.address: " & to_hstring(request.address);
+ end procedure read;
+end package body tlm;
trunk/rtl/vivado-synthesis/pkg-tlm.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/rtl/vivado-synthesis/user.vhdl
===================================================================
--- trunk/rtl/vivado-synthesis/user.vhdl (nonexistent)
+++ trunk/rtl/vivado-synthesis/user.vhdl (revision 21)
@@ -0,0 +1,353 @@
+--/*
+-- This file is part of the AXI4 Transactor and Bus Functional Model
+-- (axi4_tlm_bfm) project:
+-- http://www.opencores.org/project,axi4_tlm_bfm
+
+-- Description
+-- Synthesisable use case for AXI4 on-chip messaging.
+
+-- To Do:
+
+-- Author(s):
+-- - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+-- Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+-- This source file may be used and distributed without
+-- restriction provided that this copyright statement is not
+-- removed from the file and that any derivative work contains
+-- the original copyright notice and the associated disclaimer.
+
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE. See the GNU Lesser General Public License for more
+-- details.
+
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.opencores.org/lgpl.shtml.
+--*/
+library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
+--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
+
+--/* TODO remove once generic packages are supported. */
+library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
+
+--/* synthesis translate_off */
+library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
+--/* synthesis translate_on */
+
+library altera; use altera.stp;
+
+
+entity user is port(
+-- /* Comment-out for simulation. */
+ clk,nReset:in std_ulogic;
+
+-- /* AXI Master interface */
+-- axiMaster_in:in t_axi4StreamTransactor_s2m;
+ axiMaster_out:buffer t_axi4StreamTransactor_m2s
+
+-- /* Debug ports. */
+);
+end entity user;
+
+architecture rtl of user is
+-- /* Global counters. */
+ constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
+ signal symbolsPerTransfer:t_cnt;
+ signal outstandingTransactions:t_cnt;
+
+-- /* BFM signalling. */
+ signal readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
+ signal writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
+ signal readResponse:t_bfm;
+ signal writeResponse:t_bfm;
+
+ type txStates is (idle,transmitting);
+ signal txFSM,i_txFSM:txStates;
+
+-- /* Tester signals. */
+-- /* synthesis translate_off */
+ signal clk,reset:std_ulogic:='0';
+-- /* synthesis translate_on */
+
+ signal cnt:unsigned(3 downto 0);
+ signal reset:std_ulogic:='0';
+ signal testerClk:std_ulogic;
+ --signal trigger:boolean;
+ signal dbg_axiTxFSM:axiBfmStatesTx;
+ signal anlysr_dataIn:std_logic_vector(127 downto 0);
+ signal anlysr_trigger:std_ulogic;
+
+ signal axiMaster_in:t_axi4StreamTransactor_s2m;
+ signal irq_write:std_ulogic; -- clock gating.
+
+begin
+-- /* Bus functional models. */
+ axiMaster: entity work.axiBfmMaster(rtl)
+ port map(
+ aclk=>irq_write, n_areset=>not reset,
+
+ readRequest=>readRequest, writeRequest=>writeRequest,
+ readResponse=>readResponse, writeResponse=>writeResponse,
+ axiMaster_in=>axiMaster_in,
+ axiMaster_out=>axiMaster_out,
+
+ symbolsPerTransfer=>symbolsPerTransfer,
+ outstandingTransactions=>outstandingTransactions,
+ dbg_axiTxFSM=>dbg_axiTxFSM
+ );
+
+-- /* Interrupt-request generator. */
+ irq_write<=clk when not reset else '0';
+
+-- /* Simulation Tester. */
+-- /* PLL to generate tester's clock. */
+ f100MHz: entity altera.pll(syn) port map(
+ areset=>'0', --not nReset,
+ inclk0=>clk,
+ c0=>testerClk,
+ locked=>open
+ );
+
+-- /* synthesis translate_off */
+ clk<=not clk after 10 ps;
+ process is begin
+ nReset<='1'; wait for 1 ps;
+ nReset<='0'; wait for 500 ps;
+ nReset<='1';
+ wait;
+ end process;
+-- /* synthesis translate_on */
+
+
+-- /* Hardware tester. */
+ por: process(nReset,clk) is
+ --variable cnt:unsigned(7 downto 0):=(others=>'1');
+ begin
+ if not nReset then cnt<=(others=>'1');
+ elsif rising_edge(clk) then
+ reset<='0';
+
+ if cnt>0 then reset<='1'; cnt<=cnt-1; end if;
+ end if;
+ end process por;
+
+-- /* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
+ --anlysr_trigger<='1' when writeRequest.trigger else '0';
+ anlysr_trigger<='1' when reset else '0';
+
+-- /* Disable this for synthesis as this is not currently synthesisable.
+-- Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
+-- */
+-- /* synthesis translate_off */
+ --framerFSM<=to_unsigned(<>,framerFSM'length);
+-- /* synthesis translate_on */
+
+ anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
+ anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
+ --anlysr_dataIn(2 downto 0) <= <>;
+ anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
+ anlysr_dataIn(18)<='1' when clk else '0';
+ anlysr_dataIn(19)<='1' when reset else '0';
+ anlysr_dataIn(20)<='1' when irq_write else '0';
+ anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
+ anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
+ anlysr_dataIn(86 downto 23)<=std_logic_vector(axiMaster_out.tData);
+ anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
+ anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
+ anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
+ anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
+ anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
+ --anlysr_dataIn(99 downto 98)<=to_std_logic_vector(txFSM);
+ anlysr_dataIn(101 downto 98)<=std_logic_vector(cnt);
+
+ anlysr_dataIn(anlysr_dataIn'high downto 106)<=(others=>'0');
+
+
+-- /* Simulate only if you have compiled Altera's simulation libraries. */
+ i_bistFramer_stp_analyser: entity altera.stp(syn) port map(
+ acq_clk=>testerClk,
+ acq_data_in=>anlysr_dataIn,
+ acq_trigger_in=>"1",
+ trigger_in=>anlysr_trigger
+ );
+
+
+
+-- /* Stimuli sequencer. TODO move to tester/stimuli.
+-- This emulates the AXI4-Stream Slave.
+-- */
+-- /* Simulation-only stimuli sequencer. */
+-- /* synthesis translate_off */
+ process is begin
+-- /* Fast read. */
+ while not axiMaster_out.tLast loop
+-- /* Wait for tValid to assert. */
+ while not axiMaster_out.tValid loop
+ wait until falling_edge(clk);
+ end loop;
+
+ axiMaster_in.tReady<=true;
+
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=false;
+ end loop;
+
+ wait until falling_edge(clk);
+
+-- /* Normal read. */
+ while not axiMaster_out.tLast loop
+-- /* Wait for tValid to assert. */
+ while not axiMaster_out.tValid loop
+ wait until falling_edge(clk);
+ end loop;
+
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=true;
+
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=false;
+ end loop;
+
+ for i in 0 to 10 loop
+ wait until falling_edge(clk);
+ end loop;
+
+-- /* One-shot read. */
+ axiMaster_in.tReady<=true;
+
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=false;
+
+ wait;
+ end process;
+-- /* synthesis translate_on */
+
+-- /* Synthesisable stimuli sequencer. */
+ process(clk) is begin
+ if falling_edge(clk) then
+ axiMaster_in.tReady<=false;
+ --if axiMaster_out.tValid and not axiMaster_out.tLast then
+ if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
+ axiMaster_in.tReady<=true;
+ end if;
+ end if;
+ end process;
+
+
+-- /* Data transmitter. */
+ sequencer_ns: process(all) is begin
+ txFSM<=i_txFSM;
+ if reset then txFSM<=idle;
+ else
+ case i_txFSM is
+ when idle=>
+ if outstandingTransactions>0 then txFSM<=transmitting; end if;
+ when transmitting=>
+ if axiMaster_out.tLast then
+ txFSM<=idle;
+ end if;
+ when others=> null;
+ end case;
+ end if;
+ end process sequencer_ns;
+
+-- /* Data transmitter. */
+ sequencer_op: process(reset,irq_write) is
+-- /* Local procedures to map BFM signals with the package procedure. */
+ procedure read(address:in t_addr) is begin
+ read(readRequest,address);
+ end procedure read;
+
+ procedure write(data:in t_msg) is begin
+ write(request=>writeRequest, address=>(others=>'-'), data=>data);
+ end procedure write;
+
+ variable isPktError:boolean;
+
+-- /* Tester variables. */
+-- /* Synthesis-only randomisation. */
+ variable rand0:signed(63 downto 0);
+-- /* Simulation-only randomisation. */
+-- /* synthesis translate_off */
+ variable rv0:RandomPType;
+-- /* synthesis translate_on */
+
+ begin
+ if reset then
+-- /* synthesis only. */
+ rand0:=(others=>'0');
+
+-- /* simulation only. */
+-- /* synthesis translate_off */
+ rv0.InitSeed(rv0'instance_name);
+-- /* synthesis translate_on */
+
+ --txFSM<=idle;
+ elsif falling_edge(irq_write) then
+ case txFSM is
+ when transmitting=>
+ if txFSM/=i_txFSM or writeResponse.trigger then
+-- /* synthesis translate_off */
+ write(rv0.RandSigned(axiMaster_out.tData'length));
+-- /* synthesis translate_on */
+ write(rand0);
+ rand0:=rand0+1;
+ end if;
+ when others=>null;
+ end case;
+ end if;
+ end process sequencer_op;
+
+ sequencer_regs: process(irq_write) is begin
+ if falling_edge(irq_write) then
+ i_txFSM<=txFSM;
+ end if;
+ end process sequencer_regs;
+
+
+-- /* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
+ process(reset,irq_write) is
+-- /* synthesis translate_off */
+ variable rv0:RandomPType;
+-- /* synthesis translate_on */
+ begin
+ if reset then
+-- /* synthesis translate_off */
+ rv0.InitSeed(rv0'instance_name);
+ symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
+ report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
+-- /* synthesis translate_on */
+
+ symbolsPerTransfer<=128x"8";
+ elsif rising_edge(irq_write) then
+ if axiMaster_out.tLast then
+-- /* synthesis only. */
+-- /* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
+ --symbolsPerTransfer<=(others=>'0');
+
+-- /* Testcase 2: number of symbols per transfer is randomised. */
+ --uniform(seed0,seed1,rand0);
+ --symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
+ --report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
+
+
+-- /* synthesis translate_off */
+ symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
+ report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length));
+-- /* synthesis translate_on */
+
+ symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
+ end if;
+ end if;
+ end process;
+end architecture rtl;
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trunk/rtl/vivado-synthesis/user.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
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