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URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

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  • This comparison shows the changes necessary to convert path 
    /axi4_tlm_bfm
    from Rev 4 to Rev 5
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Rev 4 → Rev 5

/trunk/rtl/user.vhdl
45,8 → 45,8
-- clk,reset:in std_ulogic;
/* AXI Master interface */
-- axiMaster_in:in tAxi4StreamTransactor_s2m;
axiMaster_out:buffer tAxi4StreamTransactor_m2s
-- axiMaster_in:in t_axi4StreamTransactor_s2m;
axiMaster_out:buffer t_axi4StreamTransactor_m2s
/* Debug ports. */
);
59,16 → 59,16
signal outstandingTransactions:t_cnt;
/* BFM signalling. */
signal readRequest,next_readRequest:tBfmCtrl:=((others=>'0'),(others=>'0'),false);
signal writeRequest,next_writeRequest:tBfmCtrl:=((others=>'0'),(others=>'0'),false);
signal readResponse,next_readResponse:tBfmCtrl;
signal writeResponse,next_writeResponse:tBfmCtrl;
signal readRequest,next_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal writeRequest,next_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal readResponse,next_readResponse:t_bfm;
signal writeResponse,next_writeResponse:t_bfm;
/* Tester signals. */
/* synthesis translate_off */
signal clk,reset:std_ulogic:='0';
signal axiMaster_in:tAxi4StreamTransactor_s2m;
signal axiMaster_in:t_axi4StreamTransactor_s2m;
/* synthesis translate_on */
signal irq_write:std_ulogic; -- clock gating.
/trunk/rtl/axi4-stream-bfm.vhdl
47,12 → 47,12
trigger:in boolean;
/* BFM signalling. */
readRequest,writeRequest:in tBfmCtrl:=((others=>'X'),(others=>'X'),false); -- this is tauhop.transactor.tBfmCtrl.
readResponse,writeResponse:buffer tBfmCtrl; -- use buffer until synthesis tools support reading from out ports.
readRequest,writeRequest:in t_bfm:=((others=>'X'),(others=>'X'),false); -- this is tauhop.transactor.t_bfm.
readResponse,writeResponse:buffer t_bfm; -- use buffer until synthesis tools support reading from out ports.
/* AXI Master interface */
axiMaster_in:in tAxi4StreamTransactor_s2m;
axiMaster_out:buffer tAxi4StreamTransactor_m2s;
axiMaster_in:in t_axi4StreamTransactor_s2m;
axiMaster_out:buffer t_axi4StreamTransactor_m2s;
-- /* AXI Slave interface */
-- axiSlave_in:in tAxi4Transactor_m2s;
73,11 → 73,11
signal axiTxState,next_axiTxState:axiBfmStatesTx:=idle;
/* General pipelines. */
signal i_axiMaster_out:tAxi4StreamTransactor_m2s;
signal i_axiMaster_out:t_axi4StreamTransactor_m2s;
/* BFM signalling. */
signal i_readRequest:tBfmCtrl:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:tBfmCtrl:=((others=>'0'),(others=>'0'),false);
signal i_readRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal i_writeRequest:t_bfm:=((others=>'0'),(others=>'0'),false);
signal response,i_response:boolean;
/trunk/rtl/packages/pkg-axi-tlm.vhdl
55,7 → 55,7
-- subtype t_resp is unsigned(1 downto 0); --2 bits. b"00" = OKAY, b"01" = ExOKAY, b"10" = SLVERR (slave error), b"11" = DECERR (decode error).
/* AXI Transactor block interfaces. */
type tAxi4Transactor_m2s is record
type t_axi4Transactor_m2s is record
/* Address must be unresolved, because you need to drive the read address only when read is asserted, and
drive the write address when write is asserted. Resolution functions are not expected to know how to decide this.
*/
104,9 → 104,9
/* Read data channel. */
rReady:boolean;
end record tAxi4Transactor_m2s;
end record t_axi4Transactor_m2s;
type tAxi4Transactor_s2m is record
type t_axi4Transactor_s2m is record
/* Write address channel. */
awReady:boolean;
131,9 → 131,9
rValid:boolean;
rData:t_msg;
rResp:t_resp;
end record tAxi4Transactor_s2m;
end record t_axi4Transactor_s2m;
type tAxi4StreamTransactor_m2s is record
type t_axi4StreamTransactor_m2s is record
/* AXI4 streaming interface. */
tValid:boolean;
tData:t_msg;
143,11 → 143,11
tId:t_id;
tDest:t_dest;
tUser:t_user;
end record tAxi4StreamTransactor_m2s;
end record t_axi4StreamTransactor_m2s;
type tAxi4StreamTransactor_s2m is record
type t_axi4StreamTransactor_s2m is record
tReady:boolean;
end record tAxi4StreamTransactor_s2m;
end record t_axi4StreamTransactor_s2m;
-- /* AXI Low-power interface. */
-- type tAxiTransactor_lp is record
/trunk/rtl/packages/pkg-tlm.vhdl
52,25 → 52,25
-- subtype t_msg is signed(63 downto 0);
/* BFM control interface. */
type tBfmCtrl is record
type t_bfm is record
address:t_addr;
message:t_msg;
trigger:boolean;
end record tBfmCtrl;
end record t_bfm;
procedure write(
signal request:inout tBfmCtrl; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr;
data:in t_msg
);
procedure writeStream(
signal request:inout tBfmCtrl;
signal request:inout t_bfm;
data:in t_msg
);
procedure read(
signal request:inout tBfmCtrl; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr
);
end package tlm;
77,7 → 77,7
 
package body tlm is
procedure write(
signal request:inout tBfmCtrl; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr;
data:in t_msg
) is begin
87,7 → 87,7
end procedure write;
procedure writeStream(
signal request:inout tBfmCtrl;
signal request:inout t_bfm;
data:in t_msg
) is begin
request.message<=data;
95,7 → 95,7
end procedure writeStream;
procedure read(
signal request:inout tBfmCtrl; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
signal request:inout t_bfm; --FIXME use inout because Quartus doesn't yet allow reading of "out" within a procedure. VHDL-2008 allows this, and QuestaSim works fine.
address:in t_addr
) is begin
request.address<=address;

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