URL
https://opencores.org/ocsvn/axi_master/axi_master/trunk
Subversion Repositories axi_master
Compare Revisions
- This comparison shows the changes necessary to convert path
/axi_master/trunk/src/base
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/def_ic.txt
31,6 → 31,8
|
INCLUDE def_ic_static.txt |
|
STARTUSER |
|
SWAP.GLOBAL #FFD #1 ##flip-flop delay |
|
SWAP.USER PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names |
44,6 → 46,8
SWAP.USER DATA_BITS 64 ##AXI data bits |
SWAP.USER ADDR_BITS 32 ##AXI address bits |
|
SWAP.USER SIZE_BITS 2 ##AXI size bits |
|
DEFINE.USER DEF_DECERR_SLV ##use interanl decode slave error |
|
SWAP.USER USER_BITS 4 ##AXI user bits |
/def_axi_master.txt
31,6 → 31,8
|
INCLUDE def_axi_master_static.txt |
|
STARTUSER |
|
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay |
|
SWAP.USER PREFIX axi_master ##prefix for all module and file names |
/def_ic_static.txt
27,6 → 27,10
//// //// |
//////////////////////////////////////////////////////////////////##> |
|
VERIFY (DATA_BITS in 32, 64) ##stub supports 32 or 64 bits data bus |
VERIFY (SIZE_BITS in 2, 3) ##stub supports 32 or 64 bits data bus |
|
|
SWAP.GLOBAL MODEL_NAME AXI interconnect fabric |
|
SWAP MSTRS MASTER_NUM |
52,7 → 56,7
ID ID_BITS input SON(CHANGE 1) |
ADDR ADDR_BITS input |
LEN 4 input |
SIZE 2 input |
SIZE SIZE_BITS input |
BURST 2 input |
CACHE 4 input |
PROT 3 input |
/axi_master.v
182,7 → 182,7
DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\ |
DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\ |
DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\ |
DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\ |
DEFCMD(SWAP.GLOBAL CONST(MSTR_ID_BITS) ID_BITS) \\ |
DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\ |
DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\ |
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\ |