URL
https://opencores.org/ocsvn/axi_master/axi_master/trunk
Subversion Repositories axi_master
Compare Revisions
- This comparison shows the changes necessary to convert path
/axi_master/trunk/src
- from Rev 13 to Rev 14
- ↔ Reverse comparison
Rev 13 → Rev 14
/base/ic_registry_resp.v
31,11 → 31,6
|
ITER MX |
ITER SX |
|
LOOP MX |
ITER MMX_IDX |
ENDLOOP MX |
|
|
module PREFIX_ic_registry_resp(PORTS); |
|
51,66 → 46,56
output [MSTR_BITS-1:0] SSX_MSTR; |
output SSX_OK; |
|
|
wire Amatch_MMX_IDGROUP_MMX_ID.IDX; |
|
|
wire Amatch_MMX_IDMMX_IDX; |
wire match_SSX_MMX_IDMMX_IDX; |
wire match_SSX_MMX_IDGROUP_MMX_ID.IDX; |
wire no_Amatch_MMX; |
|
wire cmd_push_MMX; |
wire cmd_push_MMX_IDMMX_IDX; |
wire cmd_push_MMX_IDGROUP_MMX_ID.IDX; |
|
wire cmd_pop_SSX; |
LOOP MX |
wire cmd_pop_MMX_IDMMX_IDX; |
ENDLOOP MX |
wire cmd_pop_MMX_IDGROUP_MMX_ID.IDX; |
|
wire [SLV_BITS-1:0] slave_in_MMX_IDMMX_IDX; |
wire [SLV_BITS-1:0] slave_out_MMX_IDMMX_IDX; |
wire slave_empty_MMX_IDMMX_IDX; |
wire slave_full_MMX_IDMMX_IDX; |
wire [SLV_BITS-1:0] slave_in_MMX_IDGROUP_MMX_ID.IDX; |
wire [SLV_BITS-1:0] slave_out_MMX_IDGROUP_MMX_ID.IDX; |
wire slave_empty_MMX_IDGROUP_MMX_ID.IDX; |
wire slave_full_MMX_IDGROUP_MMX_ID.IDX; |
|
reg [MSTR_BITS-1:0] ERR_MSTR_reg; |
wire [MSTR_BITS-1:0] ERR_MSTR; |
reg [MSTR_BITS-1:0] ERR_MSTR_reg; |
wire [MSTR_BITS-1:0] ERR_MSTR; |
|
reg [MSTR_BITS-1:0] SSX_MSTR; |
reg SSX_OK; |
reg [MSTR_BITS-1:0] SSX_MSTR; |
reg SSX_OK; |
|
|
|
|
assign Amatch_MMX_IDMMX_IDX = MMX_AID == ID_MMX_IDMMX_IDX; |
assign Amatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AID == ID_BITS'GROUP_MMX_ID; |
|
assign match_SSX_MMX_IDMMX_IDX = SSX_ID == ID_MMX_IDMMX_IDX; |
assign match_SSX_MMX_IDGROUP_MMX_ID.IDX = SSX_ID == ID_BITS'GROUP_MMX_ID; |
|
|
assign cmd_push_MMX = MMX_AVALID & MMX_AREADY; |
assign cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & Amatch_MMX_IDMMX_IDX; |
assign cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & Amatch_MMX_IDGROUP_MMX_ID.IDX; |
assign cmd_pop_SSX = SSX_VALID & SSX_READY & SSX_LAST; |
|
LOOP MX |
assign cmd_pop_MMX_IDMMX_IDX = CONCAT((cmd_pop_SSX & match_SSX_MMX_IDMMX_IDX) |); |
ENDLOOP MX |
|
|
assign slave_in_MMX_IDMMX_IDX = MMX_ASLV; |
LOOP MX |
assign cmd_pop_MMX_IDGROUP_MMX_ID.IDX = CONCAT((cmd_pop_SSX & match_SSX_MMX_IDGROUP_MMX_ID.IDX) |); |
ENDLOOP MX |
|
assign slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_ASLV; |
|
|
|
|
IFDEF DEF_DECERR_SLV |
LOOP MX |
assign no_Amatch_MMX = CONCAT((~Amatch_MMX_IDMMX_IDX) &); |
ENDLOOP MX |
assign no_Amatch_MMX = GONCAT.REV((~Amatch_MMX_IDGROUP_MMX_ID.IDX) &); |
|
|
always @(posedge clk or posedge reset) |
if (reset) |
ERR_MSTR_reg <= #FFD {MSTR_BITS{1'b0}}; |
LOOP MX |
else if (cmd_push_MMX & no_Amatch_MMX) |
ERR_MSTR_reg <= #FFD 'dMX; |
ENDLOOP MX |
else if (cmd_push_MMX & no_Amatch_MMX) ERR_MSTR_reg <= #FFD MSTR_BITS'dMX; |
|
assign ERR_MSTR = ERR_MSTR_reg; |
ELSE DEF_DECERR_SLV |
119,12 → 104,10
|
|
LOOP SX |
always @(SSX_ID or ERR_MSTR) |
always @(*) |
begin |
case (SSX_ID) |
LOOP MX |
ID_MMX_IDMMX_IDX : SSX_MSTR = 'dMX; |
ENDLOOP MX |
ID_BITS'GROUP_MMX_ID : SSX_MSTR = MSTR_BITS'dMX; |
default : SSX_MSTR = ERR_MSTR; |
endcase |
end |
132,9 → 115,7
always @(*) |
begin |
case (SSX_ID) |
LOOP MX |
ID_MMX_IDMMX_IDX : SSX_OK = slave_out_MMX_IDMMX_IDX == 'dSX; |
ENDLOOP MX |
ID_BITS'GROUP_MMX_ID : SSX_OK = slave_out_MMX_IDGROUP_MMX_ID.IDX == SLV_BITS'dSX; |
default : SSX_OK = 1'b1; //SLVERR |
endcase |
end |
142,20 → 123,20
|
CREATE prgen_fifo.v DEFCMD(SWAP CONST(#FFD) #FFD) |
LOOP MX |
LOOP MMX_IDX |
LOOP IX GROUP_MMX_ID.NUM |
prgen_fifo #(SLV_BITS, CMD_DEPTH) |
slave_fifo_MMX_IDMMX_IDX( |
.clk(clk), |
.reset(reset), |
.push(cmd_push_MMX_IDMMX_IDX), |
.pop(cmd_pop_MMX_IDMMX_IDX), |
.din(slave_in_MMX_IDMMX_IDX), |
.dout(slave_out_MMX_IDMMX_IDX), |
.empty(slave_empty_MMX_IDMMX_IDX), |
.full(slave_full_MMX_IDMMX_IDX) |
); |
slave_fifo_MMX_IDIX( |
.clk(clk), |
.reset(reset), |
.push(cmd_push_MMX_IDIX), |
.pop(cmd_pop_MMX_IDIX), |
.din(slave_in_MMX_IDIX), |
.dout(slave_out_MMX_IDIX), |
.empty(slave_empty_MMX_IDIX), |
.full(slave_full_MMX_IDIX) |
); |
|
ENDLOOP MMX_IDX |
ENDLOOP IX |
ENDLOOP MX |
|
|
/base/ic_decerr.v
53,7 → 53,6
reg RVALID; |
reg [4-1:0] rvalid_cnt; |
|
|
IFDEF TRUE (USER_BITS>0) |
assign BUSER = 'd0; |
assign RUSER = 'd0; |
/base/def_ic.txt
1,36 → 1,61
<##////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
//////////////////////////////////////////////////////////////////##> |
<##////////////////////////////////////////////////////////////////// |
//// //// |
//// Author: Eyal Hochberg //// |
//// eyal@provartec.com //// |
//// //// |
//// Downloaded from: http://www.opencores.org //// |
///////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Provartec LTD //// |
//// www.provartec.com //// |
//// info@provartec.com //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer.//// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation.//// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more//// |
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
//////////////////////////////////////////////////////////////////##> |
|
REQUIRE(1.3) |
|
INCLUDE def_ic_static.txt |
|
SWAP PREFIX PARENT ##prefix for all module and file names |
SWAP #FFD #1 ##flip-flop delay |
|
SWAP SLAVE_NUM 1 ##number of slaves |
SWAP.USER PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names |
|
SWAP USER_BITS 0 ##AXI user bits |
SWAP.USER MASTER_NUM 3 ##number of masters |
SWAP.USER SLAVE_NUM 6 ##number of slaves |
|
DEFINE.USER DEF_DECERR_SLV ##use interanl decode slave error |
|
SWAP ID_BITS 3 ##AXI ID bits |
|
GROUP M0_ID is { |
b000 |
b001 |
} |
GROUP M1_ID is { |
b011 |
} |
GROUP M2_ID is { |
b101 |
} |
|
SWAP.USER CMD_DEPTH 8 ##AXI command depth for read and write |
|
SWAP.USER DATA_BITS 64 ##AXI data bits |
SWAP.USER ADDR_BITS 32 ##AXI address bits |
|
SWAP.USER USER_BITS 4 ##AXI user bits |
/base/def_axi_master.txt
26,23 → 26,27
//// details. http://www.gnu.org/licenses/lgpl.html //// |
//// //// |
//////////////////////////////////////////////////////////////////##> |
|
INCLUDE def_axi_master_static.txt |
|
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay |
|
SWAP.USER PREFIX axi_master ##prefix for all module and file names |
|
SWAP.USER ID_BITS 4 ##AXI ID bits |
SWAP.USER ADDR_BITS 32 ##AXI address bits |
SWAP.USER DATA_BITS 64 ##AXI data bits |
SWAP.USER LEN_BITS 4 ##AXI LEN bits |
SWAP.USER SIZE_BITS 2 ##AXI SIZE bits |
|
SWAP.USER CMD_DEPTH 4 ##AXI command depth for read and write |
|
SWAP.USER ID_NUM 3 ##Number of IDs (internal masters) |
SWAP.USER ID0_VAL 'b0011 ##AXI ID0 |
SWAP.USER ID1_VAL 'b0010 ##AXI ID1 |
SWAP.USER ID2_VAL 'b1010 ##AXI ID2 |
|
|
VERIFY (VERSION >=1.3) else Version 1.3 or higher is required (Current version is VERSION) |
|
INCLUDE def_axi_master_static.txt |
|
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay |
|
SWAP.USER PREFIX axi_master ##prefix for all module and file names |
|
SWAP.USER ADDR_BITS 32 ##AXI address bits |
SWAP.USER DATA_BITS 64 ##AXI data bits |
SWAP.USER LEN_BITS 4 ##AXI LEN bits |
SWAP.USER SIZE_BITS 2 ##AXI SIZE bits |
|
SWAP.USER CMD_DEPTH 4 ##AXI command depth for read and write |
|
SWAP.USER ID_BITS 4 ##AXI ID bits |
|
GROUP.USER AXI_ID is { ##Supported AXI IDs (one per internal master) |
b0011 |
b0010 |
b1010 |
} |
|
/base/def_ic_static.txt
28,6 → 28,8
//////////////////////////////////////////////////////////////////##> |
|
##Static defines |
SWAP MODEL_NAME AXI interconnect fabric |
|
SWAP MSTRS MASTER_NUM |
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DEF_DECERR_SLV)) |
|
/base/def_axi_master_static.txt
88,4 → 88,7
addr_min SON(DEFAULT 0) |
addr_max SON(DEFAULT {DATA_BITS{1'b1}}) |
} |
|
SWAP ID_NUM GROUP_AXI_ID.NUM |
|
|
/base/ic.v
28,11 → 28,14
//////////////////////////////////////////////////////////////////##> |
|
OUTFILE PREFIX_ic.v |
INCLUDE def_ic.txt |
INCLUDE def_ic.txt |
|
ITER MX |
|
ITER SX SLAVE_NUM ##external slave ports don't include decerr slave |
|
##check all masters have IDs |
VERIFY (GROUP_MMX_ID.NUM > 0) else Master MX does not have group for AXI IDs |
|
module PREFIX_ic (PORTS); |
|
input clk; |
98,8 → 101,8
.MMX_AWGROUP_IC_AXI_CMD(MMX_AWGROUP_IC_AXI_CMD), |
.MMX_WGROUP_IC_AXI_W(MMX_WGROUP_IC_AXI_W), |
.SSX_WGROUP_IC_AXI_W(SSX_WGROUP_IC_AXI_W), |
.SSX_AWVALID(SSX_AWVALID), |
.SSX_AWREADY(SSX_AWREADY), |
.SSX_AWVALID(SSX_AWVALID), |
.SSX_AWREADY(SSX_AWREADY), |
.SSX_AWMSTR(SSX_AWMSTR), |
STOMP , |
); |
/base/ic_registry_wr.v
32,10 → 32,6
ITER MX |
ITER SX |
|
LOOP MX |
ITER MMX_IDX |
ENDLOOP MX |
|
module PREFIX_ic_registry_wr(PORTS); |
|
|
45,82 → 41,78
|
port MMX_AWGROUP_IC_AXI_CMD; |
|
input [ID_BITS-1:0] MMX_WID; |
input [ID_BITS-1:0] MMX_WID; |
input MMX_WVALID; |
input MMX_WREADY; |
input MMX_WLAST; |
output [SLV_BITS-1:0] MMX_WSLV; |
output [SLV_BITS-1:0] MMX_WSLV; |
output MMX_WOK; |
|
input SSX_AWVALID; |
input SSX_AWREADY; |
input [MSTR_BITS-1:0] SSX_AWMSTR; |
input [MSTR_BITS-1:0] SSX_AWMSTR; |
input SSX_WVALID; |
input SSX_WREADY; |
input SSX_WLAST; |
|
|
wire AWmatch_MMX_IDMMX_IDX; |
wire Wmatch_MMX_IDMMX_IDX; |
wire AWmatch_MMX_IDGROUP_MMX_ID.IDX; |
wire Wmatch_MMX_IDGROUP_MMX_ID.IDX; |
|
wire cmd_push_MMX; |
wire cmd_push_MMX_IDMMX_IDX; |
wire cmd_push_MMX_IDGROUP_MMX_ID.IDX; |
|
wire cmd_pop_MMX; |
wire cmd_pop_MMX_IDMMX_IDX; |
wire cmd_pop_MMX_IDGROUP_MMX_ID.IDX; |
|
wire [SLV_BITS-1:0] slave_in_MMX_IDMMX_IDX; |
wire [SLV_BITS-1:0] slave_out_MMX_IDMMX_IDX; |
wire slave_empty_MMX_IDMMX_IDX; |
wire slave_full_MMX_IDMMX_IDX; |
wire [SLV_BITS-1:0] slave_in_MMX_IDGROUP_MMX_ID.IDX; |
wire [SLV_BITS-1:0] slave_out_MMX_IDGROUP_MMX_ID.IDX; |
wire slave_empty_MMX_IDGROUP_MMX_ID.IDX; |
wire slave_full_MMX_IDGROUP_MMX_ID.IDX; |
|
wire cmd_push_SSX; |
wire cmd_pop_SSX; |
wire [MSTR_BITS-1:0] master_in_SSX; |
wire [MSTR_BITS-1:0] master_out_SSX; |
wire [MSTR_BITS-1:0] master_in_SSX; |
wire [MSTR_BITS-1:0] master_out_SSX; |
wire master_empty_SSX; |
wire master_full_SSX; |
|
reg [SLV_BITS-1:0] MMX_WSLV; |
reg [SLV_BITS-1:0] MMX_WSLV; |
reg MMX_WOK; |
|
|
|
|
assign AWmatch_MMX_IDMMX_IDX = MMX_AWID == ID_MMX_IDMMX_IDX; |
assign AWmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AWID == ID_BITS'GROUP_MMX_ID; |
|
assign Wmatch_MMX_IDMMX_IDX = MMX_WID == ID_MMX_IDMMX_IDX; |
assign Wmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_WID == ID_BITS'GROUP_MMX_ID; |
|
|
assign cmd_push_MMX = MMX_AWVALID & MMX_AWREADY; |
assign cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & AWmatch_MMX_IDMMX_IDX; |
assign cmd_push_MMX_IDGROUP_MMX_ID.IDX = cmd_push_MMX & AWmatch_MMX_IDGROUP_MMX_ID.IDX; |
assign cmd_pop_MMX = MMX_WVALID & MMX_WREADY & MMX_WLAST; |
assign cmd_pop_MMX_IDMMX_IDX = cmd_pop_MMX & Wmatch_MMX_IDMMX_IDX; |
assign cmd_pop_MMX_IDGROUP_MMX_ID.IDX = cmd_pop_MMX & Wmatch_MMX_IDGROUP_MMX_ID.IDX; |
|
assign cmd_push_SSX = SSX_AWVALID & SSX_AWREADY; |
assign cmd_pop_SSX = SSX_WVALID & SSX_WREADY & SSX_WLAST; |
assign master_in_SSX = SSX_AWMSTR; |
|
assign slave_in_MMX_IDMMX_IDX = MMX_AWSLV; |
assign slave_in_MMX_IDGROUP_MMX_ID.IDX = MMX_AWSLV; |
|
|
LOOP MX |
always @(MMX_WID |
or slave_out_MMX_IDMMX_IDX |
) |
always @(*) |
begin |
case (MMX_WID) |
ID_MMX_IDMMX_IDX : MMX_WSLV = slave_out_MMX_IDMMX_IDX; |
ID_BITS'GROUP_MMX_ID : MMX_WSLV = slave_out_MMX_IDGROUP_MMX_ID.IDX; |
default : MMX_WSLV = SERR; |
endcase |
end |
|
always @(MMX_WSLV |
or master_out_SSX |
) |
always @(*) |
begin |
case (MMX_WSLV) |
'dSX : MMX_WOK = master_out_SSX == 'dMX; |
SLV_BITS'dSX : MMX_WOK = master_out_SSX == MSTR_BITS'dMX; |
default : MMX_WOK = 1'b0; |
endcase |
end |
128,25 → 120,25
ENDLOOP MX |
|
LOOP MX |
LOOP MMX_IDX |
LOOP IX GROUP_MMX_ID.NUM |
prgen_fifo #(SLV_BITS, CMD_DEPTH) |
slave_fifo_MMX_IDMMX_IDX( |
.clk(clk), |
.reset(reset), |
.push(cmd_push_MMX_IDMMX_IDX), |
.pop(cmd_pop_MMX_IDMMX_IDX), |
.din(slave_in_MMX_IDMMX_IDX), |
.dout(slave_out_MMX_IDMMX_IDX), |
.empty(slave_empty_MMX_IDMMX_IDX), |
.full(slave_full_MMX_IDMMX_IDX) |
); |
slave_fifo_MMX_IDIX( |
.clk(clk), |
.reset(reset), |
.push(cmd_push_MMX_IDIX), |
.pop(cmd_pop_MMX_IDIX), |
.din(slave_in_MMX_IDIX), |
.dout(slave_out_MMX_IDIX), |
.empty(slave_empty_MMX_IDIX), |
.full(slave_full_MMX_IDIX) |
); |
|
ENDLOOP MMX_IDX |
ENDLOOP MX |
ENDLOOP IX |
ENDLOOP MX |
|
|
|
LOOP SX |
LOOP SX |
prgen_fifo #(MSTR_BITS, 32) |
master_fifo_SSX( |
.clk(clk), |
159,7 → 151,7
.full(master_full_SSX) |
); |
|
ENDLOOP SX |
ENDLOOP SX |
|
endmodule |
|
/base/axi_master.v
125,8 → 125,7
|
INCLUDE def_axi_master.txt |
|
|
ITER IX ID_NUM |
ITER IDX ID_NUM |
module PREFIX(PORTS); |
|
`include "prgen_rand.v" |
143,34 → 142,34
//random parameters |
integer GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND.DEFAULT; |
|
wire GROUP_STUB_AXI_IX; |
wire idle_IX; |
wire scrbrd_empty_IX; |
wire GROUP_STUB_AXI_IDX; |
wire idle_IDX; |
wire scrbrd_empty_IDX; |
|
|
always @(*) |
begin |
#FFD; |
PREFIX_singleIX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND; |
PREFIX_singleIDX.GROUP_AXI_MASTER_RAND = GROUP_AXI_MASTER_RAND; |
end |
|
assign idle = CONCAT(idle_IX &); |
assign scrbrd_empty = CONCAT(scrbrd_empty_IX &); |
assign idle = CONCAT(idle_IDX &); |
assign scrbrd_empty = CONCAT(scrbrd_empty_IDX &); |
|
|
CREATE axi_master_single.v |
|
LOOP IX ID_NUM |
PREFIX_single #(IX, IDIX_VAL, CMD_DEPTH) |
PREFIX_singleIX( |
LOOP IDX ID_NUM |
PREFIX_single #(IDX, ID_BITS'GROUP_AXI_ID[IDX], CMD_DEPTH) |
PREFIX_singleIDX( |
.clk(clk), |
.reset(reset), |
.GROUP_STUB_AXI(GROUP_STUB_AXI_IX), |
.idle(idle_IX), |
.scrbrd_empty(scrbrd_empty_IX) |
.GROUP_STUB_AXI(GROUP_STUB_AXI_IDX), |
.idle(idle_IDX), |
.scrbrd_empty(scrbrd_empty_IDX) |
); |
|
ENDLOOP IX |
ENDLOOP IDX |
|
IFDEF TRUE(ID_NUM==1) |
|
179,24 → 178,27
|
ELSE TRUE(ID_NUM==1) |
|
CREATE ic.v \\ |
DEFCMD(SWAP.GLOBAL PARENT PREFIX) \\ |
CREATE ic.v \\ |
DEFCMD(SWAP.GLOBAL CONST(PREFIX) PREFIX) \\ |
DEFCMD(SWAP.GLOBAL MASTER_NUM ID_NUM) \\ |
DEFCMD(SWAP.GLOBAL SLAVE_NUM 1) \\ |
DEFCMD(SWAP.GLOBAL CONST(ID_BITS) ID_BITS) \\ |
DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\ |
DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\ |
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) |
LOOP IX ID_NUM |
STOMP NEWLINE |
DEFCMD(LOOP.GLOBAL MIX_IDX 1) \\ |
DEFCMD(SWAP.GLOBAL ID_MIX_ID0 ID_BITSIDIX_VAL) |
ENDLOOP IX |
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\ |
DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0) |
LOOP IDX ID_NUM |
STOMP NEWLINE |
DEFCMD(GROUP.GLOBAL MIDX_ID overrides { ) \\ |
DEFCMD(GROUP_AXI_ID[IDX]) \\ |
DEFCMD(}) |
ENDLOOP IDX |
|
|
PREFIX_ic PREFIX_ic( |
.clk(clk), |
.reset(reset), |
.MIX_GROUP_STUB_AXI(GROUP_STUB_AXI_IX), |
.MIDX_GROUP_STUB_AXI(GROUP_STUB_AXI_IDX), |
.S0_GROUP_STUB_AXI(GROUP_STUB_AXI), |
STOMP , |
|
222,7 → 224,7
begin |
check_master_num("enable", master_num); |
case (master_num) |
IX : PREFIX_singleIX.enable = 1; |
IDX : PREFIX_singleIDX.enable = 1; |
endcase |
end |
endtask |
229,7 → 231,7
|
task enable_all; |
begin |
PREFIX_singleIX.enable = 1; |
PREFIX_singleIDX.enable = 1; |
end |
endtask |
|
240,7 → 242,7
begin |
check_master_num("write_single", master_num); |
case (master_num) |
IX : PREFIX_singleIX.write_single(addr, wdata); |
IDX : PREFIX_singleIDX.write_single(addr, wdata); |
endcase |
end |
endtask |
252,7 → 254,7
begin |
check_master_num("read_single", master_num); |
case (master_num) |
IX : PREFIX_singleIX.read_single(addr, rdata); |
IDX : PREFIX_singleIDX.read_single(addr, rdata); |
endcase |
end |
endtask |
264,7 → 266,7
begin |
check_master_num("check_single", master_num); |
case (master_num) |
IX : PREFIX_singleIX.check_single(addr, expected); |
IDX : PREFIX_singleIDX.check_single(addr, expected); |
endcase |
end |
endtask |
276,7 → 278,7
begin |
check_master_num("write_and_check_single", master_num); |
case (master_num) |
IX : PREFIX_singleIX.write_and_check_single(addr, data); |
IDX : PREFIX_singleIDX.write_and_check_single(addr, data); |
endcase |
end |
endtask |
289,7 → 291,7
begin |
check_master_num("insert_wr_cmd", master_num); |
case (master_num) |
IX : PREFIX_singleIX.insert_wr_cmd(addr, len, size); |
IDX : PREFIX_singleIDX.insert_wr_cmd(addr, len, size); |
endcase |
end |
endtask |
302,7 → 304,7
begin |
check_master_num("insert_rd_cmd", master_num); |
case (master_num) |
IX : PREFIX_singleIX.insert_rd_cmd(addr, len, size); |
IDX : PREFIX_singleIDX.insert_rd_cmd(addr, len, size); |
endcase |
end |
endtask |
313,7 → 315,7
begin |
check_master_num("insert_wr_data", master_num); |
case (master_num) |
IX : PREFIX_singleIX.insert_wr_data(wdata); |
IDX : PREFIX_singleIDX.insert_wr_data(wdata); |
endcase |
end |
endtask |
326,7 → 328,7
begin |
check_master_num("insert_wr_incr_data", master_num); |
case (master_num) |
IX : PREFIX_singleIX.insert_wr_incr_data(addr, len, size); |
IDX : PREFIX_singleIDX.insert_wr_incr_data(addr, len, size); |
endcase |
end |
endtask |
337,7 → 339,7
begin |
check_master_num("insert_rand_chk", master_num); |
case (master_num) |
IX : PREFIX_singleIX.insert_rand_chk(burst_num); |
IDX : PREFIX_singleIDX.insert_rand_chk(burst_num); |
endcase |
end |
endtask |
345,7 → 347,6
task insert_rand; |
input [31:0] burst_num; |
|
ITER IDX ID_NUM |
reg [31:0] burst_numIDX; |
integer remain; |
begin |
/base/axi_master_single.v
50,7 → 50,6
(MAX_CMDS <= 256) ? 8 : |
(MAX_CMDS <= 512) ? 9 : 0; //0 is ilegal |
|
|
|
input clk; |
input reset; |
75,6 → 74,8
reg rd_enable = 0; |
reg wr_enable = 0; |
reg wait_for_write = 0; |
reg err_on_wr_resp = 1; |
reg err_on_rd_resp = 1; |
|
reg scrbrd_enable = 0; |
reg [LEN_BITS-1:0] wvalid_cnt; |
225,7 → 226,7
assign AWADDR = wr_cmd_addr; |
assign AWLEN = wr_cmd_len; |
assign AWSIZE = wr_cmd_size; |
assign AWID = MASTER_ID; |
assign AWID = MASTER_ID; |
assign AWBURST = 2'd1; //INCR only |
assign AWCACHE = 4'd0; //not supported |
assign AWPROT = 4'd0; //not supported |
249,7 → 250,7
assign ARLOCK = 2'd0; //not supported |
|
assign rd_fifo_data_in = RDATA; |
assign rd_fifo_resp_in = BRESP; |
assign rd_fifo_resp_in = RRESP; |
|
assign wr_data_bytes = 1'b1 << wr_data_size; |
|
548,6 → 549,8
rd_fifo_pop = 1; |
@(posedge clk); #FFD; |
rd_fifo_pop = 0; |
if ((resp != 2'b00) && (err_on_rd_resp)) |
$display("PREFIX_MASTER%0d: RRESP_ERROR: Received RRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time); |
end |
endtask |
|
582,6 → 585,8
wr_resp_pop = 1; |
@(posedge clk); #FFD; |
wr_resp_pop = 0; |
if ((resp != 2'b00) && (err_on_wr_resp)) |
$display("PREFIX_MASTER%0d: BRESP_ERROR: Received BRESP 2'b%0b.\tTime: %0d ns.", MASTER_NUM, resp, $time); |
end |
endtask |
|
638,7 → 643,7
begin |
read_single_ack(addr, rdata, resp); |
if (rdata !== expected) |
$display("MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time); |
$display("PREFIX_MASTER%0d: CHK_SINGLE_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected, rdata, $time); |
end |
endtask |
|
678,7 → 683,7
rdata_masked = rdata & mask; |
|
if (expected_data !== rdata_masked) |
$display("MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time); |
$display("PREFIX_MASTER%0d: SCRBRD_ERROR: Address: 0x%0h, Expected: 0x%0h, Received: 0x%0h.\tTime: %0d ns.", MASTER_NUM, addr, expected_data, rdata, $time); |
end |
endtask |
|
/base/ic_dec.v
32,10 → 32,6
ITER MX |
ITER SX |
|
LOOP MX |
ITER MMX_IDX |
ENDLOOP MX |
|
module PREFIX_ic_dec (PORTS); |
|
input [ADDR_BITS-1:0] MMX_AADDR; |
49,17 → 45,17
reg [SLV_BITS-1:0] MMX_ASLV; |
reg MMX_AIDOK; |
|
LOOP MX |
LOOP MX |
always @(MMX_AADDR or MMX_AIDOK) |
begin |
IFDEF TRUE(SLAVE_NUM==1) |
case (MMX_AIDOK) |
1'b1 : MMX_ASLV = 'd0; |
1'b1 : MMX_ASLV = SLV_BITS'd0; |
ELSE TRUE(SLAVE_NUM==1) |
case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]}) |
{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = 'dSX; |
{1'b1, BIN(SX SLV_BITS)} : MMX_ASLV = SLV_BITS'dSX; |
ENDIF TRUE(SLAVE_NUM==1) |
default : MMX_ASLV = 'dSERR; |
default : MMX_ASLV = SLV_BITS'dSERR; |
endcase |
end |
|
66,14 → 62,14
always @(MMX_AID) |
begin |
case (MMX_AID) |
ID_MMX_IDMMX_IDX : MMX_AIDOK = 1'b1; |
ID_BITS'GROUP_MMX_ID : MMX_AIDOK = 1'b1; |
default : MMX_AIDOK = 1'b0; |
endcase |
end |
|
ENDLOOP MX |
ENDLOOP MX |
|
endmodule |
endmodule |
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