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URL https://opencores.org/ocsvn/axi_master/axi_master/trunk

Subversion Repositories axi_master

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  • This comparison shows the changes necessary to convert path 
    /axi_master/trunk
    from Rev 16 to Rev 17
    ↔ Reverse comparison
  •

Rev 16 → Rev 17

/src/base/ic_registry_resp.v
72,9 → 72,9
assign Amatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AID == ID_BITS'GROUP_MMX_ID;
assign Amatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AID == ID_BITS'bADD_IDGROUP_MMX_ID;
assign match_SSX_MMX_IDGROUP_MMX_ID.IDX = SSX_ID == ID_BITS'GROUP_MMX_ID;
assign match_SSX_MMX_IDGROUP_MMX_ID.IDX = SSX_ID == ID_BITS'bADD_IDGROUP_MMX_ID;
 
assign cmd_push_MMX = MMX_AVALID & MMX_AREADY;
101,13 → 101,13
ELSE DEF_DECERR_SLV
assign ERR_MSTR = 'd0;
ENDIF DEF_DECERR_SLV
 
LOOP SX
always @(*)
begin
case (SSX_ID)
ID_BITS'GROUP_MMX_ID : SSX_MSTR = MSTR_BITS'dMX;
case (SSX_ID)
ID_BITS'bADD_IDGROUP_MMX_ID : SSX_MSTR = MSTR_BITS'dMX;
default : SSX_MSTR = ERR_MSTR;
endcase
end
114,8 → 114,8
always @(*)
begin
case (SSX_ID)
ID_BITS'GROUP_MMX_ID : SSX_OK = slave_out_MMX_IDGROUP_MMX_ID.IDX == SLV_BITS'dSX;
case (SSX_ID)
ID_BITS'bADD_IDGROUP_MMX_ID : SSX_OK = slave_out_MMX_IDGROUP_MMX_ID.IDX == SLV_BITS'dSX;
default : SSX_OK = 1'b1; //SLVERR
endcase
end
/src/base/def_ic.txt
47,16 → 47,21
SWAP.USER USER_BITS 4 ##AXI user bits
 
SWAP.USER ID_BITS 3 ##AXI ID bits
SWAP.USER MSTR_ID_BITS 4 ##AXI ID bits
 
GROUP.USER M0_ID is { ##Supported AXI IDs for master 0
b000
b001
UNDEF.USER UNIQUE_ID ##If defined all IDs must be unique, else bits will be added to slave IDs to identify masters
 
GROUP.USER M0_ID is { ##Supported AXI IDs for master 0 (binary)
000
001
}
GROUP.USER M1_ID is { ##Supported AXI IDs for master
b011
GROUP.USER M1_ID is { ##Supported AXI IDs for master 1 (binary)
011
}
GROUP.USER M2_ID is { ##Supported AXI IDs for master 2
b101
GROUP.USER M2_ID is { ##Supported AXI IDs for master 2 (binary)
000
100
101
}
/src/base/def_axi_master.txt
45,8 → 45,8
SWAP.USER ID_BITS 4 ##AXI ID bits
GROUP.USER AXI_ID is { ##Supported AXI IDs (one per internal master)
b0011
b0010
b1010
0011
0010
1010
}
 
/src/base/ic_addr.v
65,12 → 65,21
reg [EXPR(MSTR_BITS-1):0] SSX_AMSTR;
 
wire SSX_AIDOK;
 
wire [EXPR(ADDR_BITS-1):0] MMX_AADDR_valid;
wire [EXPR(ID_BITS-1):0] MMX_AID_valid;
 
 
assign MMX_AADDR_valid = MMX_AADDR & {ADDR_BITS{MMX_AVALID}};
assign MMX_AID_valid = MMX_AID & {ID_BITS{MMX_AVALID}};
 
CREATE ic_dec.v def_ic.txt
PREFIX_ic_dec
PREFIX_ic_dec (
.MMX_AADDR(MMX_AADDR),
.MMX_AID(MMX_AID),
.MMX_AADDR(MMX_AADDR_valid),
.MMX_AID(MMX_AID_valid),
.MMX_ASLV(MMX_ASLV),
.MMX_AIDOK(MMX_AIDOK),
STOMP ,
/src/base/def_ic_static.txt
40,8 → 40,16
 
SWAP SERR EXPR(SLVS-1)
 
IFDEF UNIQUE_ID
SWAP ID_BITS MSTR_ID_BITS
SWAP ADD_ID NULL
ELSE UNIQUE_ID
SWAP ID_BITS EXPR(MSTR_ID_BITS+EXTRA_BITS)
SWAP ADD_ID BIN(MX MSTR_BITS NOPRE)_
ENDIF UNIQUE_ID
GROUP IC_AXI_A is {
ID ID_BITS input
ID ID_BITS input SON(CHANGE 1)
ADDR ADDR_BITS input
LEN 4 input
SIZE 2 input
55,7 → 63,7
}
 
GROUP IC_AXI_W is {
ID ID_BITS input
ID ID_BITS input SON(CHANGE 1)
DATA DATA_BITS input
STRB DATA_BITS/8 input
LAST 1 input
65,7 → 73,7
}
 
GROUP IC_AXI_B is {
ID ID_BITS output
ID ID_BITS output SON(CHANGE 1)
RESP 2 output
USER USER_BITS output
VALID 1 output
73,7 → 81,7
}
 
GROUP IC_AXI_R is {
ID ID_BITS output
ID ID_BITS output SON(CHANGE 1)
DATA DATA_BITS output
RESP 2 output
LAST 1 output
92,7 → 100,7
 
GROUP IC_AXI_CMD is {
SLV SLV_BITS input
ID ID_BITS input
ID ID_BITS input SON(CHANGE 1)
VALID 1 input
READY 1 input
}
/src/base/ic.v
37,14 → 37,16
VERIFY(UNIQUE(GONCAT(GROUP_MMX_ID ,))) ##Master MX IDs are not unique
 
IF UNIQUE_ID VERIFY (UNIQUE(CONCAT(GONCAT(GROUP_MMX_ID ,) ,))) ##Masters IDs are not unique (Undefinig UNIQUE_ID will make IDs unique internally)
 
 
module PREFIX_ic (PORTS);
 
input clk;
input reset;
 
port MMX_GROUP_IC_AXI;
revport SSX_GROUP_IC_AXI;
port MMX_GROUP_IC_AXI.PARAM(EXTRA_BITS 0);
revport SSX_GROUP_IC_AXI.PARAM(EXTRA_BITS MSTR_BITS);
ENDITER SX
ITER SX ##use global iterator
55,14 → 57,44
wire [EXPR(MSTR_BITS-1):0] SSX_ARMSTR;
wire SSX_AWIDOK;
wire SSX_ARIDOK;
 
 
CREATE ic_addr.v def_ic.txt
IFDEF UNIQUE_ID
wire [EXPR(MSTR_ID_BITS-1):0] MMX_AWID_FULL;
wire [EXPR(MSTR_ID_BITS-1):0] MMX_ARID_FULL;
wire [EXPR(MSTR_ID_BITS-1):0] MMX_WID_FULL;
wire [EXPR(MSTR_ID_BITS-1):0] MMX_BID_FULL;
wire [EXPR(MSTR_ID_BITS-1):0] MMX_RID_FULL;
assign MMX_AWID_FULL = MMX_AWID;
assign MMX_WID_FULL = MMX_WID;
assign MMX_ARID_FULL = MMX_ARID;
assign MMX_RID = MMX_RID_FULL;
assign MMX_BID = MMX_BID_FULL;
ELSE UNIQUE_ID
wire [EXPR(MSTR_ID_BITS+MSTR_BITS-1):0] MMX_AWID_FULL;
wire [EXPR(MSTR_ID_BITS+MSTR_BITS-1):0] MMX_WID_FULL;
wire [EXPR(MSTR_ID_BITS+MSTR_BITS-1):0] MMX_BID_FULL;
wire [EXPR(MSTR_ID_BITS+MSTR_BITS-1):0] MMX_ARID_FULL;
wire [EXPR(MSTR_ID_BITS+MSTR_BITS-1):0] MMX_RID_FULL;
assign MMX_AWID_FULL = {BIN(MX MSTR_BITS), MMX_AWID};
assign MMX_WID_FULL = {BIN(MX MSTR_BITS), MMX_WID};
assign MMX_ARID_FULL = {BIN(MX MSTR_BITS), MMX_ARID};
assign MMX_RID[MSTR_ID_BITS-1:0] = MMX_RID_FULL;
assign MMX_BID[MSTR_ID_BITS-1:0] = MMX_BID_FULL;
ENDIF UNIQUE_ID
CREATE ic_addr.v def_ic.txt DEFCMD(SWAP.GLOBAL EXTRA_BITS MSTR_BITS)
PREFIX_ic_addr
PREFIX_ic_addr_rd (.clk(clk),
.reset(reset),
.MMX_ASLV(MMX_ARSLV),
.MMX_AGROUP_IC_AXI_A(MMX_ARGROUP_IC_AXI_A),
.MMX_AID(MMX_ARID_FULL),
.MMX_AGROUP_IC_AXI_A.SON(CHANGE!=1)(MMX_ARGROUP_IC_AXI_A),
.SSX_AMSTR(SSX_ARMSTR),
.SSX_AIDOK(SSX_ARIDOK),
.SSX_AGROUP_IC_AXI_A(SSX_ARGROUP_IC_AXI_A),
75,7 → 107,8
.clk(clk),
.reset(reset),
.MMX_ASLV(MMX_AWSLV),
.MMX_AGROUP_IC_AXI_A(MMX_AWGROUP_IC_AXI_A),
.MMX_AID(MMX_AWID_FULL),
.MMX_AGROUP_IC_AXI_A.SON(CHANGE!=1)(MMX_AWGROUP_IC_AXI_A),
.SSX_AMSTR(SSX_AWMSTR),
.SSX_AIDOK(SSX_AWIDOK),
.SSX_AGROUP_IC_AXI_A(SSX_AWGROUP_IC_AXI_A),
83,25 → 116,29
);
 
CREATE ic_resp.v def_ic.txt DEFCMD(SWAP CONST(RW) R)
CREATE ic_resp.v def_ic.txt DEFCMD(SWAP CONST(RW) R) DEFCMD(SWAP.GLOBAL EXTRA_BITS MSTR_BITS)
PREFIX_ic_resp
PREFIX_ic_rresp (
.clk(clk),
.reset(reset),
.MMX_AGROUP_IC_AXI_CMD(MMX_ARGROUP_IC_AXI_CMD),
.MMX_GROUP_IC_AXI_R(MMX_RGROUP_IC_AXI_R),
.MMX_AID(MMX_ARID_FULL),
.MMX_ID(MMX_RID_FULL),
.MMX_AGROUP_IC_AXI_CMD.SON(CHANGE!=1)(MMX_ARGROUP_IC_AXI_CMD),
.MMX_GROUP_IC_AXI_R.SON(CHANGE!=1)(MMX_RGROUP_IC_AXI_R),
.SSX_GROUP_IC_AXI_R(SSX_RGROUP_IC_AXI_R),
STOMP ,
);
 
CREATE ic_wdata.v def_ic.txt
CREATE ic_wdata.v def_ic.txt DEFCMD(SWAP.GLOBAL EXTRA_BITS MSTR_BITS)
PREFIX_ic_wdata
PREFIX_ic_wdata (
.clk(clk),
.reset(reset),
.MMX_AWGROUP_IC_AXI_CMD(MMX_AWGROUP_IC_AXI_CMD),
.MMX_WGROUP_IC_AXI_W(MMX_WGROUP_IC_AXI_W),
.MMX_AWID(MMX_AWID_FULL),
.MMX_WID(MMX_WID_FULL),
.MMX_AWGROUP_IC_AXI_CMD.SON(CHANGE!=1)(MMX_AWGROUP_IC_AXI_CMD),
.MMX_WGROUP_IC_AXI_W.SON(CHANGE!=1)(MMX_WGROUP_IC_AXI_W),
.SSX_WGROUP_IC_AXI_W(SSX_WGROUP_IC_AXI_W),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
110,13 → 147,15
);
 
CREATE ic_resp.v def_ic.txt DEFCMD(SWAP CONST(RW) W)
CREATE ic_resp.v def_ic.txt DEFCMD(SWAP CONST(RW) W) DEFCMD(SWAP.GLOBAL EXTRA_BITS MSTR_BITS)
PREFIX_ic_resp
PREFIX_ic_bresp (
.clk(clk),
.reset(reset),
.MMX_AGROUP_IC_AXI_CMD(MMX_AWGROUP_IC_AXI_CMD),
.MMX_GROUP_IC_AXI_B(MMX_BGROUP_IC_AXI_B),
.MMX_AID(MMX_AWID_FULL),
.MMX_ID(MMX_BID_FULL),
.MMX_AGROUP_IC_AXI_CMD.SON(CHANGE!=1)(MMX_AWGROUP_IC_AXI_CMD),
.MMX_GROUP_IC_AXI_B.SON(CHANGE!=1)(MMX_BGROUP_IC_AXI_B),
.MMX_DATA(),
.MMX_LAST(),
.SSX_GROUP_IC_AXI_B(SSX_BGROUP_IC_AXI_B),
129,7 → 168,7
IFDEF DEF_DECERR_SLV
wire SSERR_GROUP_IC_AXI;
CREATE ic_decerr.v def_ic.txt
CREATE ic_decerr.v def_ic.txt DEFCMD(SWAP.GLOBAL EXTRA_BITS MSTR_BITS)
PREFIX_ic_decerr
PREFIX_ic_decerr (
.clk(clk),
/src/base/ic_registry_wr.v
83,9 → 83,9
assign AWmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AWID == ID_BITS'GROUP_MMX_ID;
assign AWmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_AWID == ID_BITS'bADD_IDGROUP_MMX_ID;
assign Wmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_WID == ID_BITS'GROUP_MMX_ID;
assign Wmatch_MMX_IDGROUP_MMX_ID.IDX = MMX_WID == ID_BITS'bADD_IDGROUP_MMX_ID;
assign cmd_push_MMX = MMX_AWVALID & MMX_AWREADY;
103,8 → 103,8
LOOP MX
always @(*)
begin
case (MMX_WID)
ID_BITS'GROUP_MMX_ID : MMX_WSLV = slave_out_MMX_IDGROUP_MMX_ID.IDX;
case (MMX_WID)
ID_BITS'bADD_IDGROUP_MMX_ID : MMX_WSLV = slave_out_MMX_IDGROUP_MMX_ID.IDX;
default : MMX_WSLV = SERR;
endcase
end
/src/base/axi_master.v
160,7 → 160,7
CREATE axi_master_single.v
 
LOOP IDX ID_NUM
PREFIX_single #(IDX, ID_BITS'GROUP_AXI_ID[IDX], CMD_DEPTH)
PREFIX_single #(IDX, ID_BITS'bGROUP_AXI_ID[IDX], CMD_DEPTH)
PREFIX_singleIDX(
.clk(clk),
.reset(reset),
186,6 → 186,7
DEFCMD(SWAP.GLOBAL CONST(CMD_DEPTH) CMD_DEPTH) \\
DEFCMD(SWAP.GLOBAL CONST(DATA_BITS) DATA_BITS) \\
DEFCMD(SWAP.GLOBAL CONST(ADDR_BITS) ADDR_BITS) \\
DEFCMD(DEFINE.GLOBAL UNIQUE_ID) \\
DEFCMD(SWAP.GLOBAL CONST(USER_BITS) 0)
LOOP IDX ID_NUM
STOMP NEWLINE
/src/base/ic_dec.v
61,8 → 61,8
 
always @(MMX_AID)
begin
case (MMX_AID)
ID_BITS'GROUP_MMX_ID : MMX_AIDOK = 1'b1;
case (MMX_AID[MSTR_ID_BITS-1:0])
MSTR_ID_BITS'bGROUP_MMX_ID : MMX_AIDOK = 1'b1;
default : MMX_AIDOK = 1'b0;
endcase
end

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