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URL https://opencores.org/ocsvn/axi_slave/axi_slave/trunk

Subversion Repositories axi_slave

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    /axi_slave/trunk/src/base
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Rev 2 → Rev 4

/axi_slave.v
26,57 → 26,58
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX.v
 
INCLUDE def_axi_slave.txt
module PREFIX(PORTS);
parameter SLAVE_NUM = 0;
input clk;
input reset;
revport GROUP_STUB_AXI;
 
 
wire GROUP_STUB_MEM;
 
CREATE axi_slave_ram.v
PREFIX_ram PREFIX_ram(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
CREATE axi_slave_mem.v
PREFIX_mem PREFIX_mem(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
 
 
IFDEF TRACE
CREATE axi_slave_trace.v #(SLAVE_NUM)
PREFIX_trace PREFIX_trace(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
ENDIF TRACE
endmodule
 
 
 
OUTFILE PREFIX.v
 
INCLUDE def_axi_slave.txt
module PREFIX(PORTS);
parameter SLAVE_NUM = 0;
input clk;
input reset;
revport GROUP_STUB_AXI;
 
 
wire GROUP_STUB_MEM;
 
CREATE axi_slave_ram.v
PREFIX_ram PREFIX_ram(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
CREATE axi_slave_mem.v
PREFIX_mem PREFIX_mem(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
 
 
IFDEF TRACE
CREATE axi_slave_trace.v
PREFIX_trace #(SLAVE_NUM)
PREFIX_trace(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
ENDIF TRACE
endmodule
 
 

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