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  • This comparison shows the changes necessary to convert path 
    /bluetooth/tags/INIT/code/cores/HEC
    from Rev 3 to Rev 4
    ↔ Reverse comparison
  •

Rev 3 → Rev 4

/generator/tb/PCK_CRC8_D8.vhd
0,0 → 1,83
-----------------------------------------------------------------------
-- File: PCK_CRC8_D8.vhd
-- Date: Sun Dec 31 07:41:19 2000
--
-- Copyright (C) 1999 Easics NV.
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose: VHDL package containing a synthesizable CRC function
-- * polynomial: (0 1 2 5 7 8)
-- * data width: 8
--
-- Info: jand@easics.be (Jan Decaluwe)
-- http://www.easics.com
-----------------------------------------------------------------------
 
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package PCK_CRC8_D8 is
 
-- polynomial: (0 1 2 5 7 8)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC8_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(7 downto 0) )
return std_logic_vector;
 
end PCK_CRC8_D8;
 
library IEEE;
use IEEE.std_logic_1164.all;
 
package body PCK_CRC8_D8 is
 
-- polynomial: (0 1 2 5 7 8)
-- data width: 8
-- convention: the first serial data bit is D(7)
function nextCRC8_D8
( Data: std_logic_vector(7 downto 0);
CRC: std_logic_vector(7 downto 0) )
return std_logic_vector is
 
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(7 downto 0);
variable NewCRC: std_logic_vector(7 downto 0);
 
begin
 
D := Data;
C := CRC;
 
NewCRC(0) := D(6) xor D(4) xor D(2) xor D(1) xor D(0) xor C(0) xor
C(1) xor C(2) xor C(4) xor C(6);
NewCRC(1) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(0) xor
C(0) xor C(3) xor C(4) xor C(5) xor C(6) xor C(7);
NewCRC(2) := D(7) xor D(5) xor D(2) xor D(0) xor C(0) xor C(2) xor
C(5) xor C(7);
NewCRC(3) := D(6) xor D(3) xor D(1) xor C(1) xor C(3) xor C(6);
NewCRC(4) := D(7) xor D(4) xor D(2) xor C(2) xor C(4) xor C(7);
NewCRC(5) := D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor D(1) xor
D(0) xor C(0) xor C(1) xor C(2) xor C(3) xor C(4) xor
C(5) xor C(6);
NewCRC(6) := D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor D(2) xor
D(1) xor C(1) xor C(2) xor C(3) xor C(4) xor C(5) xor
C(6) xor C(7);
NewCRC(7) := D(7) xor D(5) xor D(3) xor D(1) xor D(0) xor C(0) xor
C(1) xor C(3) xor C(5) xor C(7);
 
return NewCRC;
 
end nextCRC8_D8;
 
end PCK_CRC8_D8;
 
/generator/tb/hec_gen.vhd
0,0 → 1,109
-------------------------------------------------------------------------------
-- Title : HEC generator
-- Project : Bluetooth baseband core
-------------------------------------------------------------------------------
-- File : hec_gen.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update : 2000/12/28
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: HEC generator core
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 28 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
use work.PCK_CRC8_D8.all;
 
entity HECgen_ent is
 
port (
clk : in std_logic; -- system clock
rst : in std_logic; -- system reset
header : in std_logic_vector(9 downto 0); -- header data
hec : out std_logic_vector(7 downto 0); -- HEC 8 bit value
init : in std_logic_vector(7 downto 0); -- init value
load : in std_logic); -- load header
 
end HECgen_ent;
 
architecture HECgen_beh of HECgen_ent is
 
signal tsthec : std_logic_vector(7 downto 0);
 
begin -- HECgen_beh
 
tsthec <= nextCRC8_D8(header(9 downto 2), (others=> '1'));
 
 
-- purpose: Generate HEC
-- type : sequential
-- inputs : clk, rst
-- outputs:
generate_proc : process (clk, rst)
 
variable lfsr : std_logic_vector(7 downto 0); -- LFSR (HEC register)
variable feedback_var : std_logic; -- feed back variable
 
begin -- process generate_proc
if rst = '0' then -- asynchronous reset (active low)
 
lfsr := (others => '0');
HEC <= (others => '0');
 
elsif clk'event and clk = '1' then -- rising clock edge
 
if load = '1' then
 
lfsr := init;
 
else
 
for i in 9 downto 0 loop
 
feedback_var := header(i) xor lfsr(7);
 
lfsr(7) := feedback_var xor lfsr(6);
lfsr(6) := lfsr(5);
lfsr(5) := feedback_var xor lfsr(4);
lfsr(4) := lfsr(3);
lfsr(3) := lfsr(2);
lfsr(2) := feedback_var xor lfsr(1);
lfsr(1) := feedback_var xor lfsr(0);
lfsr(0) := feedback_var;
 
end loop; -- i
 
 
end if;
 
HEC <= lfsr;
 
end if;
 
end process generate_proc;
 
end HECgen_beh;
/generator/core/HEC_gen.vhd
0,0 → 1,104
-------------------------------------------------------------------------------
-- Title : HEC generator
-- Project : Bluetooth baseband core
-------------------------------------------------------------------------------
-- File : hec_gen.vhd
-- Author : Jamil Khatib (khatib@ieee.org)
-- Organization: OpenIPCore Project
-- Created : 2000/12/28
-- Last update : 2000/12/28
-- Platform :
-- Simulators : Modelsim 5.3XE/Windows98
-- Synthesizers: Leonardo/WindowsNT
-- Target :
-- Dependency : ieee.std_logic_1164
-------------------------------------------------------------------------------
-- Description: HEC generator core
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml
 
-------------------------------------------------------------------------------
-- Revisions :
-- Revision Number : 1
-- Version : 0.1
-- Date : 28 Dec 2000
-- Modifier : Jamil Khatib (khatib@ieee.org)
-- Desccription : Created
-- Known bugs :
-- To Optimze :
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
 
entity HECgen_ent is
 
port (
clk : in std_logic; -- system clock
rst : in std_logic; -- system reset
header : in std_logic_vector(9 downto 0); -- header data
hec : out std_logic_vector(7 downto 0); -- HEC 8 bit value
init : in std_logic_vector(7 downto 0); -- init value
load : in std_logic); -- load header
 
end HECgen_ent;
 
architecture HECgen_beh of HECgen_ent is
 
begin -- HECgen_beh
 
 
 
-- purpose: Generate HEC
-- type : sequential
-- inputs : clk, rst
-- outputs:
generate_proc : process (clk, rst)
 
variable lfsr : std_logic_vector(7 downto 0); -- LFSR (HEC register)
variable feedback_var : std_logic; -- feed back variable
 
begin -- process generate_proc
if rst = '0' then -- asynchronous reset (active low)
 
lfsr := (others => '0');
HEC <= (others => '0');
 
elsif clk'event and clk = '1' then -- rising clock edge
 
if load = '1' then
 
lfsr := init;
 
else
 
for i in 9 downto 0 loop
 
feedback_var := header(i) xor lfsr(7);
 
lfsr(7) := feedback_var xor lfsr(6);
lfsr(6) := lfsr(5);
lfsr(5) := feedback_var xor lfsr(4);
lfsr(4) := lfsr(3);
lfsr(3) := lfsr(2);
lfsr(2) := feedback_var xor lfsr(1);
lfsr(1) := feedback_var xor lfsr(0);
lfsr(0) := feedback_var;
 
end loop; -- i
 
 
end if;
 
HEC <= lfsr;
 
end if;
 
end process generate_proc;
 
end HECgen_beh;

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