URL
https://opencores.org/ocsvn/btc_dsha256/btc_dsha256/trunk
Subversion Repositories btc_dsha256
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- This comparison shows the changes necessary to convert path
/btc_dsha256
- from Rev 4 to Rev 5
- ↔ Reverse comparison
Rev 4 → Rev 5
/trunk/rtl/vhdl/TestBench/btc_dsha_TB.vhd
117,8 → 117,8
signal ovDigest : tDwordArray(0 to 7) := (others=>(others=>'0')); |
|
-- Add your code here ... |
constant cREG_CLK_PERIOD : time := 30 ns; -- 33M Register Clock |
constant cPROC_CLK_PERIOD : time := 10 ns; -- 100M Processing Clock |
constant cREG_CLK_PERIOD : time := 10 ns; -- 100M Register Clock |
constant cPROC_CLK_PERIOD : time := 5 ns; -- 200M Processing Clock |
constant cRESET_INTERVAL : time := 71 ns; |
constant cSTRAT_TEST : integer := 25; |
|
210,7 → 210,7
svWriteCnt <= svWriteCnt + '1'; |
end if; |
|
if svWriteCnt(3 downto 0) = X"F" and svWriteCnt(15 downto 4) <= conv_std_logic_vector(13, 12) then |
if svWriteCnt(1 downto 0) = "11" and svWriteCnt(13 downto 2) <= conv_std_logic_vector(13, 12) then |
iValid_p <= '1'; |
else |
iValid_p <= '0'; |
224,8 → 224,8
ivAddr <= (others=>'0'); |
ivData <= (others=>'0'); |
elsif rising_edge(iClkReg) then |
if svWriteCnt(3 downto 0) = X"F" then |
case svWriteCnt(15 downto 4) is |
if svWriteCnt(1 downto 0) = "11" then |
case svWriteCnt(13 downto 2) is |
when X"000" => |
ivAddr <= X"0"; |
ivData <= svMidState(0); |
272,11 → 272,11
|
when X"00B" => |
ivAddr <= X"B"; |
ivData <= svWork(19) - X"20"; |
ivData <= svWork(19) - X"02"; |
|
when X"00C" => |
ivAddr <= X"C"; |
ivData <= svWork(19) + X"20"; |
ivData <= svWork(19) + X"02"; |
|
when X"00D" => |
ivAddr <= cCMD_ADDR; |
/trunk/rtl/vhdl/sha256core/btc_dsha.vhd
47,8 → 47,8
ivAddr : in std_logic_vector(3 downto 0) := (others=>'0'); |
ivData : in std_logic_vector(31 downto 0) := (others=>'0'); |
|
oReachEnd : out std_logic := '0'; |
oFoundNonce : out std_logic := '0'; |
oReachEnd_p : out std_logic := '0'; |
oFoundNonce_p : out std_logic := '0'; |
ovNonce : out std_logic_vector(31 downto 0) := (others=>'0'); |
ovDigest : out tDwordArray(0 to 7) := (others=>(others=>'0')) |
); |
134,6 → 134,7
end component; |
|
constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D"; |
constant cCMD_NOP : std_logic_vector(15 downto 0) := X"0000"; |
constant cCMD_START : std_logic_vector(15 downto 0) := X"0001"; |
|
constant cPROCESS_DEALY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1, 16); |
837,12 → 838,12
begin |
if rising_edge(iClkProcess) then |
if sCmdStart_syncProcess_p = '1' then |
oReachEnd <= '0'; |
oReachEnd_p <= '0'; |
else |
if sProcess = stSearch and sReachEndToIdle = '1' and sFoundNonceToIdle = '0' then |
oReachEnd <= '1'; |
oReachEnd_p <= '1'; |
else |
oReachEnd <= '0'; |
oReachEnd_p <= '0'; |
end if; |
end if; |
end if; |
867,12 → 868,12
begin |
if rising_edge(iClkProcess) then |
if sCmdStart_syncProcess_p = '1' then |
oFoundNonce <= '0'; |
oFoundNonce_p <= '0'; |
else |
if sProcess = stSearch and sFoundNonceToIdle = '1' then |
oFoundNonce <= '1'; |
oFoundNonce_p <= '1'; |
else |
oFoundNonce <= '0'; |
oFoundNonce_p <= '0'; |
end if; |
end if; |
end if; |
/trunk/doc/btc_dsha256.pdf
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