URL
https://opencores.org/ocsvn/bu_pacman/bu_pacman/trunk
Subversion Repositories bu_pacman
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- This comparison shows the changes necessary to convert path
/bu_pacman/tags/arelease/Sources
- from Rev 4 to Rev 6
- ↔ Reverse comparison
Rev 4 → Rev 6
/ps2/ps2_receive.v
0,0 → 1,68
////////////////////////////////////////////////////////////////////////////////// |
// Company: BU PACMAN TEAM |
// Engineer: Huaxin Dai |
// |
// Create Date: 21:02:09 11/14/2008 |
// Design Name: PS/2 Interface |
// Module Name: ps2_rcv |
// Project Name: BU PACMAN |
// Target Devices: Spartan3 XC3S1000 |
// Tool versions: ISE 10.1 |
// Description: PS/2 interface, data receiving part. |
// |
// Dependencies: Nothing |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: Currently the parity check and start/stop bit detection |
// hasn't been done, will do it in later version. |
////////////////////////////////////////////////////////////////////////////////// |
module ps2_receive( |
input in_clk, |
input in_reset, |
input in_ps2_clk, |
input in_ps2_data, |
output reg [7:0] out_data |
); |
|
reg [3:0] i;//Counter |
reg [10:0] data_in;//keycode register, including start bit, keycode, parity bit and stop bit |
reg flag_break; |
reg [2:0] ps2_clkr;//a fifo to detect ps2 clk |
|
wire ps2_clk_fallingedge = (ps2_clkr[2:1]==2'b10); //re-generate the falling edge |
|
always @(posedge in_clk) |
ps2_clkr <= {ps2_clkr[1:0], in_ps2_clk}; //Buffer the incoming PS/2 clock |
|
always @(posedge in_clk) |
if(in_reset) //Reset |
begin |
i <= 0; |
data_in <= 0; |
out_data <= 8'h00; |
end |
else |
if(ps2_clk_fallingedge) //Incoming clock falling edge, read data |
begin |
data_in[i] <= in_ps2_data; |
if(i<10) //If it's still in the middle of some word |
i <= i+1; |
else //Word processing |
begin |
i <= 0; |
if(data_in[8:1]==8'hF0) //If it's the break code |
begin |
out_data <= 8'h00; //Output an Idle |
flag_break <= 1; //Set the break flag |
end |
else if(flag_break == 1) //If the break flag is on, which means this is a keycode for break action |
begin |
out_data <= 8'h00; //Output an Idle |
flag_break <= 0; //Clear the break flag |
end |
else //If it's a make code |
out_data <= data_in[8:1]; //Output the keycode |
end |
end |
endmodule |
/ps2/ps2_top.v
0,0 → 1,41
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: BU PACMAN TEAM |
// Engineer: Huaxin Dai |
// |
// Create Date: 21:07:03 11/14/2008 |
// Design Name: PS/2 Interface |
// Module Name: ps2_top |
// Project Name: BU PACMAN |
// Target Devices: XC3S1000 |
// Tool versions: ISE 10.1 |
// Description: PS/2 interface, top module. |
// |
// Dependencies: ps2_receive.v, ps2_decode.v |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module ps2_top( |
input in_reset, |
input in_clk_main, |
input in_clk_ps2, |
input in_data_ps2, |
output [6:0]out_key |
); |
wire [7:0]wire_data; |
ps2_receive ps2_rcv ( .in_clk(in_clk_main), |
.in_reset(in_reset), |
.in_ps2_clk(in_clk_ps2), |
.in_ps2_data(in_data_ps2), |
.out_data(wire_data) |
); |
|
ps2_decode ps2_dec ( .in_clk(in_clk_main), |
.in_reset(in_reset), |
.in_data(wire_data), |
.out_data(out_key) |
); |
endmodule |
/ps2/ps2_decode.v
0,0 → 1,59
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Company: BU PACMAN TEAM |
// Engineer: Huaxin Dai |
// |
// Create Date: 21:02:09 11/14/2008 |
// Design Name: PS/2 Interface |
// Module Name: ps2_decode |
// Project Name: BU PACMAN |
// Target Devices: XC3S1000 |
// Tool versions: ISE 10.1 |
// Description: PS/2 interface, key decode part. |
// |
// Dependencies: ps2_receive.v |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module ps2_decode( |
input in_clk, |
input in_reset, |
input [7:0]in_data, |
output reg [6:0]out_data |
); |
always @(posedge in_clk) |
if(in_reset) |
begin |
out_data <= 7'b0000001; |
end |
else |
begin |
case(in_data) |
8'h1C:begin//left, A |
out_data <= 7'b0010000; |
end |
8'h1B:begin//down, S |
out_data <= 7'b0100000; |
end |
8'h23:begin//right, D |
out_data <= 7'b0001000; |
end |
8'h1D:begin//up, W |
out_data <= 7'b1000000; |
end |
8'h2D:begin//reset, R |
out_data <= 7'b0000100; |
end |
8'h4D:begin//pause, P |
out_data <= 7'b0000010; |
end |
default: begin//stop |
out_data <= 7'b0000001; |
end |
endcase |
end |
|
endmodule |