URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
Subversion Repositories bustap-jtag
Compare Revisions
- This comparison shows the changes necessary to convert path
/bustap-jtag/trunk/par/xilinx
- from Rev 18 to Rev 20
- ↔ Reverse comparison
Rev 18 → Rev 20
/xps/cleanup.sh
0,0 → 1,3
rm -f -r etc hdl synthesis implementation pcores simulation __xps |
rm -f *.log *.opt *.cmd *.make *.bxml *.bmm *.v |
|
/xps/zynq_bram.xmp
0,0 → 1,31
#Please do not modify this file by hand |
XmpVersion: 14.3 |
VerMgmt: 14.3 |
IntStyle: default |
Flow: ise |
ModuleSearchPath: ../../../rtl/xilinx/pcores/bustap_jtag_v1_00_a/../../../ |
MHS File: zynq_bram.mhs |
Architecture: zynq |
Device: xc7z020 |
Package: clg484 |
SpeedGrade: -1 |
UserCmd1: |
UserCmd1Type: 0 |
UserCmd2: |
UserCmd2Type: 0 |
GenSimTB: 0 |
SdkExportBmmBit: 0 |
SdkExportDir: SDK/SDK_Export |
InsertNoPads: 0 |
WarnForEAArch: 1 |
HdlLang: VERILOG |
SimModel: BEHAVIORAL |
ExternalMemSim: 0 |
UcfFile: data/zynq_bram.ucf |
EnableParTimingError: 1 |
ShowLicenseDialog: 1 |
BInfo: |
LockAddr: PL_bram_ctrl,C_S_AXI_BASEADDR |
Processor: PS |
ElfImp: |
ElfSim: |
/xps/zynq_bram.mhs
0,0 → 1,189
|
PARAMETER VERSION = 2.1.0 |
|
|
PORT PS_SRSTB = PS_SRSTB, DIR = I |
PORT PS_CLK = PS_CLK, DIR = I, SIGIS = CLK |
PORT PS_PORB = PS_PORB, DIR = I |
PORT PS_DDR_Clk = PS_DDR_Clk, DIR = IO, SIGIS = CLK |
PORT PS_DDR_Clk_n = PS_DDR_Clk_n, DIR = IO, SIGIS = CLK |
PORT PS_DDR_CKE = PS_DDR_CKE, DIR = IO |
PORT PS_DDR_CS_n = PS_DDR_CS_n, DIR = IO |
PORT PS_DDR_RAS_n = PS_DDR_RAS_n, DIR = IO |
PORT PS_DDR_CAS_n = PS_DDR_CAS_n, DIR = IO |
PORT PS_DDR_WEB = PS_DDR_WEB, DIR = O |
PORT PS_DDR_BankAddr = PS_DDR_BankAddr, DIR = IO, VEC = [2:0] |
PORT PS_DDR_Addr = PS_DDR_Addr, DIR = IO, VEC = [14:0] |
PORT PS_DDR_ODT = PS_DDR_ODT, DIR = IO |
PORT PS_DDR_DRSTB = PS_DDR_DRSTB, DIR = IO, SIGIS = RST |
PORT PS_DDR_DQ = PS_DDR_DQ, DIR = IO, VEC = [31:0] |
PORT PS_DDR_DM = PS_DDR_DM, DIR = IO, VEC = [3:0] |
PORT PS_DDR_DQS = PS_DDR_DQS, DIR = IO, VEC = [3:0] |
PORT PS_DDR_DQS_n = PS_DDR_DQS_n, DIR = IO, VEC = [3:0] |
PORT PS_DDR_VRN = PS_DDR_VRN, DIR = IO |
PORT PS_DDR_VRP = PS_DDR_VRP, DIR = IO |
PORT PS_MIO = PS_MIO, DIR = IO, VEC = [53:0] |
|
|
BEGIN processing_system7 |
PARAMETER INSTANCE = PS |
PARAMETER HW_VER = 4.02.a |
PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF |
PARAMETER C_EN_EMIO_CAN0 = 0 |
PARAMETER C_EN_EMIO_CAN1 = 0 |
PARAMETER C_EN_EMIO_ENET0 = 0 |
PARAMETER C_EN_EMIO_ENET1 = 0 |
PARAMETER C_EN_EMIO_I2C0 = 0 |
PARAMETER C_EN_EMIO_I2C1 = 0 |
PARAMETER C_EN_EMIO_PJTAG = 0 |
PARAMETER C_EN_EMIO_SDIO0 = 0 |
PARAMETER C_EN_EMIO_CD_SDIO0 = 0 |
PARAMETER C_EN_EMIO_WP_SDIO0 = 0 |
PARAMETER C_EN_EMIO_SDIO1 = 0 |
PARAMETER C_EN_EMIO_CD_SDIO1 = 0 |
PARAMETER C_EN_EMIO_WP_SDIO1 = 0 |
PARAMETER C_EN_EMIO_SPI0 = 0 |
PARAMETER C_EN_EMIO_SPI1 = 0 |
PARAMETER C_EN_EMIO_SRAM_INT = 0 |
PARAMETER C_EN_EMIO_TRACE = 0 |
PARAMETER C_EN_EMIO_TTC0 = 1 |
PARAMETER C_EN_EMIO_TTC1 = 0 |
PARAMETER C_EN_EMIO_UART0 = 0 |
PARAMETER C_EN_EMIO_UART1 = 0 |
PARAMETER C_EN_EMIO_MODEM_UART0 = 0 |
PARAMETER C_EN_EMIO_MODEM_UART1 = 0 |
PARAMETER C_EN_EMIO_WDT = 1 |
PARAMETER C_EN_QSPI = 1 |
PARAMETER C_EN_SMC = 0 |
PARAMETER C_EN_CAN0 = 1 |
PARAMETER C_EN_CAN1 = 0 |
PARAMETER C_EN_ENET0 = 1 |
PARAMETER C_EN_ENET1 = 0 |
PARAMETER C_EN_I2C0 = 1 |
PARAMETER C_EN_I2C1 = 0 |
PARAMETER C_EN_PJTAG = 0 |
PARAMETER C_EN_SDIO0 = 1 |
PARAMETER C_EN_SDIO1 = 0 |
PARAMETER C_EN_SPI0 = 0 |
PARAMETER C_EN_SPI1 = 0 |
PARAMETER C_EN_TRACE = 0 |
PARAMETER C_EN_TTC0 = 1 |
PARAMETER C_EN_TTC1 = 0 |
PARAMETER C_EN_UART0 = 0 |
PARAMETER C_EN_UART1 = 1 |
PARAMETER C_EN_MODEM_UART0 = 0 |
PARAMETER C_EN_MODEM_UART1 = 0 |
PARAMETER C_EN_USB0 = 1 |
PARAMETER C_EN_USB1 = 0 |
PARAMETER C_EN_WDT = 1 |
PARAMETER C_EN_DDR = 1 |
PARAMETER C_EN_GPIO = 1 |
PARAMETER C_FCLK_CLK0_FREQ = 100000000 |
PARAMETER C_FCLK_CLK1_FREQ = 50000000 |
PARAMETER C_FCLK_CLK2_FREQ = 50000000 |
PARAMETER C_FCLK_CLK3_FREQ = 50000000 |
PARAMETER C_USE_M_AXI_GP0 = 1 |
PARAMETER C_USE_M_AXI_GP1 = 1 |
PARAMETER C_USE_CR_FABRIC = 1 |
PARAMETER C_NUM_F2P_INTR_INPUTS = 7 |
PARAMETER C_USE_S_AXI_GP0 = 0 |
PARAMETER C_USE_S_AXI_GP1 = 0 |
PARAMETER C_USE_S_AXI_HP0 = 1 |
PARAMETER C_USE_S_AXI_HP1 = 1 |
PARAMETER C_USE_S_AXI_HP2 = 1 |
PARAMETER C_USE_S_AXI_HP3 = 1 |
PARAMETER C_S_AXI_HP0_BASEADDR = 0x00000000 |
PARAMETER C_S_AXI_HP0_HIGHADDR = 0x3FFFFFFF |
PARAMETER C_EMIO_GPIO_WIDTH = 64 |
PARAMETER C_EN_EMIO_GPIO = 0 |
BUS_INTERFACE M_AXI_GP0 = AXI_PS_PL |
PORT PS_SRSTB = PS_SRSTB |
PORT PS_CLK = PS_CLK |
PORT PS_PORB = PS_PORB |
PORT FCLK_CLK0 = PS_FCLK_CLK0 |
PORT DDR_Clk = PS_DDR_Clk |
PORT DDR_Clk_n = PS_DDR_Clk_n |
PORT DDR_CKE = PS_DDR_CKE |
PORT DDR_CS_n = PS_DDR_CS_n |
PORT DDR_RAS_n = PS_DDR_RAS_n |
PORT DDR_CAS_n = PS_DDR_CAS_n |
PORT DDR_WEB = PS_DDR_WEB |
PORT DDR_BankAddr = PS_DDR_BankAddr |
PORT DDR_Addr = PS_DDR_Addr |
PORT DDR_ODT = PS_DDR_ODT |
PORT DDR_DRSTB = PS_DDR_DRSTB |
PORT DDR_DQ = PS_DDR_DQ |
PORT DDR_DM = PS_DDR_DM |
PORT DDR_DQS = PS_DDR_DQS |
PORT DDR_DQS_n = PS_DDR_DQS_n |
PORT DDR_VRN = PS_DDR_VRN |
PORT DDR_VRP = PS_DDR_VRP |
PORT MIO = PS_MIO |
PORT M_AXI_GP1_ACLK = clock_generator_0_CLKOUT0 |
PORT M_AXI_GP0_ARESETN = PS_M_AXI_GP0_ARESETN |
PORT M_AXI_GP0_ACLK = clock_generator_0_CLKOUT0 |
PORT S_AXI_HP0_ACLK = clock_generator_0_CLKOUT0 |
PORT S_AXI_HP1_ACLK = clock_generator_0_CLKOUT0 |
PORT S_AXI_HP2_ACLK = clock_generator_0_CLKOUT0 |
PORT S_AXI_HP3_ACLK = clock_generator_0_CLKOUT0 |
PORT FCLK_RESET0_N = PS_FCLK_RESET0_N |
END |
|
BEGIN bram_block |
PARAMETER INSTANCE = PL_bram_block |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE PORTA = axi_bram_ctrl_1_BRAM_PORTA |
BUS_INTERFACE PORTB = axi_bram_ctrl_1_BRAM_PORTB |
END |
|
BEGIN axi_bram_ctrl |
PARAMETER INSTANCE = PL_bram_ctrl |
PARAMETER HW_VER = 1.03.a |
PARAMETER C_S_AXI_BASEADDR = 0x40000000 |
PARAMETER C_S_AXI_HIGHADDR = 0x40000FFF |
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = PS.M_AXI_GP0 |
BUS_INTERFACE S_AXI = AXI_PS_PL |
BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_1_BRAM_PORTA |
BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_1_BRAM_PORTB |
PORT S_AXI_ACLK = clock_generator_0_CLKOUT0 |
END |
|
BEGIN axi_interconnect |
PARAMETER INSTANCE = AXI_PS_PL |
PARAMETER HW_VER = 1.06.a |
PORT INTERCONNECT_ACLK = clock_generator_0_CLKOUT0 |
PORT INTERCONNECT_ARESETN = PS_M_AXI_GP0_ARESETN |
END |
|
BEGIN clock_generator |
PARAMETER INSTANCE = clock_generator_0 |
PARAMETER HW_VER = 4.03.a |
PARAMETER C_CLKIN_FREQ = 100000000 |
PARAMETER C_CLKOUT0_FREQ = 75000000 |
PARAMETER C_EXT_RESET_HIGH = 0 |
PARAMETER C_CLKOUT1_FREQ = 50000000 |
PARAMETER C_CLKOUT2_FREQ = 0 |
PORT CLKIN = PS_FCLK_CLK0 |
PORT RST = PS_FCLK_RESET0_N |
PORT CLKOUT0 = clock_generator_0_CLKOUT0 |
END |
|
BEGIN bustap_jtag |
PARAMETER INSTANCE = bustap_jtag_0 |
PARAMETER HW_VER = 1.00.a |
BUS_INTERFACE MON_AXI = PS.M_AXI_GP0 |
PORT ACLK = clock_generator_0_CLKOUT0 |
PORT CHIPSCOPE_ICON_CONTROL0 = chipscope_icon_0_control0 |
PORT CHIPSCOPE_ICON_CONTROL1 = chipscope_icon_0_control1 |
PORT CHIPSCOPE_ICON_CONTROL2 = chipscope_icon_0_control2 |
END |
|
BEGIN chipscope_icon |
PARAMETER INSTANCE = chipscope_icon_0 |
PARAMETER HW_VER = 1.06.a |
PARAMETER C_NUM_CONTROL_PORTS = 3 |
PORT control0 = chipscope_icon_0_control0 |
PORT control1 = chipscope_icon_0_control1 |
PORT control2 = chipscope_icon_0_control2 |
END |
|
/xps/data/ps7_zynq_bram_prj.xml
0,0 → 1,172
<?xml version="1.0" encoding="UTF-8" ?> |
<!DOCTYPE project PUBLIC "project" "project.dtd" > |
<project version="1.0" > |
<set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::UIPARAM::DDR::MEMORY_TYPE" value="DDR 3" /> |
<set param="PCW::I2C0::I2C0::IO" value="MIO 50 .. 51" /> |
<set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::I2C0::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::PRESET::GLOBAL::DEFAULT" value="powerup" /> |
<set param="PCW::CAN0::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::CAN0::CAN0::IO" value="MIO 46 .. 47" /> |
<set param="PCW::SD0::GRP_CD::ENABLE" value="1" /> |
<set param="PCW::SD0::GRP_WP::ENABLE" value="1" /> |
<set param="PCW::SD0::GRP_CD::IO" value="MIO 0" /> |
<set param="PCW::SD0::GRP_WP::IO" value="MIO 15" /> |
<set param="PCW::TTC0::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" /> |
<set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" /> |
<set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" /> |
<set param="PCW::QSPI::GRP_FBCLK::ENABLE" value="1" /> |
<set param="PCW::PRESET::GLOBAL::CONFIG" value="Default" /> |
<set param="PCW::WDT::PERIPHERAL::ENABLE" value="1" /> |
<set param="PCW::PJTAG::PERIPHERAL::ENABLE" value="0" /> |
<set param="PCW::MIO::MIO[3]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[3]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[3]::PULLUP" value="disabled" /> |
<set param="PCW::MIO::MIO[4]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[4]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[4]::PULLUP" value="disabled" /> |
<set param="PCW::MIO::MIO[5]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[5]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[5]::PULLUP" value="disabled" /> |
<set param="PCW::MIO::MIO[6]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[6]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[6]::PULLUP" value="disabled" /> |
<set param="PCW::MIO::MIO[7]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[7]::PULLUP" value="disabled" /> |
<set param="PCW::MIO::MIO[8]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[8]::PULLUP" value="disabled" /> |
<set param="PCW::MIO::MIO[9]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[10]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[11]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[12]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[13]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[14]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[15]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[15]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[16]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[16]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[17]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[17]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[18]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[18]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[19]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[19]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[20]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[20]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[21]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[21]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[22]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[22]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[23]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[23]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW:GPIO::EMIO_GPIO::WIDTH" value="64" /> |
<set param="PCW::GPIO::V2.00.A::C_EN_EMIO_GPIO" value="0" /> |
<set param="PCW::PRESET::FPGA::PARTNUMBER" value="xc7z020clg484-1" /> |
<set param="PCW::PRESET::FPGA::SPEED" value="-1" /> |
<set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 1.8V" /> |
<set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[0]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[0]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[1]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[1]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::UIPARAM::DDR::PARTNO" value="MT41J256M8 HX-15E" /> |
<set param="PCW::UIPARAM::DDR::DRAM_WIDTH" value="8 Bits" /> |
<set param="PCW::UIPARAM::DDR::DEVICE_CAPACITY" value="2048 MBits" /> |
<set param="PCW::UIPARAM::DDR::SPEED_BIN" value="DDR3_1066F" /> |
<set param="PCW::UIPARAM::DDR::FREQ_MHZ" value="533.333313" /> |
<set param="PCW::UIPARAM::DDR::CL" value="7" /> |
<set param="PCW::UIPARAM::DDR::CWL" value="6" /> |
<set param="PCW::UIPARAM::DDR::T_RCD" value="7" /> |
<set param="PCW::UIPARAM::DDR::T_RP" value="7" /> |
<set param="PCW::UIPARAM::DDR::T_RC" value="49.5" /> |
<set param="PCW::UIPARAM::DDR::T_RAS_MIN" value="36.0" /> |
<set param="PCW::UIPARAM::DDR::T_FAW" value="30.0" /> |
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_0" value="0.217" /> |
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_1" value="0.133" /> |
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_2" value="0.089" /> |
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_3" value="0.248" /> |
<set param="PCW::MIO::MIO[2]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[2]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[2]::PULLUP" value="disabled" /> |
<set param="PCW::APU::PERIPHERAL::FREQMHZ" value="533.000000" /> |
<set param="PCW::FPGA0::PERIPHERAL::FREQMHZ" value="100.000000" /> |
<set param="PCW::ENET0::PERIPHERAL::FREQMHZ" value="100 Mbps" /> |
<set param="PCW::SDIO::PERIPHERAL::FREQMHZ" value="50" /> |
<set param="PCW::UART::PERIPHERAL::FREQMHZ" value="50" /> |
<set param="PCW::CAN::PERIPHERAL::FREQMHZ" value="23.8095" /> |
<set param="PCW::UIPARAM::DDR::BL" value="8" /> |
<set param="PCW::MIO::MIO[24]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[24]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[25]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[25]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[26]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[26]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[27]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[27]::IOTYPE" value="HSTL 1.8V" /> |
<set param="PCW::MIO::MIO[28]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[28]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[29]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[29]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[30]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[30]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[31]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[31]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[32]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[32]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[33]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[33]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[34]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[34]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[35]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[35]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[36]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[36]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[37]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[37]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[38]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[38]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[39]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[39]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[40]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[40]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[41]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[41]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[42]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[42]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[43]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[43]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[44]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[44]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[45]::SLEW" value="fast" /> |
<set param="PCW::MIO::MIO[45]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[46]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[47]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[48]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[49]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[50]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[51]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[52]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::MIO::MIO[53]::IOTYPE" value="LVCMOS 1.8V" /> |
<set param="PCW::UIPARAM::DDR::TRAIN_WRITE_LEVEL" value="1" /> |
<set param="PCW::UIPARAM::DDR::TRAIN_READ_GATE" value="1" /> |
<set param="PCW::UIPARAM::DDR::TRAIN_DATA_EYE" value="1" /> |
<set param="PCW::UIPARAM::DDR::USE_INTERNAL_VREF" value="1" /> |
<set param="PCW::UIPARAM::DDR::BOARD_DELAY0" value="0.537" /> |
<set param="PCW::UIPARAM::DDR::BOARD_DELAY1" value="0.442" /> |
<set param="PCW::UIPARAM::DDR::BOARD_DELAY2" value="0.464" /> |
<set param="PCW::UIPARAM::DDR::BOARD_DELAY3" value="0.521" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP0_BASEADDR" value="0x00000000" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP0_HIGHADDR" value="0x3FFFFFFF" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP1_BASEADDR" value="0x00000000" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP1_HIGHADDR" value="0x3FFFFFFF" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP2_BASEADDR" value="0x00000000" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP2_HIGHADDR" value="0x3FFFFFFF" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP3_BASEADDR" value="0x00000000" /> |
<set param="PCW::DDR::V4.00.A::C_S_AXI_HP3_HIGHADDR" value="0x3FFFFFFF" /> |
</project> |
/xps/data/ps7_constraints.ucf
0,0 → 1,151
############################################################################ |
## |
## Xilinx, Inc. 2006 www.xilinx.com |
############################################################################ |
## File name : data/ps7_constraints.ucf |
## |
## Details : Constraints file |
## FPGA family: zynq |
## FPGA: xc7z020clg484-1 |
## Device Size: xc7z020 |
## Package: clg484 |
## Speedgrade: -1 |
## |
##Note: This is a generated file. Configuration settings should not be edited |
## |
############################################################################ |
############################################################################ |
############################################################################ |
# I/O STANDARDS and Location Constraints # |
############################################################################ |
|
NET "MIO[53]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C12" | PULLUP = "TRUE" ; # Enet 0 / mdio / MIO[53] |
NET "MIO[52]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D10" | PULLUP = "TRUE" ; # Enet 0 / mdc / MIO[52] |
NET "MIO[51]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C10" | PULLUP = "TRUE" ; # I2C 0 / sda / MIO[51] |
NET "MIO[50]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D13" | PULLUP = "TRUE" ; # I2C 0 / scl / MIO[50] |
NET "MIO[49]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C14" | PULLUP = "TRUE" ; # UART 1 / rx / MIO[49] |
NET "MIO[48]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D11" | PULLUP = "TRUE" ; # UART 1 / tx / MIO[48] |
NET "MIO[47]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B10" | PULLUP = "TRUE" ; # CAN 0 / tx / MIO[47] |
NET "MIO[46]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D12" | PULLUP = "TRUE" ; # CAN 0 / rx / MIO[46] |
NET "MIO[45]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B9" | PULLUP = "TRUE" ; # SD 0 / data[3] / MIO[45] |
NET "MIO[44]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E13" | PULLUP = "TRUE" ; # SD 0 / data[2] / MIO[44] |
NET "MIO[43]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B11" | PULLUP = "TRUE" ; # SD 0 / data[1] / MIO[43] |
NET "MIO[42]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "D8" | PULLUP = "TRUE" ; # SD 0 / data[0] / MIO[42] |
NET "MIO[41]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C8" | PULLUP = "TRUE" ; # SD 0 / cmd / MIO[41] |
NET "MIO[40]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E14" | PULLUP = "TRUE" ; # SD 0 / clk / MIO[40] |
NET "MIO[39]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C13" | PULLUP = "TRUE" ; # USB 0 / data[7] / MIO[39] |
NET "MIO[38]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F13" | PULLUP = "TRUE" ; # USB 0 / data[6] / MIO[38] |
NET "MIO[37]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B14" | PULLUP = "TRUE" ; # USB 0 / data[5] / MIO[37] |
NET "MIO[36]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A9" | PULLUP = "TRUE" ; # USB 0 / clk / MIO[36] |
NET "MIO[35]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F14" | PULLUP = "TRUE" ; # USB 0 / data[3] / MIO[35] |
NET "MIO[34]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B12" | PULLUP = "TRUE" ; # USB 0 / data[2] / MIO[34] |
NET "MIO[33]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "G13" | PULLUP = "TRUE" ; # USB 0 / data[1] / MIO[33] |
NET "MIO[32]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C7" | PULLUP = "TRUE" ; # USB 0 / data[0] / MIO[32] |
NET "MIO[31]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F9" | PULLUP = "TRUE" ; # USB 0 / nxt / MIO[31] |
NET "MIO[30]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A11" | PULLUP = "TRUE" ; # USB 0 / stp / MIO[30] |
NET "MIO[29]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E8" | PULLUP = "TRUE" ; # USB 0 / dir / MIO[29] |
NET "MIO[28]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A12" | PULLUP = "TRUE" ; # USB 0 / data[4] / MIO[28] |
NET "MIO[27]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D7" | PULLUP = "TRUE" ; # Enet 0 / rx_ctl / MIO[27] |
NET "MIO[26]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A13" | PULLUP = "TRUE" ; # Enet 0 / rxd[3] / MIO[26] |
NET "MIO[25]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F12" | PULLUP = "TRUE" ; # Enet 0 / rxd[2] / MIO[25] |
NET "MIO[24]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "B7" | PULLUP = "TRUE" ; # Enet 0 / rxd[1] / MIO[24] |
NET "MIO[23]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E11" | PULLUP = "TRUE" ; # Enet 0 / rxd[0] / MIO[23] |
NET "MIO[22]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A14" | PULLUP = "TRUE" ; # Enet 0 / rx_clk / MIO[22] |
NET "MIO[21]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F11" | PULLUP = "TRUE" ; # Enet 0 / tx_ctl / MIO[21] |
NET "MIO[20]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A8" | PULLUP = "TRUE" ; # Enet 0 / txd[3] / MIO[20] |
NET "MIO[19]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E10" | PULLUP = "TRUE" ; # Enet 0 / txd[2] / MIO[19] |
NET "MIO[18]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A7" | PULLUP = "TRUE" ; # Enet 0 / txd[1] / MIO[18] |
NET "MIO[17]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E9" | PULLUP = "TRUE" ; # Enet 0 / txd[0] / MIO[17] |
NET "MIO[16]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D6" | PULLUP = "TRUE" ; # Enet 0 / tx_clk / MIO[16] |
NET "MIO[15]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E6" | PULLUP = "TRUE" ; # SD 0 / wp / MIO[15] |
NET "MIO[14]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B6" | PULLUP = "TRUE" ; # GPIO / gpio[14] / MIO[14] |
NET "MIO[13]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "A6" | PULLUP = "TRUE" ; # GPIO / gpio[13] / MIO[13] |
NET "MIO[12]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C5" | PULLUP = "TRUE" ; # GPIO / gpio[12] / MIO[12] |
NET "MIO[11]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B4" | PULLUP = "TRUE" ; # GPIO / gpio[11] / MIO[11] |
NET "MIO[10]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "G7" | PULLUP = "TRUE" ; # GPIO / gpio[10] / MIO[10] |
NET "MIO[9]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C4" | PULLUP = "TRUE" ; # GPIO / gpio[9] / MIO[9] |
NET "MIO[8]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "E5" ; # Quad SPI Flash / qspi_fbclk / MIO[8] |
NET "MIO[7]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D5" ; # GPIO / gpio[7] / MIO[7] |
NET "MIO[6]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A4" ; # Quad SPI Flash / qspi0_sclk / MIO[6] |
NET "MIO[5]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A3" ; # Quad SPI Flash / qspi0_io[3] / MIO[5] |
NET "MIO[4]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E4" ; # Quad SPI Flash / qspi0_io[2] / MIO[4] |
NET "MIO[3]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F6" ; # Quad SPI Flash / qspi0_io[1] / MIO[3] |
NET "MIO[2]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A2" ; # Quad SPI Flash / qspi0_io[0] / MIO[2] |
NET "MIO[1]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A1" | PULLUP = "TRUE" ; # Quad SPI Flash / qspi0_ss_b / MIO[1] |
NET "MIO[0]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "G6" | PULLUP = "TRUE" ; # SD 0 / cd / MIO[0] |
NET "DDR_WEB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "R4" ; |
NET "DDR_VRP" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N7" ; |
NET "DDR_VRN" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M7" ; |
NET "DDR_RAS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "R5" ; |
NET "DDR_ODT" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P5" ; |
NET "DDR_DRSTB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F3" ; |
NET "DDR_DQS[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "V2" ; |
NET "DDR_DQS[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "N2" ; |
NET "DDR_DQS[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "H2" ; |
NET "DDR_DQS[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C2" ; |
NET "DDR_DQS_n[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "W2" ; |
NET "DDR_DQS_n[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "P2" ; |
NET "DDR_DQS_n[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "J2" ; |
NET "DDR_DQS_n[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "D2" ; |
NET "DDR_DQ[9]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G1" ; |
NET "DDR_DQ[8]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G2" ; |
NET "DDR_DQ[7]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F1" ; |
NET "DDR_DQ[6]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F2" ; |
NET "DDR_DQ[5]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E1" ; |
NET "DDR_DQ[4]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E3" ; |
NET "DDR_DQ[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D3" ; |
NET "DDR_DQ[31]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y1" ; |
NET "DDR_DQ[30]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W3" ; |
NET "DDR_DQ[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B2" ; |
NET "DDR_DQ[29]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y3" ; |
NET "DDR_DQ[28]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W1" ; |
NET "DDR_DQ[27]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U2" ; |
NET "DDR_DQ[26]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA1" ; |
NET "DDR_DQ[25]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U1" ; |
NET "DDR_DQ[24]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA3" ; |
NET "DDR_DQ[23]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R1" ; |
NET "DDR_DQ[22]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M2" ; |
NET "DDR_DQ[21]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T2" ; |
NET "DDR_DQ[20]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R3" ; |
NET "DDR_DQ[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C3" ; |
NET "DDR_DQ[19]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T1" ; |
NET "DDR_DQ[18]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N3" ; |
NET "DDR_DQ[17]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T3" ; |
NET "DDR_DQ[16]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M1" ; |
NET "DDR_DQ[15]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K3" ; |
NET "DDR_DQ[14]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J1" ; |
NET "DDR_DQ[13]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K1" ; |
NET "DDR_DQ[12]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L3" ; |
NET "DDR_DQ[11]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L2" ; |
NET "DDR_DQ[10]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L1" ; |
NET "DDR_DQ[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D1" ; |
NET "DDR_DM[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA2" ; |
NET "DDR_DM[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "P1" ; |
NET "DDR_DM[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H3" ; |
NET "DDR_DM[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B1" ; |
NET "DDR_CS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P6" ; |
NET "DDR_CKE" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "V3" ; |
NET "DDR_Clk" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "N4" ; |
NET "DDR_Clk_n" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "N5" ; |
NET "DDR_CAS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P3" ; |
NET "DDR_BankAddr[2]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M6" ; |
NET "DDR_BankAddr[1]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L6" ; |
NET "DDR_BankAddr[0]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L7" ; |
NET "DDR_Addr[9]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H5" ; |
NET "DDR_Addr[8]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J5" ; |
NET "DDR_Addr[7]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J6" ; |
NET "DDR_Addr[6]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J7" ; |
NET "DDR_Addr[5]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K5" ; |
NET "DDR_Addr[4]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K6" ; |
NET "DDR_Addr[3]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L4" ; |
NET "DDR_Addr[2]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K4" ; |
NET "DDR_Addr[1]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M5" ; |
NET "DDR_Addr[14]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G4" ; |
NET "DDR_Addr[13]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F4" ; |
NET "DDR_Addr[12]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H4" ; |
NET "DDR_Addr[11]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G5" ; |
NET "DDR_Addr[10]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J3" ; |
NET "DDR_Addr[0]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M4" ; |
NET "PS_PORB" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B5" ; |
NET "PS_SRSTB" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C9" ; |
NET "PS_CLK" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F7" ; |
/xps/data/ps7_constraints.xdc
0,0 → 1,557
############################################################################ |
## |
## Xilinx, Inc. 2006 www.xilinx.com |
############################################################################ |
## File name : data/ps7_constraints.xdc |
## |
## Details : Constraints file |
## FPGA family: zynq |
## FPGA: xc7z020clg484-1 |
## Device Size: xc7z020 |
## Package: clg484 |
## Speedgrade: -1 |
## |
##Note: This is a generated file. Configuration settings should not be edited |
## |
############################################################################ |
############################################################################ |
############################################################################ |
# I/O STANDARDS and Location Constraints # |
############################################################################ |
|
# Enet 0 / mdio / MIO[53] |
set_property iostandard "LVCMOS18" [get_ports "MIO[53]"] |
set_property PACKAGE_PIN "C12" [get_ports "MIO[53]"] |
set_property slew "slow" [get_ports "MIO[53]"] |
set_property drive "8" [get_ports "MIO[53]"] |
set_property pullup "TRUE" [get_ports "MIO[53]"] |
# Enet 0 / mdc / MIO[52] |
set_property iostandard "LVCMOS18" [get_ports "MIO[52]"] |
set_property PACKAGE_PIN "D10" [get_ports "MIO[52]"] |
set_property slew "slow" [get_ports "MIO[52]"] |
set_property drive "8" [get_ports "MIO[52]"] |
set_property pullup "TRUE" [get_ports "MIO[52]"] |
# I2C 0 / sda / MIO[51] |
set_property iostandard "LVCMOS18" [get_ports "MIO[51]"] |
set_property PACKAGE_PIN "C10" [get_ports "MIO[51]"] |
set_property slew "slow" [get_ports "MIO[51]"] |
set_property drive "8" [get_ports "MIO[51]"] |
set_property pullup "TRUE" [get_ports "MIO[51]"] |
# I2C 0 / scl / MIO[50] |
set_property iostandard "LVCMOS18" [get_ports "MIO[50]"] |
set_property PACKAGE_PIN "D13" [get_ports "MIO[50]"] |
set_property slew "slow" [get_ports "MIO[50]"] |
set_property drive "8" [get_ports "MIO[50]"] |
set_property pullup "TRUE" [get_ports "MIO[50]"] |
# UART 1 / rx / MIO[49] |
set_property iostandard "LVCMOS18" [get_ports "MIO[49]"] |
set_property PACKAGE_PIN "C14" [get_ports "MIO[49]"] |
set_property slew "slow" [get_ports "MIO[49]"] |
set_property drive "8" [get_ports "MIO[49]"] |
set_property pullup "TRUE" [get_ports "MIO[49]"] |
# UART 1 / tx / MIO[48] |
set_property iostandard "LVCMOS18" [get_ports "MIO[48]"] |
set_property PACKAGE_PIN "D11" [get_ports "MIO[48]"] |
set_property slew "slow" [get_ports "MIO[48]"] |
set_property drive "8" [get_ports "MIO[48]"] |
set_property pullup "TRUE" [get_ports "MIO[48]"] |
# CAN 0 / tx / MIO[47] |
set_property iostandard "LVCMOS18" [get_ports "MIO[47]"] |
set_property PACKAGE_PIN "B10" [get_ports "MIO[47]"] |
set_property slew "slow" [get_ports "MIO[47]"] |
set_property drive "8" [get_ports "MIO[47]"] |
set_property pullup "TRUE" [get_ports "MIO[47]"] |
# CAN 0 / rx / MIO[46] |
set_property iostandard "LVCMOS18" [get_ports "MIO[46]"] |
set_property PACKAGE_PIN "D12" [get_ports "MIO[46]"] |
set_property slew "slow" [get_ports "MIO[46]"] |
set_property drive "8" [get_ports "MIO[46]"] |
set_property pullup "TRUE" [get_ports "MIO[46]"] |
# SD 0 / data[3] / MIO[45] |
set_property iostandard "LVCMOS18" [get_ports "MIO[45]"] |
set_property PACKAGE_PIN "B9" [get_ports "MIO[45]"] |
set_property slew "fast" [get_ports "MIO[45]"] |
set_property drive "8" [get_ports "MIO[45]"] |
set_property pullup "TRUE" [get_ports "MIO[45]"] |
# SD 0 / data[2] / MIO[44] |
set_property iostandard "LVCMOS18" [get_ports "MIO[44]"] |
set_property PACKAGE_PIN "E13" [get_ports "MIO[44]"] |
set_property slew "fast" [get_ports "MIO[44]"] |
set_property drive "8" [get_ports "MIO[44]"] |
set_property pullup "TRUE" [get_ports "MIO[44]"] |
# SD 0 / data[1] / MIO[43] |
set_property iostandard "LVCMOS18" [get_ports "MIO[43]"] |
set_property PACKAGE_PIN "B11" [get_ports "MIO[43]"] |
set_property slew "fast" [get_ports "MIO[43]"] |
set_property drive "8" [get_ports "MIO[43]"] |
set_property pullup "TRUE" [get_ports "MIO[43]"] |
# SD 0 / data[0] / MIO[42] |
set_property iostandard "LVCMOS18" [get_ports "MIO[42]"] |
set_property PACKAGE_PIN "D8" [get_ports "MIO[42]"] |
set_property slew "fast" [get_ports "MIO[42]"] |
set_property drive "8" [get_ports "MIO[42]"] |
set_property pullup "TRUE" [get_ports "MIO[42]"] |
# SD 0 / cmd / MIO[41] |
set_property iostandard "LVCMOS18" [get_ports "MIO[41]"] |
set_property PACKAGE_PIN "C8" [get_ports "MIO[41]"] |
set_property slew "fast" [get_ports "MIO[41]"] |
set_property drive "8" [get_ports "MIO[41]"] |
set_property pullup "TRUE" [get_ports "MIO[41]"] |
# SD 0 / clk / MIO[40] |
set_property iostandard "LVCMOS18" [get_ports "MIO[40]"] |
set_property PACKAGE_PIN "E14" [get_ports "MIO[40]"] |
set_property slew "fast" [get_ports "MIO[40]"] |
set_property drive "8" [get_ports "MIO[40]"] |
set_property pullup "TRUE" [get_ports "MIO[40]"] |
# USB 0 / data[7] / MIO[39] |
set_property iostandard "LVCMOS18" [get_ports "MIO[39]"] |
set_property PACKAGE_PIN "C13" [get_ports "MIO[39]"] |
set_property slew "fast" [get_ports "MIO[39]"] |
set_property drive "8" [get_ports "MIO[39]"] |
set_property pullup "TRUE" [get_ports "MIO[39]"] |
# USB 0 / data[6] / MIO[38] |
set_property iostandard "LVCMOS18" [get_ports "MIO[38]"] |
set_property PACKAGE_PIN "F13" [get_ports "MIO[38]"] |
set_property slew "fast" [get_ports "MIO[38]"] |
set_property drive "8" [get_ports "MIO[38]"] |
set_property pullup "TRUE" [get_ports "MIO[38]"] |
# USB 0 / data[5] / MIO[37] |
set_property iostandard "LVCMOS18" [get_ports "MIO[37]"] |
set_property PACKAGE_PIN "B14" [get_ports "MIO[37]"] |
set_property slew "fast" [get_ports "MIO[37]"] |
set_property drive "8" [get_ports "MIO[37]"] |
set_property pullup "TRUE" [get_ports "MIO[37]"] |
# USB 0 / clk / MIO[36] |
set_property iostandard "LVCMOS18" [get_ports "MIO[36]"] |
set_property PACKAGE_PIN "A9" [get_ports "MIO[36]"] |
set_property slew "fast" [get_ports "MIO[36]"] |
set_property drive "8" [get_ports "MIO[36]"] |
set_property pullup "TRUE" [get_ports "MIO[36]"] |
# USB 0 / data[3] / MIO[35] |
set_property iostandard "LVCMOS18" [get_ports "MIO[35]"] |
set_property PACKAGE_PIN "F14" [get_ports "MIO[35]"] |
set_property slew "fast" [get_ports "MIO[35]"] |
set_property drive "8" [get_ports "MIO[35]"] |
set_property pullup "TRUE" [get_ports "MIO[35]"] |
# USB 0 / data[2] / MIO[34] |
set_property iostandard "LVCMOS18" [get_ports "MIO[34]"] |
set_property PACKAGE_PIN "B12" [get_ports "MIO[34]"] |
set_property slew "fast" [get_ports "MIO[34]"] |
set_property drive "8" [get_ports "MIO[34]"] |
set_property pullup "TRUE" [get_ports "MIO[34]"] |
# USB 0 / data[1] / MIO[33] |
set_property iostandard "LVCMOS18" [get_ports "MIO[33]"] |
set_property PACKAGE_PIN "G13" [get_ports "MIO[33]"] |
set_property slew "fast" [get_ports "MIO[33]"] |
set_property drive "8" [get_ports "MIO[33]"] |
set_property pullup "TRUE" [get_ports "MIO[33]"] |
# USB 0 / data[0] / MIO[32] |
set_property iostandard "LVCMOS18" [get_ports "MIO[32]"] |
set_property PACKAGE_PIN "C7" [get_ports "MIO[32]"] |
set_property slew "fast" [get_ports "MIO[32]"] |
set_property drive "8" [get_ports "MIO[32]"] |
set_property pullup "TRUE" [get_ports "MIO[32]"] |
# USB 0 / nxt / MIO[31] |
set_property iostandard "LVCMOS18" [get_ports "MIO[31]"] |
set_property PACKAGE_PIN "F9" [get_ports "MIO[31]"] |
set_property slew "fast" [get_ports "MIO[31]"] |
set_property drive "8" [get_ports "MIO[31]"] |
set_property pullup "TRUE" [get_ports "MIO[31]"] |
# USB 0 / stp / MIO[30] |
set_property iostandard "LVCMOS18" [get_ports "MIO[30]"] |
set_property PACKAGE_PIN "A11" [get_ports "MIO[30]"] |
set_property slew "fast" [get_ports "MIO[30]"] |
set_property drive "8" [get_ports "MIO[30]"] |
set_property pullup "TRUE" [get_ports "MIO[30]"] |
# USB 0 / dir / MIO[29] |
set_property iostandard "LVCMOS18" [get_ports "MIO[29]"] |
set_property PACKAGE_PIN "E8" [get_ports "MIO[29]"] |
set_property slew "fast" [get_ports "MIO[29]"] |
set_property drive "8" [get_ports "MIO[29]"] |
set_property pullup "TRUE" [get_ports "MIO[29]"] |
# USB 0 / data[4] / MIO[28] |
set_property iostandard "LVCMOS18" [get_ports "MIO[28]"] |
set_property PACKAGE_PIN "A12" [get_ports "MIO[28]"] |
set_property slew "fast" [get_ports "MIO[28]"] |
set_property drive "8" [get_ports "MIO[28]"] |
set_property pullup "TRUE" [get_ports "MIO[28]"] |
# Enet 0 / rx_ctl / MIO[27] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[27]"] |
set_property PACKAGE_PIN "D7" [get_ports "MIO[27]"] |
set_property slew "fast" [get_ports "MIO[27]"] |
set_property pullup "TRUE" [get_ports "MIO[27]"] |
# Enet 0 / rxd[3] / MIO[26] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[26]"] |
set_property PACKAGE_PIN "A13" [get_ports "MIO[26]"] |
set_property slew "fast" [get_ports "MIO[26]"] |
set_property pullup "TRUE" [get_ports "MIO[26]"] |
# Enet 0 / rxd[2] / MIO[25] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[25]"] |
set_property PACKAGE_PIN "F12" [get_ports "MIO[25]"] |
set_property slew "fast" [get_ports "MIO[25]"] |
set_property pullup "TRUE" [get_ports "MIO[25]"] |
# Enet 0 / rxd[1] / MIO[24] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[24]"] |
set_property PACKAGE_PIN "B7" [get_ports "MIO[24]"] |
set_property slew "fast" [get_ports "MIO[24]"] |
set_property pullup "TRUE" [get_ports "MIO[24]"] |
# Enet 0 / rxd[0] / MIO[23] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[23]"] |
set_property PACKAGE_PIN "E11" [get_ports "MIO[23]"] |
set_property slew "fast" [get_ports "MIO[23]"] |
set_property pullup "TRUE" [get_ports "MIO[23]"] |
# Enet 0 / rx_clk / MIO[22] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[22]"] |
set_property PACKAGE_PIN "A14" [get_ports "MIO[22]"] |
set_property slew "fast" [get_ports "MIO[22]"] |
set_property pullup "TRUE" [get_ports "MIO[22]"] |
# Enet 0 / tx_ctl / MIO[21] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[21]"] |
set_property PACKAGE_PIN "F11" [get_ports "MIO[21]"] |
set_property slew "fast" [get_ports "MIO[21]"] |
set_property pullup "TRUE" [get_ports "MIO[21]"] |
# Enet 0 / txd[3] / MIO[20] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[20]"] |
set_property PACKAGE_PIN "A8" [get_ports "MIO[20]"] |
set_property slew "fast" [get_ports "MIO[20]"] |
set_property pullup "TRUE" [get_ports "MIO[20]"] |
# Enet 0 / txd[2] / MIO[19] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[19]"] |
set_property PACKAGE_PIN "E10" [get_ports "MIO[19]"] |
set_property slew "fast" [get_ports "MIO[19]"] |
set_property pullup "TRUE" [get_ports "MIO[19]"] |
# Enet 0 / txd[1] / MIO[18] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[18]"] |
set_property PACKAGE_PIN "A7" [get_ports "MIO[18]"] |
set_property slew "fast" [get_ports "MIO[18]"] |
set_property pullup "TRUE" [get_ports "MIO[18]"] |
# Enet 0 / txd[0] / MIO[17] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[17]"] |
set_property PACKAGE_PIN "E9" [get_ports "MIO[17]"] |
set_property slew "fast" [get_ports "MIO[17]"] |
set_property pullup "TRUE" [get_ports "MIO[17]"] |
# Enet 0 / tx_clk / MIO[16] |
set_property iostandard "HSTL_I_18" [get_ports "MIO[16]"] |
set_property PACKAGE_PIN "D6" [get_ports "MIO[16]"] |
set_property slew "fast" [get_ports "MIO[16]"] |
set_property pullup "TRUE" [get_ports "MIO[16]"] |
# SD 0 / wp / MIO[15] |
set_property iostandard "LVCMOS18" [get_ports "MIO[15]"] |
set_property PACKAGE_PIN "E6" [get_ports "MIO[15]"] |
set_property slew "fast" [get_ports "MIO[15]"] |
set_property drive "8" [get_ports "MIO[15]"] |
set_property pullup "TRUE" [get_ports "MIO[15]"] |
# GPIO / gpio[14] / MIO[14] |
set_property iostandard "LVCMOS18" [get_ports "MIO[14]"] |
set_property PACKAGE_PIN "B6" [get_ports "MIO[14]"] |
set_property slew "slow" [get_ports "MIO[14]"] |
set_property drive "8" [get_ports "MIO[14]"] |
set_property pullup "TRUE" [get_ports "MIO[14]"] |
# GPIO / gpio[13] / MIO[13] |
set_property iostandard "LVCMOS18" [get_ports "MIO[13]"] |
set_property PACKAGE_PIN "A6" [get_ports "MIO[13]"] |
set_property slew "slow" [get_ports "MIO[13]"] |
set_property drive "8" [get_ports "MIO[13]"] |
set_property pullup "TRUE" [get_ports "MIO[13]"] |
# GPIO / gpio[12] / MIO[12] |
set_property iostandard "LVCMOS18" [get_ports "MIO[12]"] |
set_property PACKAGE_PIN "C5" [get_ports "MIO[12]"] |
set_property slew "slow" [get_ports "MIO[12]"] |
set_property drive "8" [get_ports "MIO[12]"] |
set_property pullup "TRUE" [get_ports "MIO[12]"] |
# GPIO / gpio[11] / MIO[11] |
set_property iostandard "LVCMOS18" [get_ports "MIO[11]"] |
set_property PACKAGE_PIN "B4" [get_ports "MIO[11]"] |
set_property slew "slow" [get_ports "MIO[11]"] |
set_property drive "8" [get_ports "MIO[11]"] |
set_property pullup "TRUE" [get_ports "MIO[11]"] |
# GPIO / gpio[10] / MIO[10] |
set_property iostandard "LVCMOS18" [get_ports "MIO[10]"] |
set_property PACKAGE_PIN "G7" [get_ports "MIO[10]"] |
set_property slew "slow" [get_ports "MIO[10]"] |
set_property drive "8" [get_ports "MIO[10]"] |
set_property pullup "TRUE" [get_ports "MIO[10]"] |
# GPIO / gpio[9] / MIO[9] |
set_property iostandard "LVCMOS18" [get_ports "MIO[9]"] |
set_property PACKAGE_PIN "C4" [get_ports "MIO[9]"] |
set_property slew "slow" [get_ports "MIO[9]"] |
set_property drive "8" [get_ports "MIO[9]"] |
set_property pullup "TRUE" [get_ports "MIO[9]"] |
# Quad SPI Flash / qspi_fbclk / MIO[8] |
set_property iostandard "LVCMOS18" [get_ports "MIO[8]"] |
set_property PACKAGE_PIN "E5" [get_ports "MIO[8]"] |
set_property slew "slow" [get_ports "MIO[8]"] |
set_property drive "8" [get_ports "MIO[8]"] |
# GPIO / gpio[7] / MIO[7] |
set_property iostandard "LVCMOS18" [get_ports "MIO[7]"] |
set_property PACKAGE_PIN "D5" [get_ports "MIO[7]"] |
set_property slew "slow" [get_ports "MIO[7]"] |
set_property drive "8" [get_ports "MIO[7]"] |
# Quad SPI Flash / qspi0_sclk / MIO[6] |
set_property iostandard "LVCMOS18" [get_ports "MIO[6]"] |
set_property PACKAGE_PIN "A4" [get_ports "MIO[6]"] |
set_property slew "fast" [get_ports "MIO[6]"] |
set_property drive "8" [get_ports "MIO[6]"] |
# Quad SPI Flash / qspi0_io[3] / MIO[5] |
set_property iostandard "LVCMOS18" [get_ports "MIO[5]"] |
set_property PACKAGE_PIN "A3" [get_ports "MIO[5]"] |
set_property slew "fast" [get_ports "MIO[5]"] |
set_property drive "8" [get_ports "MIO[5]"] |
# Quad SPI Flash / qspi0_io[2] / MIO[4] |
set_property iostandard "LVCMOS18" [get_ports "MIO[4]"] |
set_property PACKAGE_PIN "E4" [get_ports "MIO[4]"] |
set_property slew "fast" [get_ports "MIO[4]"] |
set_property drive "8" [get_ports "MIO[4]"] |
# Quad SPI Flash / qspi0_io[1] / MIO[3] |
set_property iostandard "LVCMOS18" [get_ports "MIO[3]"] |
set_property PACKAGE_PIN "F6" [get_ports "MIO[3]"] |
set_property slew "fast" [get_ports "MIO[3]"] |
set_property drive "8" [get_ports "MIO[3]"] |
# Quad SPI Flash / qspi0_io[0] / MIO[2] |
set_property iostandard "LVCMOS18" [get_ports "MIO[2]"] |
set_property PACKAGE_PIN "A2" [get_ports "MIO[2]"] |
set_property slew "fast" [get_ports "MIO[2]"] |
set_property drive "8" [get_ports "MIO[2]"] |
# Quad SPI Flash / qspi0_ss_b / MIO[1] |
set_property iostandard "LVCMOS18" [get_ports "MIO[1]"] |
set_property PACKAGE_PIN "A1" [get_ports "MIO[1]"] |
set_property slew "fast" [get_ports "MIO[1]"] |
set_property drive "8" [get_ports "MIO[1]"] |
set_property pullup "TRUE" [get_ports "MIO[1]"] |
# SD 0 / cd / MIO[0] |
set_property iostandard "LVCMOS18" [get_ports "MIO[0]"] |
set_property PACKAGE_PIN "G6" [get_ports "MIO[0]"] |
set_property slew "fast" [get_ports "MIO[0]"] |
set_property drive "8" [get_ports "MIO[0]"] |
set_property pullup "TRUE" [get_ports "MIO[0]"] |
set_property iostandard "SSTL15" [get_ports "DDR_WEB"] |
set_property PACKAGE_PIN "R4" [get_ports "DDR_WEB"] |
set_property slew "FAST" [get_ports "DDR_WEB"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"] |
set_property PACKAGE_PIN "N7" [get_ports "DDR_VRP"] |
set_property slew "FAST" [get_ports "DDR_VRP"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"] |
set_property PACKAGE_PIN "M7" [get_ports "DDR_VRN"] |
set_property slew "FAST" [get_ports "DDR_VRN"] |
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"] |
set_property PACKAGE_PIN "R5" [get_ports "DDR_RAS_n"] |
set_property slew "FAST" [get_ports "DDR_RAS_n"] |
set_property iostandard "SSTL15" [get_ports "DDR_ODT"] |
set_property PACKAGE_PIN "P5" [get_ports "DDR_ODT"] |
set_property slew "FAST" [get_ports "DDR_ODT"] |
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"] |
set_property PACKAGE_PIN "F3" [get_ports "DDR_DRSTB"] |
set_property slew "FAST" [get_ports "DDR_DRSTB"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"] |
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQS[3]"] |
set_property slew "FAST" [get_ports "DDR_DQS[3]"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"] |
set_property PACKAGE_PIN "N2" [get_ports "DDR_DQS[2]"] |
set_property slew "FAST" [get_ports "DDR_DQS[2]"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"] |
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQS[1]"] |
set_property slew "FAST" [get_ports "DDR_DQS[1]"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"] |
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"] |
set_property slew "FAST" [get_ports "DDR_DQS[0]"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"] |
set_property PACKAGE_PIN "W2" [get_ports "DDR_DQS_n[3]"] |
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"] |
set_property PACKAGE_PIN "P2" [get_ports "DDR_DQS_n[2]"] |
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"] |
set_property PACKAGE_PIN "J2" [get_ports "DDR_DQS_n[1]"] |
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"] |
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"] |
set_property PACKAGE_PIN "D2" [get_ports "DDR_DQS_n[0]"] |
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"] |
set_property PACKAGE_PIN "G1" [get_ports "DDR_DQ[9]"] |
set_property slew "FAST" [get_ports "DDR_DQ[9]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"] |
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQ[8]"] |
set_property slew "FAST" [get_ports "DDR_DQ[8]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"] |
set_property PACKAGE_PIN "F1" [get_ports "DDR_DQ[7]"] |
set_property slew "FAST" [get_ports "DDR_DQ[7]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"] |
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQ[6]"] |
set_property slew "FAST" [get_ports "DDR_DQ[6]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"] |
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[5]"] |
set_property slew "FAST" [get_ports "DDR_DQ[5]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"] |
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[4]"] |
set_property slew "FAST" [get_ports "DDR_DQ[4]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"] |
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[3]"] |
set_property slew "FAST" [get_ports "DDR_DQ[3]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"] |
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DQ[31]"] |
set_property slew "FAST" [get_ports "DDR_DQ[31]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"] |
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[30]"] |
set_property slew "FAST" [get_ports "DDR_DQ[30]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"] |
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQ[2]"] |
set_property slew "FAST" [get_ports "DDR_DQ[2]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"] |
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[29]"] |
set_property slew "FAST" [get_ports "DDR_DQ[29]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"] |
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[28]"] |
set_property slew "FAST" [get_ports "DDR_DQ[28]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"] |
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[27]"] |
set_property slew "FAST" [get_ports "DDR_DQ[27]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"] |
set_property PACKAGE_PIN "AA1" [get_ports "DDR_DQ[26]"] |
set_property slew "FAST" [get_ports "DDR_DQ[26]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"] |
set_property PACKAGE_PIN "U1" [get_ports "DDR_DQ[25]"] |
set_property slew "FAST" [get_ports "DDR_DQ[25]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"] |
set_property PACKAGE_PIN "AA3" [get_ports "DDR_DQ[24]"] |
set_property slew "FAST" [get_ports "DDR_DQ[24]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"] |
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[23]"] |
set_property slew "FAST" [get_ports "DDR_DQ[23]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"] |
set_property PACKAGE_PIN "M2" [get_ports "DDR_DQ[22]"] |
set_property slew "FAST" [get_ports "DDR_DQ[22]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"] |
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQ[21]"] |
set_property slew "FAST" [get_ports "DDR_DQ[21]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"] |
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[20]"] |
set_property slew "FAST" [get_ports "DDR_DQ[20]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"] |
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[1]"] |
set_property slew "FAST" [get_ports "DDR_DQ[1]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"] |
set_property PACKAGE_PIN "T1" [get_ports "DDR_DQ[19]"] |
set_property slew "FAST" [get_ports "DDR_DQ[19]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"] |
set_property PACKAGE_PIN "N3" [get_ports "DDR_DQ[18]"] |
set_property slew "FAST" [get_ports "DDR_DQ[18]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"] |
set_property PACKAGE_PIN "T3" [get_ports "DDR_DQ[17]"] |
set_property slew "FAST" [get_ports "DDR_DQ[17]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"] |
set_property PACKAGE_PIN "M1" [get_ports "DDR_DQ[16]"] |
set_property slew "FAST" [get_ports "DDR_DQ[16]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"] |
set_property PACKAGE_PIN "K3" [get_ports "DDR_DQ[15]"] |
set_property slew "FAST" [get_ports "DDR_DQ[15]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"] |
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[14]"] |
set_property slew "FAST" [get_ports "DDR_DQ[14]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"] |
set_property PACKAGE_PIN "K1" [get_ports "DDR_DQ[13]"] |
set_property slew "FAST" [get_ports "DDR_DQ[13]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"] |
set_property PACKAGE_PIN "L3" [get_ports "DDR_DQ[12]"] |
set_property slew "FAST" [get_ports "DDR_DQ[12]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"] |
set_property PACKAGE_PIN "L2" [get_ports "DDR_DQ[11]"] |
set_property slew "FAST" [get_ports "DDR_DQ[11]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"] |
set_property PACKAGE_PIN "L1" [get_ports "DDR_DQ[10]"] |
set_property slew "FAST" [get_ports "DDR_DQ[10]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"] |
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[0]"] |
set_property slew "FAST" [get_ports "DDR_DQ[0]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"] |
set_property PACKAGE_PIN "AA2" [get_ports "DDR_DM[3]"] |
set_property slew "FAST" [get_ports "DDR_DM[3]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"] |
set_property PACKAGE_PIN "P1" [get_ports "DDR_DM[2]"] |
set_property slew "FAST" [get_ports "DDR_DM[2]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"] |
set_property PACKAGE_PIN "H3" [get_ports "DDR_DM[1]"] |
set_property slew "FAST" [get_ports "DDR_DM[1]"] |
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"] |
set_property PACKAGE_PIN "B1" [get_ports "DDR_DM[0]"] |
set_property slew "FAST" [get_ports "DDR_DM[0]"] |
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"] |
set_property PACKAGE_PIN "P6" [get_ports "DDR_CS_n"] |
set_property slew "FAST" [get_ports "DDR_CS_n"] |
set_property iostandard "SSTL15" [get_ports "DDR_CKE"] |
set_property PACKAGE_PIN "V3" [get_ports "DDR_CKE"] |
set_property slew "FAST" [get_ports "DDR_CKE"] |
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"] |
set_property PACKAGE_PIN "N4" [get_ports "DDR_Clk"] |
set_property slew "FAST" [get_ports "DDR_Clk"] |
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"] |
set_property PACKAGE_PIN "N5" [get_ports "DDR_Clk_n"] |
set_property slew "FAST" [get_ports "DDR_Clk_n"] |
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"] |
set_property PACKAGE_PIN "P3" [get_ports "DDR_CAS_n"] |
set_property slew "FAST" [get_ports "DDR_CAS_n"] |
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"] |
set_property PACKAGE_PIN "M6" [get_ports "DDR_BankAddr[2]"] |
set_property slew "FAST" [get_ports "DDR_BankAddr[2]"] |
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"] |
set_property PACKAGE_PIN "L6" [get_ports "DDR_BankAddr[1]"] |
set_property slew "FAST" [get_ports "DDR_BankAddr[1]"] |
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"] |
set_property PACKAGE_PIN "L7" [get_ports "DDR_BankAddr[0]"] |
set_property slew "FAST" [get_ports "DDR_BankAddr[0]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"] |
set_property PACKAGE_PIN "H5" [get_ports "DDR_Addr[9]"] |
set_property slew "FAST" [get_ports "DDR_Addr[9]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"] |
set_property PACKAGE_PIN "J5" [get_ports "DDR_Addr[8]"] |
set_property slew "FAST" [get_ports "DDR_Addr[8]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"] |
set_property PACKAGE_PIN "J6" [get_ports "DDR_Addr[7]"] |
set_property slew "FAST" [get_ports "DDR_Addr[7]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"] |
set_property PACKAGE_PIN "J7" [get_ports "DDR_Addr[6]"] |
set_property slew "FAST" [get_ports "DDR_Addr[6]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"] |
set_property PACKAGE_PIN "K5" [get_ports "DDR_Addr[5]"] |
set_property slew "FAST" [get_ports "DDR_Addr[5]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"] |
set_property PACKAGE_PIN "K6" [get_ports "DDR_Addr[4]"] |
set_property slew "FAST" [get_ports "DDR_Addr[4]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"] |
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[3]"] |
set_property slew "FAST" [get_ports "DDR_Addr[3]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"] |
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[2]"] |
set_property slew "FAST" [get_ports "DDR_Addr[2]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"] |
set_property PACKAGE_PIN "M5" [get_ports "DDR_Addr[1]"] |
set_property slew "FAST" [get_ports "DDR_Addr[1]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"] |
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[14]"] |
set_property slew "FAST" [get_ports "DDR_Addr[14]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"] |
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[13]"] |
set_property slew "FAST" [get_ports "DDR_Addr[13]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"] |
set_property PACKAGE_PIN "H4" [get_ports "DDR_Addr[12]"] |
set_property slew "FAST" [get_ports "DDR_Addr[12]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"] |
set_property PACKAGE_PIN "G5" [get_ports "DDR_Addr[11]"] |
set_property slew "FAST" [get_ports "DDR_Addr[11]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"] |
set_property PACKAGE_PIN "J3" [get_ports "DDR_Addr[10]"] |
set_property slew "FAST" [get_ports "DDR_Addr[10]"] |
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"] |
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[0]"] |
set_property slew "FAST" [get_ports "DDR_Addr[0]"] |
set_property iostandard "LVCMOS18" [get_ports "PS_PORB"] |
set_property PACKAGE_PIN "B5" [get_ports "PS_PORB"] |
set_property slew "fast" [get_ports "PS_PORB"] |
set_property drive "8" [get_ports "PS_PORB"] |
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"] |
set_property PACKAGE_PIN "C9" [get_ports "PS_SRSTB"] |
set_property slew "fast" [get_ports "PS_SRSTB"] |
set_property drive "8" [get_ports "PS_SRSTB"] |
set_property iostandard "LVCMOS18" [get_ports "PS_CLK"] |
set_property PACKAGE_PIN "F7" [get_ports "PS_CLK"] |
set_property slew "fast" [get_ports "PS_CLK"] |
set_property drive "8" [get_ports "PS_CLK"] |
/xps/data/zynq_bram.ucf
--- xps/cleanup.bat (nonexistent)
+++ xps/cleanup.bat (revision 20)
@@ -0,0 +1,3 @@
+rmdir /S /Q etc hdl synthesis implementation pcores simulation __xps
+del *.log *.opt *.cmd *.make *.bxml *.bmm *.v
+