URL
https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk
Subversion Repositories bustap-jtag
Compare Revisions
- This comparison shows the changes necessary to convert path
/bustap-jtag/trunk/rtl/altera
- from Rev 6 to Rev 9
- ↔ Reverse comparison
Rev 6 → Rev 9
/virtual_jtag_addr_mask.v
13,6 → 13,7
// Virtual JTAG. |
//************************************************************** |
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`include "../../sim/altera/jtag_sim_define.h" |
`timescale 1ns/1ns |
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module virtual_jtag_addr_mask(mask_out0 ,mask_out1 ,mask_out2 ,mask_out3 , |
164,8 → 165,8
sld_virtual_jtag_component.sld_auto_instance_index = "NO", |
sld_virtual_jtag_component.sld_instance_index = 1, |
sld_virtual_jtag_component.sld_ir_width = 2, |
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))", |
sld_virtual_jtag_component.sld_sim_n_scan = 1, |
sld_virtual_jtag_component.sld_sim_total_length = 2; |
sld_virtual_jtag_component.sld_sim_action = `ADDR_SLD_SIM_ACTION, |
sld_virtual_jtag_component.sld_sim_n_scan = `ADDR_SLD_SIM_N_SCAN, |
sld_virtual_jtag_component.sld_sim_total_length = `ADDR_SLD_SIM_T_LENG; |
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endmodule |
/virtual_jtag_adda_fifo.v
13,6 → 13,7
// via Virtual JTAG. |
//************************************************************** |
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`include "../../sim/altera/jtag_sim_define.h" |
`timescale 1ns/1ns |
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module virtual_jtag_adda_fifo(clk,wr_en,data_in); |
165,8 → 166,8
sld_virtual_jtag_component.sld_auto_instance_index = "NO", |
sld_virtual_jtag_component.sld_instance_index = 0, |
sld_virtual_jtag_component.sld_ir_width = 2, |
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))", |
sld_virtual_jtag_component.sld_sim_n_scan = 1, |
sld_virtual_jtag_component.sld_sim_total_length = 2; |
sld_virtual_jtag_component.sld_sim_action = `FIFO_SLD_SIM_ACTION, |
sld_virtual_jtag_component.sld_sim_n_scan = `FIFO_SLD_SIM_N_SCAN, |
sld_virtual_jtag_component.sld_sim_total_length = `FIFO_SLD_SIM_T_LENG; |
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endmodule |
/virtual_jtag_adda_trig.v
13,6 → 13,7
// via Virtual JTAG. |
//************************************************************** |
|
`include "../../sim/altera/jtag_sim_define.h" |
`timescale 1ns/1ns |
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module virtual_jtag_adda_trig(trig_out); |
92,8 → 93,8
sld_virtual_jtag_component.sld_auto_instance_index = "NO", |
sld_virtual_jtag_component.sld_instance_index = 2, |
sld_virtual_jtag_component.sld_ir_width = 2, |
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))", |
sld_virtual_jtag_component.sld_sim_n_scan = 1, |
sld_virtual_jtag_component.sld_sim_total_length = 2; |
sld_virtual_jtag_component.sld_sim_action = `TRIG_SLD_SIM_ACTION, |
sld_virtual_jtag_component.sld_sim_n_scan = `TRIG_SLD_SIM_N_SCAN, |
sld_virtual_jtag_component.sld_sim_total_length = `TRIG_SLD_SIM_T_LENG; |
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endmodule |