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URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

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  • This comparison shows the changes necessary to convert path 
    /bustap-jtag/trunk/rtl
    from Rev 10 to Rev 11
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  •

Rev 10 → Rev 11

/up_monitor.v
54,6 → 54,12
// for capture storage
wire [49:0] capture_in;
wire capture_wr;
// for pretrigger capture
wire [9:0] pretrig_num;
reg [9:0] pretrig_cnt;
wire pretrig_full;
wire pretrig_wr;
reg pretrig_wr_d1,pretrig_rd;
 
/////////////////////////////////////////////////
// Capture logic main
118,10 → 124,32
end
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
 
// generate capture wr-in
// generate capture wr_in
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
 
// generate pre-trigger wr_in
assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
always @(posedge clk)
begin
if (!trig_en || (trig_en && !trig_set)) begin
pretrig_cnt <= 10'd0;
pretrig_wr_d1<= 1'b0;
pretrig_rd <= 1'b0;
end
else if (!pretrig_full) begin
pretrig_cnt <= pretrig_cnt + addr_mask_ok;
pretrig_wr_d1<= 1'b0;
pretrig_rd <= 1'b0;
end
else if (pretrig_full) begin
pretrig_cnt <= pretrig_cnt;
pretrig_wr_d1<= pretrig_wr;
pretrig_rd <= pretrig_wr_d1;
end
end
 
/////////////////////////////////////////////////
// Instantiate vendor specific JTAG functions
/////////////////////////////////////////////////
129,8 → 157,9
// index 0, instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_en(capture_wr),
.data_in(capture_in)
.wr_in(capture_wr || pretrig_wr),
.data_in(capture_in),
.rd_in(pretrig_rd)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 50,
167,9 → 196,11
 
// index 2, instantiate capture trigger, as input
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
.trig_out(trig_cond)
.trig_out(trig_cond),
.pnum_out(pretrig_num)
);
defparam
u_virtual_jtag_adda_trig.trig_width = 56;
u_virtual_jtag_adda_trig.trig_width = 56,
u_virtual_jtag_adda_trig.pnum_width = 10;
 
endmodule
/altera/virtual_jtag_adda_fifo.v
16,7 → 16,7
`include "jtag_sim_define.h"
`timescale 1ns/1ns
 
module virtual_jtag_adda_fifo(clk,wr_en,data_in);
module virtual_jtag_adda_fifo(clk,wr_in,data_in,rd_in);
 
parameter data_width = 32,
fifo_depth = 256,
25,7 → 25,7
al_empt_val = 0;
 
input clk;
input wr_en;
input wr_in, rd_in;
input [data_width-1:0] data_in;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
50,7 → 50,8
reg read_instr_d1;
reg read_instr_d2;
reg read_instr_d3;
wire rd_en = read_instr_d2 & !read_instr_d3;
wire rd_en = rd_in | (read_instr_d2 & !read_instr_d3);
wire wr_en = wr_in;
always @(posedge clk or posedge reset)
begin
if (reset)
/altera/virtual_jtag_adda_trig.v
16,21 → 16,26
`include "jtag_sim_define.h"
`timescale 1ns/1ns
 
module virtual_jtag_adda_trig(trig_out);
module virtual_jtag_adda_trig(trig_out, pnum_out);
 
parameter trig_width = 32;
parameter pnum_width = 10;
 
output [trig_width-1:0] trig_out;
output [pnum_width-1:0] pnum_out;
 
reg [trig_width-1:0] trig_out;
reg [pnum_width-1:0] pnum_out;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [trig_width-1:0] trig_instr_reg;
reg [pnum_width-1:0] pnum_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
wire pnum_instr = ir_in[1] & ~ir_in[0]; // 2
 
always @(posedge tck)
begin
38,6 → 43,12
trig_out <= trig_instr_reg;
end
 
always @(posedge tck)
begin
if (pnum_instr && e1dr)
pnum_out <= pnum_instr_reg;
end
 
/* trig_instr Instruction Handler */
always @ (posedge tck)
if ( trig_instr && cdr )
45,15 → 56,24
else if ( trig_instr && sdr )
trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
 
/* pnum_instr Instruction Handler */
always @ (posedge tck)
if ( pnum_instr && cdr )
pnum_instr_reg <= pnum_instr_reg;
else if ( pnum_instr && sdr )
pnum_instr_reg <= {tdi, pnum_instr_reg[pnum_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg <= tdi;
 
/* Node TDO Output */
always @ ( trig_instr, trig_instr_reg, bypass_reg )
always @ ( trig_instr, trig_instr_reg, pnum_instr, pnum_instr_reg, bypass_reg )
begin
if (trig_instr)
if (trig_instr)
tdo <= trig_instr_reg[0];
else if (pnum_instr)
tdo <= pnum_instr_reg[0];
else
tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
end

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